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   <TITLE>FPGA-related Work</TITLE>
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<H1>FPGA-related Work</H1>
<UL>
  <LI><A HREF="ComputerSystemDesign.pdf">The TRM: Experiments in Computer System Design</A></LI><BR>
  <LI><A HREF="RISC.pdf">The Design of a RISC Architecture and its Implementation with an FPGA</A><BR>
    <A HREF="RISC0.v">[RISC0.v]</A>
    <A HREF="RISC0Top.v">[RISC0Top.v]</A>
    <A HREF="PROM.v">[PROM.v]</A>
    <A HREF="DRAM.v">[DRAM.v]</A>
    <A HREF="Multiplier.v">[Multiplier.v]</A>
    <A HREF="Multiplier1.v">[Multiplier1.v]</A>
    <A HREF="Divider.v">[Divider.v]</A>
    <A HREF="RISC0.ucf">[RISC0.ucf]</A>
    <A HREF="RS232R.v">[RS232R.v]</A>
    <A HREF="RS232T.v">[RS232T.v]</A><BR><BR>
    <A HREF="StandalonePrograms.Mod.txt">StandalonePrograms.Mod</A>
&nbsp;&nbsp;(See Project Oberon section for Oberon RISC compiler)<BR>
  </LI><BR>
  <LI><A HREF="RISC-Arch.pdf">RISC Architecture</A></LI><BR>
  <LI><A HREF="ThreeCounters.pdf">Three Counters</A>&nbsp;&nbsp;(See also Lola section)</LI><BR>
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