upd

people.inf.ethz.ch/wirth/FPGA-relatedWork/index.html

@@ -10,16 +10,16 @@
 <UL>
   <LI><A HREF="ComputerSystemDesign.pdf">The TRM: Experiments in Computer System Design</A></LI><BR>
   <LI><A HREF="RISC.pdf">The Design of a RISC Architecture and its Implementation with an FPGA</A><BR>
-    <A HREF="RISC0.v">[RISC0.v]</A>
-    <A HREF="RISC0Top.v">[RISC0Top.v]</A>
-    <A HREF="PROM.v">[PROM.v]</A>
-    <A HREF="DRAM.v">[DRAM.v]</A>
-    <A HREF="Multiplier.v">[Multiplier.v]</A>
-    <A HREF="Multiplier1.v">[Multiplier1.v]</A>
-    <A HREF="Divider.v">[Divider.v]</A>
-    <A HREF="RISC0.ucf">[RISC0.ucf]</A>
-    <A HREF="RS232R.v">[RS232R.v]</A>
-    <A HREF="RS232T.v">[RS232T.v]</A><BR><BR>
+    <A HREF="RISC0.v.html">[RISC0.v]</A>
+    <A HREF="RISC0Top.v.html">[RISC0Top.v]</A>
+    <A HREF="PROM.v.html">[PROM.v]</A>
+    <A HREF="DRAM.v.html">[DRAM.v]</A>
+    <A HREF="Multiplier.v.html">[Multiplier.v]</A>
+    <A HREF="Multiplier1.v.html">[Multiplier1.v]</A>
+    <A HREF="Divider.v.html">[Divider.v]</A>
+    <A HREF="RISC0.ucf.html">[RISC0.ucf]</A>
+    <A HREF="RS232R.v.html">[RS232R.v]</A>
+    <A HREF="RS232T.v.html">[RS232T.v]</A><BR><BR>
     <A HREF="StandalonePrograms.Mod.txt">StandalonePrograms.Mod</A>
 &nbsp;&nbsp;(See Project Oberon section for Oberon RISC compiler)<BR>
   </LI><BR>

people.inf.ethz.ch/wirth/Lola/index.html

@@ -50,7 +50,7 @@ Lola-2: A Logic Description Language</H1>
   <A HREF="Sources/SPI.Lola.txt">SPI.Lola</A>
   <A HREF="Sources/VID.Lola.txt">VID.Lola</A><BR><BR>
 &nbsp;&nbsp;
-  <A HREF="Sources/DCMX3.v">DCMX3.v</A>
+  <A HREF="Sources/DCMX3.v.html">DCMX3.v</A>
 <P></P><BR>
 <HR>
 <P>

people.inf.ethz.ch/wirth/ProjectOberon/index.html

@@ -74,29 +74,29 @@
   <A HREF="Sources/Stars.Mod.txt">Stars.Mod</A>
   <A HREF="Sources/Tools.Mod.txt">Tools.Mod</A>
 <HR>
-  <A HREF="SourcesVerilog/RISC5Top.v">RISC5Top.v</A>
-  <A HREF="SourcesVerilog/RISC5.v">RISC5.v</A>
-  <A HREF="SourcesVerilog/Registers.v">Registers.v</A>
-  <A HREF="SourcesVerilog/LeftShifter.v">LeftShifter.v</A>
-  <A HREF="SourcesVerilog/RightShifter.v">RightShifter.v</A>
-  <A HREF="SourcesVerilog/Multiplier.v">Multiplier.v</A>
-  <A HREF="SourcesVerilog/Divider.v">Divider.v</A>
-  <A HREF="SourcesVerilog/FPAdder.v">FPAdder.v</A>
-  <A HREF="SourcesVerilog/FPMultiplier.v">FPMultiplier.v</A>
-  <A HREF="SourcesVerilog/FPDivider.v">FPDivider.v</A>
-  <A HREF="SourcesVerilog/PROM.v">PROM.v</A>
-  <A HREF="SourcesVerilog/MouseP.v">MouseP.v</A>
-  <A HREF="SourcesVerilog/PS2.v">PS2.v</A>
-  <A HREF="SourcesVerilog/RS232T.v">RS232T.v</A>
-  <A HREF="SourcesVerilog/RS232R.v">RS232R.v</A>
-  <A HREF="SourcesVerilog/SPI.v">SPI.v</A>
+  <A HREF="SourcesVerilog/RISC5Top.v.html">RISC5Top.v</A>
+  <A HREF="SourcesVerilog/RISC5.v.html">RISC5.v</A>
+  <A HREF="SourcesVerilog/Registers.v.html">Registers.v</A>
+  <A HREF="SourcesVerilog/LeftShifter.v.html">LeftShifter.v</A>
+  <A HREF="SourcesVerilog/RightShifter.v.html">RightShifter.v</A>
+  <A HREF="SourcesVerilog/Multiplier.v.html">Multiplier.v</A>
+  <A HREF="SourcesVerilog/Divider.v.html">Divider.v</A>
+  <A HREF="SourcesVerilog/FPAdder.v.html">FPAdder.v</A>
+  <A HREF="SourcesVerilog/FPMultiplier.v.html">FPMultiplier.v</A>
+  <A HREF="SourcesVerilog/FPDivider.v.html">FPDivider.v</A>
+  <A HREF="SourcesVerilog/PROM.v.html">PROM.v</A>
+  <A HREF="SourcesVerilog/MouseP.v.html">MouseP.v</A>
+  <A HREF="SourcesVerilog/PS2.v.html">PS2.v</A>
+  <A HREF="SourcesVerilog/RS232T.v.html">RS232T.v</A>
+  <A HREF="SourcesVerilog/RS232R.v.html">RS232R.v</A>
+  <A HREF="SourcesVerilog/SPI.v.html">SPI.v</A>
   <A HREF="SourcesVerilog/VID.v">VID.v</A>
-  <A HREF="SourcesVerilog/RISC5.ucf">RISC5.ucf</A>
+  <A HREF="SourcesVerilog/RISC5.ucf.html">RISC5.ucf</A>
 <HR>
-  <A HREF="SourcesVerilog/RISC5a.v">RISC5a.v</A>
-  <A HREF="SourcesVerilog/Multiplier1.v">Multiplier1.v</A>
-  <A HREF="SourcesVerilog/Divider0.v">Divider0.v</A>
-  <A HREF="SourcesVerilog/MouseX.v">MouseX.v</A>
+  <A HREF="SourcesVerilog/RISC5a.v.html">RISC5a.v</A>
+  <A HREF="SourcesVerilog/Multiplier1.v.html">Multiplier1.v</A>
+  <A HREF="SourcesVerilog/Divider0.v.html">Divider0.v</A>
+  <A HREF="SourcesVerilog/MouseX.v.html">MouseX.v</A>
 <HR>
 <A HREF="license.txt">License</A>
 &nbsp;&nbsp;See also <A HREF="http://projectoberon.com">projectoberon.com</A>