|
@@ -8,7 +8,7 @@
|
|
|
|
|
|
|
|
<H1>FPGA-related Work</H1>
|
|
<H1>FPGA-related Work</H1>
|
|
|
<UL>
|
|
<UL>
|
|
|
- <LI><A HREF="ComputerSystemDesign.pdf">The TRM: Experiments in Computer System Design</A></LI><BR>
|
|
|
|
|
|
|
+ <LI><A HREF="https://www.inf.ethz.ch/personal/wirth/FPGA-relatedWork/ComputerSystemDesign.pdf">The TRM: Experiments in Computer System Design</A></LI><BR>
|
|
|
<LI><A HREF="RISC.pdf">The Design of a RISC Architecture and its Implementation with an FPGA</A><BR>
|
|
<LI><A HREF="RISC.pdf">The Design of a RISC Architecture and its Implementation with an FPGA</A><BR>
|
|
|
<A HREF="RISC0.v">[RISC0.v]</A>
|
|
<A HREF="RISC0.v">[RISC0.v]</A>
|
|
|
<A HREF="RISC0Top.v">[RISC0Top.v]</A>
|
|
<A HREF="RISC0Top.v">[RISC0Top.v]</A>
|
