выполнил первый код из файла bootstrap

разбор самих инструкций выполняется в конструкторах операций, для
исполнения операций использую кэш замыканий с конкретными действиями или
просто замыкания.

lib/halt.dart

@@ -12,7 +12,7 @@ class halt implements Exception{
 
   static on({bool condition: false, int code: 100, msg}){
     if(!condition){
-      throw new halt._new(code, msg);
+      throw new halt._new(code, msg == null ? "" : msg);
     }
   }
 }

lib/machine/host.dart

@@ -40,7 +40,7 @@ class Host {
   bool stop = false;
   MMU mem;
   CPU proc;
-  
+
   void run(){
     Function step;
     step = () {
@@ -48,13 +48,13 @@ class Host {
     };
     step();
   }
-  
+
   Host() {
     mem = new DebugMMU(MemFactory.newMMU(bootPC, memLength));
-    proc = ProcFactory.newCPU(mem, pc: i27(bootPC ~/ 3));
+    proc = ProcFactory.newCPU(mem, pc: long(bootPC ~/ 3));
     /* инициализируем константы машины */
-    new Mapper(mem)[memLim ~/ 3] = i27(mem.length);
-    new Mapper(mem)[heapOrg ~/ 3] = i27(heap);
+    new Mapper(mem)[memLim ~/ 3] = long(mem.length);
+    new Mapper(mem)[heapOrg ~/ 3] = long(heap);
     proc.reset();
     proc.debug = true;
   }

lib/tri/mathe.dart

@@ -1,6 +1,7 @@
 library tri;
 
 import 'dart:math';
+import 'package:tri/halt.dart';
 
 part 'tri.dart';
 part 'int.dart';
@@ -82,19 +83,23 @@ Tril mod(Tril x) {
   return x | ~x;
 }
 
-tryte short(int27 i) {
-  Trits from = new Trits(i).extract(0, 9);
-  return new tryte(from.toInt27().toInt());
+tryte short(i) {
+  if(i is int27){
+    Trits from = new Trits(i).extract(0, 9);
+    return new tryte(from.toInt27().toInt());
+  }else if(i is int){
+    return new tryte(i);
+  }else{
+    halt.on();
+  }
 }
 
-int27 long(tryte t) {
-  return new int27(t.toInt());
+int27 long(t) {
+  if(t is tryte)
+    return new int27(t.toInt());
+  else if(t is int)
+    return new int27(t);
+  else
+    halt.on();
 }
 
-int27 i27(int x){
-  return new int27(x);
-}
-
-tryte i9(int x){
-  return new tryte(x);
-}

lib/trisc/alu.dart

@@ -2,22 +2,36 @@ part of trisc;
 
 abstract class Reg extends Operation{
   int27 _ir;
-  
+
   @override
   int27 get raw => _ir;
   Reg(this._ir);
 }
 
 class Reg3 extends Reg{
-  
-  Reg3(int27 ir):super(ir){
-    
+  tryte a;
+  tryte b;
+  tryte c;
+  tryte op;
+
+  Reg3(int27 ir) : super(ir){
+    a = short((ir << 3) >> 23);
+    b = short((ir << 7) >> 23);
+    op = short((ir << 11) >> 23);
+    c = short((ir << 23) >> 23);
   }
 }
 
 class Reg2 extends Reg{
-  
-  Reg2(int27 ir):super(ir){
-      
+  tryte a;
+  tryte b;
+  int27 im;
+  tryte op;
+
+  Reg2(int27 ir) : super(ir){
+    a = short((ir << 3) >> 23);
+    b = short((ir << 7) >> 23);
+    op = short((ir << 11) >> 23);
+    im = (ir << 15) >> 15;
     }
 }

lib/trisc/asm.dart

@@ -3,7 +3,7 @@ part of trisc;
 class asm{
   static final tryte reg3 = new tryte(1);
   static final tryte reg2 = -reg3;
-    
+
   static final tryte mov = new tryte(0);
   static final tryte lsl = new tryte(1);
   static final tryte ror = new tryte(2);
@@ -16,13 +16,13 @@ class asm{
   static final tryte mul = new tryte(9);
   static final tryte div = new tryte(10);
   static final tryte mod = -div;
-    
+
   static final tryte mem = new tryte(2);
   static final tryte stw = new tryte(3);
   static final tryte ldw = -stw;
   static final tryte stt = new tryte(5);
   static final tryte ldt = -stt;
-    
+
   static final tryte br = new tryte(3);
   static final tryte brr = new tryte(7);
   static final tryte brc = -brr;

lib/trisc/core.dart

@@ -9,5 +9,6 @@ part 'mem.dart';
 part 'proc.dart';
 part 'op.dart';
 part 'alu.dart';
+part 'reg.dart';
 
 final fmt = new Logger("trisc");

lib/trisc/op.dart

@@ -6,30 +6,58 @@ abstract class Operation{
 
 abstract class MemoryOperation extends Operation{
   int27 _ir;
+
   tryte a;
   tryte b;
   int27 offset;
-  
+
   @override
   int27 get raw => _ir;
-  
+
   MemoryOperation(this._ir){
-    
+    a = short((_ir << 3) >> 23);
+    b = short((_ir << 7) >> 23);
+    offset = (_ir << -11) >> 11;
+  }
+}
+
+class Condition{
+  bool link;
+  Tril jump;
+  Tril nz;
+  Tril eq;
+
+  Condition(tryte c){
+    Trits cond = new Trits(c);
+    link = cond[asm.lnk.toInt()].True;
+    jump = cond[asm.jmp.toInt()];
+    nz = cond[asm.nz.toInt()];
+    eq = cond[asm.eq.toInt()];
   }
 }
 
 abstract class BranchOperation extends Operation{
+
   int27 _ir;
-  
+
+  tryte c;
+  int27 offset;
+  int27 data;
+  Condition cond;
+
   @override
   int27 get raw => _ir;
-  
+
   BranchOperation(this._ir){
-    
+    c = short((_ir << 23) >>23);
+    offset = (_ir << 9) >> 9;
+    data = (_ir << 9) >> 13;
+    tryte cnd = short((_ir << 3) >> 21);
+    cond = new Condition(cnd);
   }
 }
 
-class GetWord extends MemoryOperation{  
+class GetWord extends MemoryOperation{
   GetWord(int27 ir) : super(ir);
 }
 
@@ -57,7 +85,7 @@ typedef Operation OperationFactory(int27 ir);
 
 class Op{
   static Map<tryte, Operation> cache = _init();
-  
+
   static Map _init(){
     Map<tryte, OperationFactory> ret = new Map();
     ret[asm.reg3] = (ir){return new Reg3(ir);};
@@ -70,7 +98,7 @@ class Op{
     ret[asm.brc] = (ir){return new BranchConst(ir);};
     return ret;
   }
-  
+
   static Operation parse(int27 ir){
     tryte format = short(ir >> 24);
     var op = cache[format];

lib/trisc/proc.dart

@@ -32,13 +32,18 @@ class ProcFactory{
 typedef CPUresult IRhandler(Operation op);
 
 class _cpu extends CPU{
+
+  Registers reg;
+  RAM mem;
+
   int27 ir;
   int27 pc;
+
   int step = 0;
+
   bool _debug = false;
 
   int27 start = new int27.zero();
-  RAM mem;
 
   @override
   bool get debug => _debug;
@@ -49,8 +54,28 @@ class _cpu extends CPU{
   }
 
   IRhandler handler(){
+    var rh = reg.handler();
+
+    var jump = (int27 to, bool link){
+      if(link)
+        reg[short(reg.length-1)] = to * long(3); /* регистры запоминают адрес в трайтах */
+      pc = to; /* сдвиг в словах */
+    };
+
+    var calc = (BranchOperation op, int27 adr){
+      if(op.cond.jump.True)
+        jump(adr, op.cond.link);
+    };
+
     var def = (Operation op){
-      
+      if(op is Reg)
+        return rh(op);
+      if(op is BranchReg){
+        calc(op, reg[op.c] ~/ long(3));
+        return CPUresult.ok;
+      }
+      else
+        halt.on(msg: op.runtimeType);
     };
     return def;
   }
@@ -63,13 +88,16 @@ class _cpu extends CPU{
       halt.on(condition: !debug, code: 146);
       return CPUresult.stop;
     }else{
-      return h(Op.parse(ir));
+      var ret = h(Op.parse(ir));
+      halt.on(condition: ret!=null);
+      return ret;
     }
   }
 
   @override
   void reset(){
     ir = new int27.zero();
+    reg = new Registers();
     pc = start;
   }
 

lib/trisc/reg.dart

@@ -0,0 +1,56 @@
+part of trisc;
+
+typedef void Computation(tryte ra, tryte rb, int27 im);
+
+class Registers{
+  Map<tryte, Computation> _cache = new Map();
+
+  List<int27> _r = new List(27);
+  int get length => _r.length;
+
+  Tril _nz = NULL;
+  Tril get nz => _nz;
+
+  void updateNZ(tryte adr){
+    int27 x = _r[adr.toInt()];
+    _nz = new Tril(x == long(0) ? null : (x > long(0)));
+  }
+
+  int27 operator[](tryte adr){
+    return _r[adr.toInt()];
+  }
+
+  operator[]=(tryte adr, int27 val){
+    _r[adr.toInt()] = val;
+  }
+
+  IRhandler handler(){
+    var def = (Operation op){
+      if(op is Reg3){
+        var comp = _cache[op.op];
+        halt.on(condition: comp != null, code: 126, msg: op.op);
+        comp(op.a, op.b, this[op.c]);
+        return CPUresult.ok;
+      }else if(op is Reg2){
+        var comp = _cache[op.op];
+        halt.on(condition: comp != null, code: 126, msg: op.op);
+        comp(op.a, op.b, op.im);
+        return CPUresult.ok;
+      }else
+        halt.on(msg: op.runtimeType);
+    };
+    return def;
+  }
+
+  void _init(){
+    _cache[asm.mov] = (tryte a, tryte b, int27 c){
+      this[a] = c;
+    };
+  }
+
+  Registers(){
+    _init();
+    for(int i = 0; i<_r.length; i++)
+      _r[i] = new int27.zero();
+  }
+}