Project-Oberon-BlackBox/BlackBox/Po/Files/RISC5Top.Lola.txt

MODULE RISC5Top(   (*NW 23.9.2015*)
  IN CLK50M: BIT;
  IN btn: [4] BIT;
  IN swi: BYTE;
  IN RxD: BIT;
  OUT TxD: BIT;
  OUT leds: BYTE;
  OUT SRce0, SRce1, SRwe, SRoe: BIT;  (*SRAM*)
  OUT SRbe: [4] BIT;
  OUT SRadr: [18] BIT;
  INOUT SRdat: WORD;
  IN MISO: [2] BIT;   (*SPI - SD card & network*)
  OUT SCLK, MOSI, SS: [2] BIT;
  OUT NEN: BIT;   (*network enable*)
  OUT hsync, vsync: BIT;   (*video control*)
  OUT RGB: [3] BIT;
  IN PS2C, PS2D: BIT;   (*keyboard*)
  INOUT msclk, msdat: BIT;
  INOUT gpio: BYTE);

(* I/O addresses:
  0  millisconds / --
  1  switches / LEDs
  2  RS232 data / data (start)
  3  RS232 status / control
  4  SPI data / data (start)
  5  SPI status / control
  6  PS2 keyboard data
  7  mouse
  8  general-purpose I/O data
  9  general-purpose I/O tri-state control *)

TYPE RISC5 := MODULE (
    IN clk, rst, stallX: BIT;
      inbus, codebus: WORD;
    OUT adr: [24] BIT;
      rd, wr, ben: BIT;
      outbus: WORD) ^;

  RS232R := MODULE (
    IN clk, rst, done, RxD, fsel: BIT;
    OUT rdy: BIT; data: BYTE) ^;

  RS232T := MODULE (
    IN clk, rst, start, fsel: BIT; data: BYTE;
    OUT rdy, TxD: BIT) ^;

  SPI := MODULE (
    IN clk, rst, start, fast: BIT; dataTx: WORD;
    OUT dataRx: WORD; rdy: BIT;
    IN MISO: BIT; 
    OUT MOSI, SCLK: BIT)  ^;

  VID := MODULE (
    IN clk, inv: BIT; viddata: WORD;
    OUT req: BIT; vidadr: [18] BIT;
      hsync, vsync: BIT; RGB: [3] BIT) ^;

  MouseP := MODULE ( 
    IN clk, rst: BIT;
    INOUT msclk, msdat: BIT;
    OUT out: [28] BIT) ^;

  PS2 = MODULE (
    IN clk, rst, done: BIT;
    OUT rdy, shift: BIT; data: BYTE;
    IN PS2C, PS2D: BIT) ^;

REG (CLK50M) clk: BIT;
REG (clk) rst: BIT;
  bitrate: BIT;   (*RS-232*)
  Lreg: BYTE;  (*LED*)
  cnt0: [16] BIT;
  cnt1: WORD;  (*milliseconds*)
  spiCtrl: [4] BIT;
  gpout, gpoc: BYTE;

VAR riscx: RISC5;
  receiver: RS232R;
  transmitter: RS232T;
  spi: SPI;  (*CD-ROM and net*)
  vid: VID;
  kbd: PS2;
  Ms: MouseP;

  dmy: BIT;
  adr: [24] BIT;
  iowadr: [4] BIT;  (*word adress*)
  rd, wr, ben, ioenb, dspreq: BIT;
  be0, be1: BIT;
  inbus, inbus0: WORD;  (*data to RISC6 core*)
  outbus: WORD;   (*data from RISC6 core*)

  dataTx, dataRx, dataKbd: BYTE;
  rdyRx, doneRx, startTx, rdyTx, rdyKbd, doneKbd: BIT;
  dataMs: [28] BIT;   (*mouse*)
  limit: BIT;   (*of cnt0*)
  spiRx: WORD;
  spiStart, spiRdy, MOSI1, SCLK1: BIT;
  vidadr: [18] BIT;
  gpin: BYTE;

BEGIN
  riscx (clk, rst, dspreq, inbus, inbus0, adr, rd, wr, ben, outbus);
  receiver (clk, rst, doneRx, RxD, bitrate, rdyRx, dataRx);
  transmitter (clk, rst, startTx, bitrate, dataTx, rdyTx, TxD);
  spi (clk, rst, spiStart, spiCtrl.2, outbus, spiRx, spiRdy, MISO.0 & MISO.1, MOSI1, SCLK1); 
  vid (clk, swi.7, inbus0, dspreq, vidadr, hsync, vsync, RGB);
  kbd (clk, rst, doneKbd, rdyKbd, dmy, dataKbd, PS2C, PS2D);
  Ms (clk, rst, msclk, msdat, dataMs);
  TS(SRdat, inbus0, outbus, ~wr);
  TS(gpio, gpin, gpout, gpoc);

  iowadr := adr[5:2];
  ioenb := (adr[23:6] = 3FFFFH'18);
  inbus := ~ioenb -> inbus0 :
    ((iowadr = 0) -> cnt1 :
    (iowadr = 1) -> {0'20, btn, swi} :
    (iowadr = 2) -> {0'24, dataRx} :
    (iowadr = 3) -> {0'30, rdyTx, rdyRx} :
    (iowadr = 4) -> spiRx :
    (iowadr = 5) -> {0'31, spiRdy} :
    (iowadr = 6) -> {0'3, rdyKbd, dataMs} :
    (iowadr = 7) -> {0'24, dataKbd} :
    (iowadr = 8) -> {0'24, gpin} :
    (iowadr = 9) -> {0'24, gpoc} : 0'32);

(*access to SRAM*)
  be0 := ben & adr.0;
  be1 := ben & ~adr.0;
  SRce0 := ben & adr.1;
  SRce1 := ben & ~adr.1;
  SRwe := ~wr | clk;
  SRoe := wr;
  SRbe := {be1, be0, be1, be0};
  SRadr := dspreq -> vidadr : adr[19:2];

  dataTx := outbus[7:0];
  startTx := wr & ioenb & (iowadr = 2);
  doneRx := rd & ioenb & (iowadr = 2);
  spiStart := wr & ioenb & (iowadr = 4);
  doneKbd := rd & ioenb & (iowadr = 7);
  limit := (cnt0 = 24999);
  leds := Lreg;
  SS := ~spiCtrl[1:0];   (*active low slave select*)
  MOSI := {MOSI1, MOSI1}; SCLK := {SCLK1, SCLK1};
  NEN := spiCtrl[3];

  rst := (cnt1[4:0] = 0'5) & limit -> ~btn[3] : rst;
  Lreg := ~rst -> 0 : (wr & ioenb & (iowadr = 1)) -> outbus[7:0] : Lreg;
  spiCtrl := ~rst -> 0 : (wr & ioenb & (iowadr = 5)) -> outbus[3:0] : spiCtrl;
  bitrate := ~rst -> 0 : (wr & ioenb & (iowadr = 3)) -> outbus[0] : bitrate;
  gpout := ~rst -> 0 : (wr & ioenb & (iowadr = 8)) -> outbus[7:0] : gpout;
  gpoc := ~rst -> 0 : (wr & ioenb & (iowadr = 9)) -> outbus[7:0] : gpoc;
  cnt0 := limit -> 0 : cnt0 + 1;
  cnt1 := cnt1 + limit;

  clk := ~clk  (* @ 50 MHz *)
END RISC5Top.