synchronized with original

BlackBox/Po/Files/Display.Mod.txt

@@ -1,4 +1,4 @@
-MODULE Display;  (*NW 5.11.2013*)
+MODULE Display;  (*NW 5.11.2013 / 3.7.2016*)
   IMPORT SYSTEM;
 
   CONST black* = 0; white* = 1;  (*black = background*)
@@ -48,7 +48,7 @@ MODULE Display;  (*NW 5.11.2013*)
         ELSE (* (mode = paint) OR (mode = replace) & (col # black) *) SYSTEM.PUT(a1, pix + mid)
         END
       END
-    ELSE
+    ELSIF ar > al THEN
       left := {(x MOD 32) .. 31}; right := {0 .. ((x+w-1) MOD 32)};
       FOR a0 := al TO al + (h-1)*128 BY 128 DO
         SYSTEM.GET(a0, pixl); SYSTEM.GET(ar, pixr);
@@ -167,7 +167,7 @@ MODULE Display;  (*NW 5.11.2013*)
         SYSTEM.GET(a1, pix); SYSTEM.GET(pta0, ptw); SYSTEM.PUT(a1, (pix - mid) + (pix/ptw * mid)); INC(pta0, 4);
         IF pta0 = pta1 THEN pta0 := patadr+4 END
       END
-    ELSE
+    ELSIF ar > al THEN
       left := {(x MOD 32) .. 31}; right := {0 .. ((x+w-1) MOD 32)};
       FOR a0 := al TO al + (h-1)*128 BY 128 DO
         SYSTEM.GET(a0, pixl); SYSTEM.GET(pta0, ptw); SYSTEM.PUT(a0, (pixl - left) + (pixl/ptw * left));

BlackBox/Po/Files/FPDivider.Lola.txt

@@ -1,36 +1,38 @@
-MODULE FPDivider(   (*NW 19.9.2015*)
+MODULE FPDivider(   (*NW 9.9.2016*)
   IN clk, run: BIT; x, y: WORD;
   OUT stall: BIT; z: WORD);
 
   REG (clk) S: [5] BIT;   (*state*)
     R: [24] BIT;   (*remainder*)
-    Q: [25] BIT;   (*quotient*)
+    Q: [26] BIT;   (*quotient*)
 
   VAR sign: BIT;
     xe, ye: [8] BIT;
     e0, e1: [9] BIT;
-    z0: [24] BIT;
-    r0, r1, d, q0: [25] BIT;
+    r0,  r1, d: [25] BIT;
+    q0: [26] BIT;
+    z0, z1: [25] BIT;
 
 BEGIN
   sign := x.31 ^ y.31;   (*xor*)
   xe := x[30:23]; ye := y[30:23];
   e0 := {0'1, xe} - {0'1, ye};
-  e1 := e0 + 126 + Q.24;
-  stall := run & (S # 25);
+  e1 := e0 + 126 + Q.25;
+  stall := run & (S # 26);
 
   r0 := (S = 0) -> {1'2, x[22:0]} : {R, 0'1};
+  r1 := d.24 -> 0 : d;
   d := r0 - {1'2, y[22:0]};
-  r1 := d.24 -> r0 : d;
   q0 := (S = 0) -> 0 : Q;
 
-  z0 := Q.24 -> Q[24:1] : Q[23:0];  (*post norm*)
+  z0 := Q.25 -> Q[25:1] : Q[24:0];  (* normalize*)
+  z1 := z0 + 1;   (*round*)
   z := (xe = 0) -> 0 :
     (ye = 0) -> {sign, 0FFH'8, 0'23} :  (*divide by 0*)
-    ~e1.8 -> {sign, e1[7:0], z0[22:0]} :
-    ~e1.7 -> {sign, 0FFH'8, z0[22:0]} : 0;   (*overflow*)
+    ~e1.8 -> {sign, e1[7:0], z1[23:1]} :
+    ~e1.7 -> {sign, 0FFH'8, z0[23:1]} : 0;   (*overflow*)
 
   R := r1[23:0];
-  Q := {q0[23:0], ~d.24};
+  Q := {q0[24:0], ~d.24};
   S := run -> S+1 : 0
 END FPDivider.

BlackBox/Po/Files/FPDivider.v

@@ -1,4 +1,4 @@
-`timescale 1ns / 1ps   // NW 18.9.2015
+`timescale 1ns / 1ps   // NW 16.9.2016
 
 module FPDivider(
     input clk, run,
@@ -9,35 +9,37 @@ module FPDivider(
 
 reg [4:0] S;  // state
 reg [23:0] R;
-reg [24:0] Q;
+reg [25:0] Q;
 
 wire sign;
 wire [7:0] xe, ye;
 wire [8:0] e0, e1;
-wire [24:0] r0, r1, d, q0;
-wire [23:0] z0;
+wire [24:0] r0, r1, d;
+wire [25:0] q0;
+wire [24:0] z0, z1;
 
 assign sign = x[31]^y[31];
 assign xe = x[30:23];
 assign ye = y[30:23];
 assign e0 = {1'b0, xe} - {1'b0, ye};
-assign e1 = e0 + 126 + Q[24];
-assign stall = run & ~(S == 25);
+assign e1 = e0 + 126 + Q[25];
+assign stall = run & ~(S == 26);
 
-assign r0 = (S == 0) ? {2'b1, x[22:0]} : {R, 1'b0};
-assign d = r0 - {2'b1, y[22:0]};
+assign r0 = (S == 0) ? {2'b01, x[22:0]} : {R, 1'b0};
 assign r1 = d[24] ? r0 : d;
+assign d = r0 - {2'b01, y[22:0]};
 assign q0 = (S == 0) ? 0 : Q;
 
-assign z0 = Q[24] ? Q[24:1] : Q[23:0];
+assign z0 = Q[25] ? Q[25:1] : Q[24:0];
+assign z1 = z0 + 1;
 assign z = (xe == 0) ? 0 :
-  (ye == 0) ? {sign, 8'b11111111, 23'b0} :
-  (~e1[8]) ? {sign, e1[7:0], z0[22:0]} :
-  (~e1[7]) ? {sign, 8'b11111111, z0[22:0]} : 0;
+  (ye == 0) ? {sign, 8'b11111111, 23'b0} :  // div by 0
+  (~e1[8]) ? {sign, e1[7:0], z1[23:1]} :
+  (~e1[7]) ? {sign, 8'b11111111, z0[23:1]} : 0;  // NaN
 
 always @ (posedge(clk)) begin
   R <= r1[23:0];
-  Q <= {q0[23:0], ~d[24]};
+  Q <= {q0[24:0], ~d[24]};
   S <= run ? S+1 : 0;
 end
 endmodule

BlackBox/Po/Files/FPMultiplier.Lola.txt

@@ -8,8 +8,8 @@ MODULE FPMultiplier(   (*NW 15.9.2015*)
   VAR sign: BIT;
     xe, ye: [8] BIT;
     e0, e1: [9] BIT;
-    w0, z0: [24] BIT;
-    w1: [25] BIT;
+    w0: [24] BIT;
+    w1, z0: [25] BIT;
 
 BEGIN sign := x.31 ^ y.31;   (*xor*)
   xe := x[30:23]; ye := y[30:23];
@@ -22,8 +22,41 @@ BEGIN sign := x.31 ^ y.31;   (*xor*)
   P := (S = 0) -> {0'24, 1'1, x[22:0]} : {w1, P[23:1]};
   S := run -> S+1 : 0;
 
-  z0 := P.47 -> P[47:24] : P[46:23];  (*post norm*)
+  z0 := P.47 -> P[47:23]+1 : P[46:22]+1;  (*round & normalize*)
+  z := (xe = 0) | (ye = 0) -> 0 :
+    ~e1.8 -> {sign, e1[7:0], z0[23:1]} :
+    ~e1.7 -> {sign, 0FFH'8, z0[23:1]} : 0;  (*overflow*)
+END FPMultiplier.
+
+MODULE FPMultiplier(
+  IN clk, run: BIT; x, y: WORD;
+  OUT stall: BIT; z: WORD);
+
+  REG (clk) S: [5] BIT;   (*state*)
+    B2, A2: [24] BIT;
+
+  VAR sign: BIT;
+    xe, ye: [8] BIT;
+    e0, e1: [9] BIT;
+    B0: [25] BIT;
+    B00, B01, B1, A1, A0, z0: [24] BIT;
+
+BEGIN sign := x.31 ^ y.31;   (*xor*)
+  xe := x[30:23]; ye := y[30:23]; e0 := {0'1, xe} + {0'1, ye};
+  B00 := (S = 0) -> 0 : B2;
+  B01 := A0.0 -> {1'1, y[22:0]} : 0;
+  B0 := {0'1, B00} + {0'1, B01};
+  B1 := B0[24:1];
+  A0 := (S = 0) -> {1'1, x[22:0]} : A2;
+  A1 := {B0.0, A0[23:1]};
+
+  e1 := e0 - 127 + B1.23;
+  z0 := B1.23 -> B1 : {B1[22:0], A1.23};
   z := (xe = 0) | (ye = 0) -> 0 :
     ~e1.8 -> {sign, e1[7:0], z0[22:0]} :
     ~e1.7 -> {sign, 0FFH'8, z0[22:0]} : 0;  (*overflow*)
+  stall := run & (S # 23);
+
+  B2 := B1; A2 := A1;
+  S := run -> S+1 : 0;
 END FPMultiplier.

BlackBox/Po/Files/FPMultiplier.v

@@ -1,4 +1,4 @@
-`timescale 1ns / 1ps  // NW 15.9.2015
+`timescale 1ns / 1ps  // NW 15.9.2015  8.8.2016
 module FPMultiplier(
   input clk, run,
   input [31:0] x, y,
@@ -11,8 +11,8 @@ reg [47:0] P; // product
 wire sign;
 wire [7:0] xe, ye;
 wire [8:0] e0, e1;
-wire [23:0] w0, z0;
-wire [24:0] w1;
+wire [24:0] w1, z0;
+wire [23:0] w0;
 
 assign sign = x[31] ^ y[31];
 assign xe = x[30:23];
@@ -23,10 +23,10 @@ assign e1 = e0 - 127 + P[47];
 assign stall = run & ~(S == 25);
 assign w0 = P[0] ? {1'b1, y[22:0]} : 0;
 assign w1 = {1'b0, P[47:24]} + {1'b0, w0};
-assign z0 = P[47] ? P[47:24] : P[46:23];
+assign z0 = P[47] ? P[47:23]+1 : P[46:22]+1;  // round and normalize
 assign z = (xe == 0) | (ye == 0) ? 0 :
-   (~e1[8]) ? {sign, e1[7:0], z0[22:0]} :
-   (~e1[7]) ? {sign, 8'b11111111, z0[22:0]} : 0;
+   (~e1[8]) ? {sign, e1[7:0], z0[23:1]} :
+   (~e1[7]) ? {sign, 8'b11111111, z0[23:1]} : 0;
 always @ (posedge(clk)) begin
     P <= (S == 0) ? {24'b0, 1'b1, x[22:0]} : {w1, P[23:1]};
     S <= run ? S+1 : 0;

BlackBox/Po/Files/LSC.Mod.txt

@@ -1,4 +1,4 @@
-MODULE LSC;  (*Lola System Compiler, NW 8.1.95 / 26.9.2015 for RISC (LSCX)*)
+MODULE LSC;  (*Lola System Compiler, NW 8.1.95 / 18.9.2016 for RISC (LSCX)*)
   IMPORT Texts, Oberon, LSB, LSS;
   
   VAR sym: INTEGER;
@@ -187,7 +187,7 @@ MODULE LSC;  (*Lola System Compiler, NW 8.1.95 / 26.9.2015 for RISC (LSCX)*)
   BEGIN
     IF sym = LSS.minus THEN LSS.Get(sym); term(y);
       IF y.tag = LSB.lit THEN x := y; x.val := -y.val
-      ELSE x := New(LSB.sub, NIL, y); x.type := y.type; x.size := y.siz
+      ELSE x := New(LSB.sub, NIL, y); x.type := y.type; x.size := y.size
       END
     ELSIF sym = LSS.plus THEN LSS.Get(sym); term(x);
     ELSE term(x)
@@ -529,6 +529,7 @@ MODULE LSC;  (*Lola System Compiler, NW 8.1.95 / 26.9.2015 for RISC (LSCX)*)
   END Compile;
 
 BEGIN Texts.OpenWriter(W);
-  Texts.WriteString(W, "Lola compiler; NW 6.7.2015"); Texts.WriteLn(W);
+  Texts.WriteString(W, "Lola compiler; NW 18.9.2016"); Texts.WriteLn(W);
+  factor := factor0; expression := expression0; Unit := Unit0;
   NEW(top); bot := LSB.root; NEW(undef); undef.tag := 2; undef.type := LSB.bitType
 END LSC.

BlackBox/Po/Files/LSV.Mod.txt

@@ -2,7 +2,7 @@ MODULE LSV;  (*Lola System: display Verilog; generate txt-File; NW 31.8.2015*)
   IMPORT Files, Texts, Oberon, LSB;
 
   VAR W: Texts.Writer;
-    nofgen: INTEGER;;
+    nofgen: INTEGER;
     Constructor: PROCEDURE (VAR x: LSB.Item);   (*to avoid forward reference*)
     F: Files.File; R: Files.Rider;
     C: ARRAY 64, 6 OF CHAR;
@@ -75,7 +75,7 @@ MODULE LSV;  (*Lola System: display Verilog; generate txt-File; NW 31.8.2015*)
           Write("{"); WriteInt(x.b.val); Write("{"); Expression(x.a);
           Write("}"); Write("}")
         ELSE
-          IF (x.tag >= LSB.and) & (x.tag <= LSB.gtr) THEN Write("(") END ;
+          IF (x.tag >= LSB.and) & (x.tag <= LSB.then) THEN Write("(") END ;
           Expression(x.a);
           IF x.tag = LSB.sel THEN Write("["); Expression(x.b); Write("]")
           ELSIF x.tag = LSB.lit THEN
@@ -84,7 +84,7 @@ MODULE LSV;  (*Lola System: display Verilog; generate txt-File; NW 31.8.2015*)
             END
           ELSE WriteString(C[x.tag]); Expression(x.b)
           END ;
-          IF (x.tag >= LSB.and) & (x.tag <= LSB.gtr) THEN Write(")") END
+          IF (x.tag >= LSB.and) & (x.tag <= LSB.then) THEN Write(")") END
         END
       END
     END

BlackBox/Po/Files/ORB.Mod.txt

@@ -1,4 +1,4 @@
-MODULE ORB;   (*NW 25.6.2014   in Oberon-07*)
+MODULE ORB;   (*NW 25.6.2014  / 17.9.2016  in Oberon-07*)
   IMPORT Files, ORS;
   (*Definition of data types Object and Type, which together form the data structure
     called "symbol table". Contains procedures for creation of Objects, and for search:
@@ -151,8 +151,8 @@ MODULE ORB;   (*NW 25.6.2014   in Oberon-07*)
   
   PROCEDURE InType(VAR R: Files.Rider; thismod: Object; VAR T: Type);
     VAR key: LONGINT;
-      ref, class, mno, form, np, readonly: INTEGER;
-      new, fld, par, obj, mod, impmod: Object;
+      ref, class, form, np, readonly: INTEGER;
+      fld, par, obj, mod: Object;
       t: Type;
       name, modname: ORS.Ident;
   BEGIN Read(R, ref);
@@ -281,8 +281,8 @@ MODULE ORB;   (*NW 25.6.2014   in Oberon-07*)
         fld := t.dsc;
         WHILE fld # NIL DO  (*fields*)
           IF fld.expo THEN
-            Write(R, Fld); Files.WriteString(R, fld.name); OutType(R, fld.type); Files.WriteNum(R, fld.val)
-          ELSE FindHiddenPointers(R, fld.type, fld.val)  (*offset*)
+            Write(R, Fld); Files.WriteString(R, fld.name); OutType(R, fld.type); Files.WriteNum(R, fld.val)  (*offset*)
+          ELSE FindHiddenPointers(R, fld.type, fld.val)
           END ;
           fld := fld.next
         END ;
@@ -329,11 +329,7 @@ MODULE ORB;   (*NW 25.6.2014   in Oberon-07*)
           ELSIF obj.type.form = Real THEN Files.WriteInt(R, obj.val)
           ELSE Files.WriteNum(R, obj.val)
           END
-        ELSIF obj.class = Var THEN
-          Files.WriteNum(R, obj.exno);
-          IF obj.type.form = String THEN
-            Files.WriteNum(R, obj.val DIV 10000H); obj.val := obj.val MOD 10000H
-          END
+        ELSIF obj.class = Var THEN Files.WriteNum(R, obj.exno)
         END
       END ;
       obj := obj.next

BlackBox/Po/Files/ORG.Mod.txt

@@ -1,4 +1,4 @@
-MODULE ORG; (* NW  18.4.2016  code generator in Oberon-07 for RISC*)
+MODULE ORG; (* NW  18.4.2016 / 17.9.2016  code generator in Oberon-07 for RISC*)
   IMPORT SYSTEM, Files, ORS, ORB;
   (*Code generator for Oberon compiler for RISC processor.
      Procedural interface to Parser OSAP; result in array "code".
@@ -654,7 +654,7 @@ MODULE ORG; (* NW  18.4.2016  code generator in Oberon-07 for RISC*)
    BEGIN loadAdr(x); len := x.type.len;
     IF len >= 0 THEN
       IF len <  y.b THEN ORS.Mark("string too long") END
-    ELSIF check THEN Put2(Ldr, RH, SP, x.a+4);  (*open array len, frame = 0hk*)
+    ELSIF check THEN Put2(Ldr, RH, SP, x.a+4);  (*open array len, frame = 0*)
       Put1(Cmp,RH, RH, y.b); Trap(LT, 3)
     END ;
     loadStringAdr(y);
@@ -793,10 +793,12 @@ MODULE ORG; (* NW  18.4.2016  code generator in Oberon-07 for RISC*)
     VAR a, r: LONGINT;
   BEGIN invalSB; frame := 0;
     IF ~int THEN (*procedure prolog*)
+      IF locblksize >= 10000H THEN ORS.Mark("too many locals") END ;
       a := 4; r := 0;
       Put1(Sub, SP, SP, locblksize); Put2(Str, LNK, SP, 0);
       WHILE a < parblksize DO Put2(Str, r, SP, a); INC(r); INC(a, 4) END
     ELSE (*interrupt procedure*)
+      IF locblksize > 0H THEN ORS.Mark("locals not allowed") END ;
       Put1(Sub, SP, SP, 12); Put2(Str, 0, SP, 0); Put2(Str, 1, SP, 4); Put2(Str, SB, SP, 8)
       (*R0, R1, SB saved on stack*)
     END

BlackBox/Po/Files/ORP.Mod.txt

@@ -1,4 +1,4 @@
-MODULE ORP; (*N. Wirth 1.7.97 / 1.5.2016  Oberon compiler for RISC in Oberon-07*)
+MODULE ORP; (*N. Wirth 1.7.97 / 17.9.2016  Oberon compiler for RISC in Oberon-07*)
   IMPORT Texts, Oberon, ORS, ORB, ORG;
   (*Author: Niklaus Wirth, 2014.
     Parser of Oberon-RISC compiler. Uses Scanner ORS to obtain symbols (tokens),
@@ -991,7 +991,7 @@ MODULE ORP; (*N. Wirth 1.7.97 / 1.5.2016  Oberon compiler for RISC in Oberon-07*
     Oberon.Collect(0)
   END Compile;
 
-BEGIN Texts.OpenWriter(W); Texts.WriteString(W, "OR Compiler  18.4.2016");
+BEGIN Texts.OpenWriter(W); Texts.WriteString(W, "OR Compiler  17.9.2016");
   Texts.WriteLn(W); Texts.Append(Oberon.Log, W.buf);
   NEW(dummy); dummy.class := ORB.Var; dummy.type := ORB.intType;
   expression := expression0; Type := Type0; FormalType := FormalType0

BlackBox/Po/Files/RISC5.Lola.txt

@@ -1,4 +1,4 @@
-MODULE RISC5 (IN clk, rst, stallX: BIT;  (*NW 26.10.2015*)
+MODULE RISC5 (IN clk, rst, stallX: BIT;  (*NW 18.9.2016*)
   IN inbus, codebus: WORD;
   OUT adr: [24] BIT;
     rd, wr, ben: BIT;
@@ -112,7 +112,7 @@ BEGIN PM(clk, pcmux[8:0], pmout);
   C0 := R[irc];
   C1 := q -> {v!16, imm} : C0 ;
   ira0 := Br -> 15'4 : ira;
-  adr := stallL -> B[23:0] + {0'4, off} : {pcmux, 0'2};
+  adr := stallL -> B[23:0] + {off.19!4, off} : {pcmux, 0'2};
   rd := Ldr & ~stallX & ~stall1;
   wr := Str & ~stallX & ~stall1;
   ben := p & ~q & v & ~stallX & ~stall1; (*byte enable*)

BlackBox/Po/Files/RISC5.v

@@ -1,4 +1,4 @@
-`timescale 1ns / 1ps  // 25.9.2015
+`timescale 1ns / 1ps  // 13.9.2016
 
 module RISC5(
 input clk, rst, stallX,
@@ -26,7 +26,7 @@ wire [3:0] op, ira, ira0, irb, irc;
 wire [2:0] cc;
 wire [15:0] imm;
 wire [19:0] off;
-wire [23:0] offL;
+wire [21:0] disp;
 
 wire regwr;
 wire stall, stallL, stallM, stallD, stallFA, stallFM, stallFD;
@@ -42,7 +42,6 @@ wire [31:0] quotient, remainder;
 wire [63:0] product;
 wire [31:0] fsum, fprod, fquot;
 
-wire MOV, LSL, ASR, ROR, AND, ANN, IOR, XOR;  // operation signals
 wire ADD, SUB, MUL, DIV; wire FAD, FSB, FML, FDV;
 wire LDR, STR, BR;
 
@@ -76,16 +75,7 @@ assign op  = ins[19:16];
 assign irc = ins[3:0];
 assign imm = ins[15:0];   // reg instr.
 assign off = ins[19:0];   // mem instr.
-assign offL = ins[23:0];  // branch instr.
-
-assign MOV = ~p & (op == 0);
-assign LSL = ~p & (op == 1);
-assign ASR = ~p & (op == 2);
-assign ROR = ~p & (op == 3);
-assign AND = ~p & (op == 4);
-assign ANN = ~p & (op == 5);
-assign IOR = ~p & (op == 6);
-assign XOR = ~p & (op == 7);
+assign disp = ins[21:0];  // branch instr.
 
 assign ADD = ~p & (op == 8);
 assign SUB = ~p & (op == 9);
@@ -107,7 +97,8 @@ assign C0 = R[irc];
 // Arithmetic-logical unit (ALU)
 assign ira0 = BR ? 15 : ira;
 assign C1 = q ? {{16{v}}, imm} : C0;
-assign adr = stallL ? B[23:0] + {4'b0, off} : {pcmux, 2'b00};
+// assign adr = stallL ? B[23:0] + {4'b0, off} : {pcmux, 2'b00};
+assign adr = stallL ? B[23:0] + {{4{off[19]}}, off} : {pcmux, 2'b00};
 assign rd = LDR & ~stallX & ~stall1;
 assign wr = STR & ~stallX & ~stall1;
 assign ben = p & ~q & v & ~stallX & ~stall1;  // byte enable
@@ -133,25 +124,27 @@ assign t2 = (sc1 == 3) ? {t1[19:0], 12'b0} :
     (sc1 == 1) ? {t1[27:0], 4'b0} : t1;
 assign t3 = C1[4] ? {t2[15:0], 16'b0} : t2;
 
-assign aluRes =
-  MOV ? (q ?
-    (~u ? {{16{v}}, imm} : {imm, 16'b0}) :
-    (~u ? C0 : (~v ? H : {N, Z, C, OV, 20'b0, 8'h50}))) :
-  LSL ? t3 :
-  (ASR|ROR) ? s3 :
-  AND ? B & C1 :
-  ANN ? B & ~C1 :
-  IOR  ? B | C1 :
-  XOR ? B ^ C1 :
-  ADD ? B + C1 + (u & C) :
-  SUB ? B - C1 - (u & C) :
-  MUL ? product[31:0] :
-  DIV ? quotient :
- (FAD|FSB) ? fsum :
-  FML ? fprod :
-  FDV ? fquot :
-  0;
-  
+assign aluRes =  // 21.71 ns
+  ~op[3] ?
+    (~op[2] ?
+      (~op[1] ?
+        (~op[0] ? 
+          (q ?  // MOV
+            (~u ? {{16{v}}, imm} : {imm, 16'b0}) :
+            (~u ? C0 : (~v ? H : {N, Z, C, OV, 20'b0, 8'h50}))) :
+          t3) :  //  LSL
+        s3) : //  ASR, ROR
+      (~op[1] ?
+        (~op[0] ? B & C1 : B & ~C1) :  // AND, ANN
+        (~op[0] ? B | C1 : B ^ C1))) : // IOR. XOR
+    (~op[2] ?
+       (~op[1] ?
+          (~op[0] ? B + C1 + (u&C) : B - C1 - (u&C)) :   // ADD, SUB
+           (~op[0] ? product[31:0] : quotient)) :  // MUL, DIV
+         (~op[1] ?    // flt.pt.
+          fsum :
+          (~op[0] ? fprod : fquot)));
+
 assign regwr = ~p & ~stall | (LDR & ~stallX & ~stall1) | (BR & cond & v & ~stallX);
 assign a0 = ~adr[1] & ~adr[0];
 assign a1 = ~adr[1] & adr[0];
@@ -183,7 +176,7 @@ assign cond = ins[27] ^
 
 assign pcmux = ~rst ? StartAdr :
   stall ? PC :
-  (BR & cond & u) ? offL[21:0] + nxpc :
+  (BR & cond & u) ? nxpc + disp :
   (BR & cond & ~u) ? C0[23:2] : nxpc;
   
 assign sa = aluRes[31];