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@@ -1,183 +1,184 @@
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-`timescale 1ns / 1ps // 9.11.2016
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-
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-module RISC5(
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-input clk, rst, stallX,
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-input [31:0] inbus, codebus,
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-output [23:0] adr,
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-output rd, wr, ben,
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-output [31:0] outbus);
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-
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-localparam StartAdr = 22'h3FF800;
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-
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-reg [21:0] PC;
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-reg [31:0] IR; // instruction register
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-reg N, Z, C, OV; // condition flags
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-reg [31:0] R [0:15]; // array of 16 registers
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-reg [31:0] H; // aux register
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-reg stall1, PMsel;
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-
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-wire [31:0] ins, pmout;
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-wire [21:0] pcmux, nxpc;
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-wire cond, S;
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-wire sa, sb, sc;
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-
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-wire p, q, u, v; // instruction fields
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-wire [3:0] op, ira, ira0, irb, irc;
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-wire [2:0] cc;
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-wire [15:0] imm;
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-wire [19:0] off;
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-wire [21:0] disp;
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-
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-wire regwr;
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-wire stall, stallL, stallM, stallD, stallFA, stallFM, stallFD;
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-wire a0, a1, a2, a3;
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-wire [7:0] inbusL, outbusB0, outbusB1, outbusB2, outbusB3;
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-wire [23:0] inbusH;
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-
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-wire [31:0] A, B, C0, C1, aluRes, regmux;
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-wire [31:0] lshout, rshout;
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-wire [31:0] quotient, remainder;
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-wire [63:0] product;
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-wire [31:0] fsum, fprod, fquot;
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-
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-wire ADD, SUB, MUL, DIV;
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-wire FAD, FSB, FML, FDV;
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-wire LDR, STR, BR;
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-
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-PROM PM (.adr(pcmux[8:0]), .data(pmout), .clk(clk));
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-
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-Multiplier mulUnit (.clk(clk), .run(MUL), .stall(stallM),
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- .u(~u), .x(B), .y(C1), .z(product));
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-
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-Divider divUnit (.clk(clk), .run(DIV), .stall(stallD),
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- .u(~u), .x(B), .y(C1), .quot(quotient), .rem(remainder));
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-
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-LeftShifter LSUnit (.x(B), .y(lshout), .sc(C1[4:0]));
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-
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-RightShifter RSUnit(.x(B), .y(rshout), .sc(C1[4:0]), .md(ins[16]));
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-
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-FPAdder fpaddx (.clk(clk), .run(FAD|FSB), .u(u), .v(v), .stall(stallFA),
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- .x(B), .y({FSB^C0[31], C0[30:0]}), .z(fsum));
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-
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-FPMultiplier fpmulx (.clk(clk), .run(FML), .stall(stallFM),
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- .x(B), .y(C0), .z(fprod));
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-
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-FPDivider fpdivx (.clk(clk), .run(FDV), .stall(stallFD),
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- .x(B), .y(C0), .z(fquot));
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-
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-assign ins = PMsel ? pmout : IR; // decoding
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-assign p = ins[31];
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-assign q = ins[30];
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-assign u = ins[29];
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-assign v = ins[28];
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-assign cc = ins[26:24];
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-assign ira = ins[27:24];
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-assign irb = ins[23:20];
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-assign op = ins[19:16];
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-assign irc = ins[3:0];
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-assign imm = ins[15:0]; // reg instr.
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-assign off = ins[19:0]; // mem instr.
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-assign disp = ins[21:0]; // branch instr.
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-
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-assign ADD = ~p & (op == 8);
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-assign SUB = ~p & (op == 9);
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-assign MUL = ~p & (op == 10);
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-assign DIV = ~p & (op == 11);
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-assign FAD = ~p & (op == 12);
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-assign FSB = ~p & (op == 13);
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-assign FML = ~p & (op == 14);
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-assign FDV = ~p & (op == 15);
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-
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-assign LDR = p & ~q & ~u;
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-assign STR = p & ~q & u;
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-assign BR = p & q;
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-
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-assign A = R[ira0]; // register data signals
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-assign B = R[irb];
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-assign C0 = R[irc];
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-
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-// Arithmetic-logical unit (ALU)
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-assign ira0 = BR ? 15 : ira;
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-assign C1 = q ? {{16{v}}, imm} : C0;
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-assign adr = stallL ? B[23:0] + {{4{off[19]}}, off} : {pcmux, 2'b00};
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-assign rd = LDR & ~stallX & ~stall1;
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-assign wr = STR & ~stallX & ~stall1;
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-assign ben = p & ~q & v & ~stallX & ~stall1; // byte enable
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-
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-assign aluRes = // 21.71 ns
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- ~op[3] ?
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- (~op[2] ?
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- (~op[1] ?
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- (~op[0] ?
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- (q ? // MOV
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- (~u ? {{16{v}}, imm} : {imm, 16'b0}) :
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- (~u ? C0 : (~v ? H : {N, Z, C, OV, 20'b0, 8'h50}))) :
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- lshout) : // LSL
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- rshout) : // ASR, ROR
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- (~op[1] ?
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- (~op[0] ? B & C1 : B & ~C1) : // AND, ANN
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- (~op[0] ? B | C1 : B ^ C1))) : // IOR. XOR
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- (~op[2] ?
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- (~op[1] ?
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- (~op[0] ? B + C1 + (u&C) : B - C1 - (u&C)) : // ADD, SUB
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- (~op[0] ? product[31:0] : quotient)) : // MUL, DIV
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- (~op[1] ? // flt.pt.
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- fsum :
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- (~op[0] ? fprod : fquot)));
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-
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-assign regwr = ~p & ~stall | (LDR & ~stallX & ~stall1) | (BR & cond & v & ~stallX);
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-assign a0 = ~adr[1] & ~adr[0];
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-assign a1 = ~adr[1] & adr[0];
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-assign a2 = adr[1] & ~adr[0];
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-assign a3 = adr[1] & adr[0];
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-assign inbusL = (~ben | a0) ? inbus[7:0] :
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- a1 ? inbus[15:8] : a2 ? inbus[23:16] : inbus[31:24];
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-assign inbusH = ~ben ? inbus[31:8] : 24'b0;
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-assign regmux = LDR ? {inbusH, inbusL} : (BR & v) ? {8'b0, nxpc, 2'b0} : aluRes;
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-
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-assign outbusB0 = A[7:0];
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-assign outbusB1 = ben & a1 ? A[7:0] : A[15:8];
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-assign outbusB2 = ben & a2 ? A[7:0] : A[23:16];
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-assign outbusB3 = ben & a3 ? A[7:0] : A[31:24];
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-assign outbus = {outbusB3, outbusB2, outbusB1, outbusB0};
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-
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-// Control unit CU
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-assign S = N ^ OV;
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-assign nxpc = PC + 1;
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-assign cond = ins[27] ^
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- ((cc == 0) & N | // MI, PL
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- (cc == 1) & Z | // EQ, NE
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- (cc == 2) & C | // CS, CC
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- (cc == 3) & OV | // VS, VC
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- (cc == 4) & (C|Z) | // LS, HI
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- (cc == 5) & S | // LT, GE
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- (cc == 6) & (S|Z) | // LE, GT
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- (cc == 7)); // T, F
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-
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-assign pcmux = ~rst ? StartAdr :
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- stall ? PC :
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- (BR & cond & u) ? nxpc + disp :
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- (BR & cond & ~u) ? C0[23:2] : nxpc;
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-
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-assign sa = aluRes[31];
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-assign sb = B[31];
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-assign sc = C1[31];
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-
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-assign stall = stallL | stallM | stallD | stallX | stallFA | stallFM | stallFD;
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-assign stallL = (LDR|STR) & ~stall1;
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-
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-always @ (posedge clk) begin
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- PC <= pcmux;
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- PMsel <= ~rst | (pcmux[21:12] == 10'h3FF);
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- IR <= stall ? IR : codebus;
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- stall1 <= stallX ? stall1 : stallL;
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- R[ira0] <= regwr ? regmux : A;
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- N <= regwr ? regmux[31] : N;
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- Z <= regwr ? (regmux == 0) : Z;
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- C <= ADD ? (~sb&sc&~sa) | (sb&sc&sa) | (sb&~sa) :
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- SUB ? (~sb&sc&~sa) | (sb&sc&sa) | (~sb&sa) : C;
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- OV <= ADD ? (sa&~sb&~sc) | (~sa&sb&sc):
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- SUB ? (sa&~sb&sc) | (~sa&sb&~sc) : OV;
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- H <= MUL ? product[63:32] : DIV ? remainder : H;
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-end
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-endmodule
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+`timescale 1ns / 1ps // 31.8.2018
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+//with interrupt and floating-point
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+
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+module RISC5(
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+input clk, rst, irq, stallX,
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+input [31:0] inbus, codebus,
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+output [23:0] adr,
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+output rd, wr, ben,
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+output [31:0] outbus);
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+
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+localparam StartAdr = 22'h3FF800;
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+
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+reg [21:0] PC;
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+reg [31:0] IR; // instruction register
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+reg N, Z, C, OV; // condition flags
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+reg [31:0] H; // aux register
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+reg stallL1;
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+
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+wire [21:0] pcmux, pcmux0, nxpc;
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+wire cond, S;
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+wire sa, sb, sc;
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+
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+wire p, q, u, v; // instruction fields
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+wire [3:0] op, ira, ira0, irb, irc;
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+wire [2:0] cc;
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+wire [15:0] imm;
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+wire [19:0] off;
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+wire [21:0] disp;
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+
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+wire regwr;
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+wire stall, stallL0, stallM, stallD, stallFA, stallFM, stallFD;
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+wire nn, zz, cx, vv;
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+
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+reg irq1, intEnb, intPnd, intMd;
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+reg [25:0] SPC; // saved PC on interrupt
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+wire intAck;
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+
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+wire [31:0] A, B, C0, C1, aluRes, regmux, inbus1;
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+wire [31:0] lshout, rshout;
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+wire [31:0] quotient, remainder;
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+wire [63:0] product;
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+wire [31:0] fsum, fprod, fquot;
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+
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+wire ADD, SUB, MUL, DIV;
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+wire FAD, FSB, FML, FDV;
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+wire LDR, STR, BR, RTI;
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+
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+Registers regs (.clk(clk), .wr(regwr), .rno0(ira0), .rno1(irb),
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+ .rno2(irc), .din(regmux), .dout0(A), .dout1(B), .dout2(C0));
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+
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+Multiplier mulUnit (.clk(clk), .run(MUL), .stall(stallM),
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+ .u(~u), .x(B), .y(C1), .z(product));
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+
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+Divider divUnit (.clk(clk), .run(DIV), .stall(stallD),
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+ .u(~u), .x(B), .y(C1), .quot(quotient), .rem(remainder));
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+
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+LeftShifter LSUnit (.x(B), .y(lshout), .sc(C1[4:0]));
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+
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+RightShifter RSUnit(.x(B), .y(rshout), .sc(C1[4:0]), .md(IR[16]));
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+
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+FPAdder fpaddx (.clk(clk), .run(FAD|FSB), .u(u), .v(v), .stall(stallFA),
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+ .x(B), .y({FSB^C0[31], C0[30:0]}), .z(fsum));
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+
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+FPMultiplier fpmulx (.clk(clk), .run(FML), .stall(stallFM),
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+ .x(B), .y(C0), .z(fprod));
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+
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+FPDivider fpdivx (.clk(clk), .run(FDV), .stall(stallFD),
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+ .x(B), .y(C0), .z(fquot));
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+
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+assign p = IR[31];
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+assign q = IR[30];
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+assign u = IR[29];
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+assign v = IR[28];
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+assign cc = IR[26:24];
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+assign ira = IR[27:24];
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+assign irb = IR[23:20];
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+assign op = IR[19:16];
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+assign irc = IR[3:0];
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+assign imm = IR[15:0]; // reg instr.
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+assign off = IR[19:0]; // mem instr.
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+assign disp = IR[21:0]; // branch instr.
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+
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+assign ADD = ~p & (op == 8);
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+assign SUB = ~p & (op == 9);
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+assign MUL = ~p & (op == 10);
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+assign DIV = ~p & (op == 11);
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+
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+assign FAD = ~p & (op == 12);
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+assign FSB = ~p & (op == 13);
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+assign FML = ~p & (op == 14);
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+assign FDV = ~p & (op == 15);
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+
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+assign LDR = p & ~q & ~u;
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+assign STR = p & ~q & u;
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+assign BR = p & q;
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+assign RTI = BR & ~u & ~v & IR[4];
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+
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+// Arithmetic-logical unit (ALU)
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+assign ira0 = BR ? 15 : ira;
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+assign C1 = q ? {{16{v}}, imm} : C0;
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+assign adr = stallL0 ? B[23:0] + {{4{off[19]}}, off} : {pcmux, 2'b00};
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+assign rd = LDR & ~stallX & ~stallL1;
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+assign wr = STR & ~stallX & ~stallL1;
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+assign ben = p & ~q & v & ~stallX & ~stallL1; // byte enable
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+
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+assign aluRes =
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+ ~op[3] ?
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+ (~op[2] ?
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+ (~op[1] ?
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+ (~op[0] ?
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+ (q ? // MOV
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+ (~u ? {{16{v}}, imm} : {imm, 16'b0}) :
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+ (~u ? C0 : (~v ? H : {N, Z, C, OV, 20'b0, 8'h53}))) :
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+ lshout) : // LSL
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+ rshout) : // ASR, ROR
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+ (~op[1] ?
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+ (~op[0] ? B & C1 : B & ~C1) : // AND, ANN
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+ (~op[0] ? B | C1 : B ^ C1))) : // IOR. XOR
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+ (~op[2] ?
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+ (~op[1] ?
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+ (~op[0] ? B + C1 + (u&C) : B - C1 - (u&C)) : // ADD, SUB
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+ (~op[0] ? product[31:0] : quotient)) : // MUL, DIV
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+ (~op[1] ? // flt.pt.
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+ fsum :
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+ (~op[0] ? fprod : fquot)));
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+
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+assign regwr = ~p & ~stall | (LDR & ~stallX & ~stallL1) | (BR & cond & v & ~stallX);
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+assign inbus1 = ~ben ? inbus :
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+ {24'b0, (adr[1] ? (adr[0] ? inbus[31:24] : inbus[23:16]) :
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+ (adr[0] ? inbus[15:8] : inbus[7:0]))};
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+assign regmux = LDR ? inbus1 : (BR & v) ? {8'b0, nxpc, 2'b0} : aluRes;
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+assign outbus = ~ben ? A :
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+ adr[1] ? (adr[0] ? {A[7:0], 24'b0} : {8'b0, A[7:0], 16'b0}) :
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+ (adr[0] ? {16'b0, A[7:0], 8'b0} : {24'b0, A[7:0]});
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+
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+// Control unit CU
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+assign S = N ^ OV;
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+assign nxpc = PC + 1;
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+assign cond = IR[27] ^
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+ ((cc == 0) & N | // MI, PL
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+ (cc == 1) & Z | // EQ, NE
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+ (cc == 2) & C | // CS, CC
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+ (cc == 3) & OV | // VS, VC
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+ (cc == 4) & (C|Z) | // LS, HI
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+ (cc == 5) & S | // LT, GE
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+ (cc == 6) & (S|Z) | // LE, GT
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+ (cc == 7)); // T, F
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+
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+assign intAck = intPnd & intEnb & ~intMd & ~stall;
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+assign pcmux = ~rst | stall | intAck | RTI ?
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+ (~rst | stall ? (~rst ? StartAdr : PC) :
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+ (intAck ? 1 : SPC)) : pcmux0;
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+assign pcmux0 = (BR & cond) ? (u? nxpc + disp : C0[23:2]) : nxpc;
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+
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+assign sa = aluRes[31];
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+assign sb = B[31];
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+assign sc = C1[31];
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+
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+assign nn = RTI ? SPC[25] : regwr ? regmux[31] : N;
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+assign zz = RTI ? SPC[24] : regwr ? (regmux == 0) : Z;
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+assign cx = RTI ? SPC[23] :
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+ ADD ? (~sb&sc&~sa) | (sb&sc&sa) | (sb&~sa) :
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+ SUB ? (~sb&sc&~sa) | (sb&sc&sa) | (~sb&sa) : C;
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+assign vv = RTI ? SPC[22] :
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+ ADD ? (sa&~sb&~sc) | (~sa&sb&sc):
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+ SUB ? (sa&~sb&sc) | (~sa&sb&~sc) : OV;
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+
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+assign stallL0 = (LDR|STR) & ~stallL1;
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+assign stall = stallL0 | stallM | stallD | stallX | stallFA | stallFM | stallFD;
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+
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+always @ (posedge clk) begin
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+ PC <= pcmux;
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+ IR <= stall ? IR : codebus;
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+ stallL1 <= stallX ? stallL1 : stallL0;
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+ N <= nn; Z <= zz; C <= cx; OV <= vv;
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+ H <= MUL ? product[63:32] : DIV ? remainder : H;
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+
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+ irq1 <= irq; // edge detector
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+ intPnd <= rst & ~intAck & ((~irq1 & irq) | intPnd);
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+ intMd <= rst & ~RTI & (intAck | intMd);
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+ intEnb <= ~rst ? 0 : (BR & ~u & ~v & IR[5]) ? IR[0] : intEnb;
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+ SPC <= (intAck) ? {nn, zz, cx, vv, pcmux0} : SPC;
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+ end
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+endmodule
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Alexander Shiryaev