synchronized with original

BlackBox/Po/Files/Divider.Lola.txt

@@ -1,24 +1,20 @@
-MODULE Divider(
-  IN clk, run: BIT;
+MODULE Divider(   (*NW 14.9.2015*)
+  IN clk, run, u: BIT;
   OUT stall: BIT;
-  IN x, y: WORD;  (*32 bit, y > 0*)
+  IN x, y: WORD;  (*y > 0*)
   OUT quot, rem: WORD);
-  REG (clk) S: [5] BIT;
-    R, Q: WORD;
-  VAR neg: BIT;
-    x0, r0, r1, r2, q0, q1, d: WORD;
-BEGIN stall := run & ~(S = 31);
-  neg := x.31;
-  x0 := neg -> ~x + y : x;    (* -x + (y-1) *)
-  r0 := (S = 0) -> 0'32 : R;
-  d := r1 - y;
-  r1 := {r0[30:0], q0.31};
-  r2 := d.31 -> r1 : d;
-  q0 := (S = 0) -> x0 : Q;
-  q1 := {q0[30:0], ~d.31};
-  quot := neg -> ~q1 : q1;
-  rem := neg -> ~r2 + y : r2;   (*(y-1) - r2*)
-  R := r2;
-  Q := q1;
-  S := run -> S+1 : 0
+  
+  REG (clk) S: [6] BIT;
+    RQ: [64] BIT;
+  VAR sign: BIT;
+    x0, w0, w1: WORD;
+BEGIN stall := run & (S # 33);
+  sign := x.31 & u;
+  x0 := sign -> -x : x;
+  w0 := RQ[62:31];
+  w1 := w0 - y;
+  S := run -> S+1 : 0;
+  quot  := ~sign -> RQ[31:0] : (RQ[63:32] = 0) -> -RQ[31:0] : -RQ[31:0] - 1;
+  rem := ~sign -> RQ[63:32] : (RQ[63:32] = 0) -> 0 :  y - RQ[63:32];
+  RQ := (S = 0) -> {0'32, x0} : {w1.31 -> w0 : w1,  RQ[30:0], ~w1[31]}
 END Divider.

BlackBox/Po/Files/Divider.v

@@ -0,0 +1,28 @@
+`timescale 1ns / 1ps  // NW 20.9.2015
+
+module Divider(
+  input clk, run, u,
+  output stall,
+  input [31:0] x, y,  // y > 0
+  output [31:0] quot, rem);
+
+reg [5:0] S;  // state
+reg [63:0] RQ;
+wire sign;
+wire [31:0] x0, w0, w1;
+
+assign stall = run & ~(S == 33);
+assign sign = x[31] & u;
+assign x0 = sign ? -x : x;
+assign w0 = RQ[62: 31];
+assign w1 = w0 - y;
+assign quot = ~sign ? RQ[31:0] :
+  (RQ[63:32] == 0) ? -RQ[31:0] : -RQ[31:0] - 1;
+assign rem = ~sign ? RQ[63:32] :
+  (RQ[63:32] == 0) ? 0 : y - RQ[63:32];
+
+always @ (posedge(clk)) begin
+  RQ <= (S == 0) ? {32'b0, x0} : {(w1[31] ? w0 : w1), RQ[30:0], ~w1[31]};
+  S <= run ? S+1 : 0;
+end
+endmodule

BlackBox/Po/Files/Divider0.v

@@ -0,0 +1,28 @@
+`timescale 1ns / 1ps  // NW 31.10.10
+
+module Divider(
+  input clk, run,
+  output stall,
+  input [31:0] x, y,  // x >= 0, y > 0
+  output [31:0] quot, rem);
+
+reg [4:0] S;  // state
+reg [31:0] R, Q;
+wire [31:0] r0, r1, r2, q0, q1, d;
+
+assign stall = run & ~(S == 31);
+assign r0 = (S == 0) ? 0 : R;
+assign d = r1 - y;
+assign r1 = {r0[30:0], q0[31]};
+assign r2 = d[31] ? r1 : d;
+assign q0 = (S == 0) ? x : Q;
+assign q1 = {q0[30:0], ~d[31]};
+assign rem = r2;
+assign quot = q1;
+
+always @ (posedge(clk)) begin
+  R <= r2; Q <= q1;
+  S <= run ? S+1 : 0;
+end
+
+endmodule

BlackBox/Po/Files/Draw.Tool.txt

@@ -1,8 +1,11 @@
 Draw.Open XX.Graph  Draw.Store 
 Rectangles.Make  Curves.MakeCircle
 
-System.SetFont Syntax10.Scn.Fnt
+System.SetFont Oberon10.Scn.Fnt
 Draw.SetWidth 2
-Draw.ChangeFont Syntax8.Scn.Fnt
+Draw.ChangeFont Oberon8.Scn.Fnt
+Draw.ChangeFont Oberon10b.Scn.Fnt
 Draw.ChangeWidth 2
 Draw.Macro TTL0 N02
+
+Blinkers.Make  Blinkers.Blink  Blinkers.Run  Blinkers.Stop

BlackBox/Po/Files/FPAdder.Lola.txt

@@ -1,9 +1,10 @@
-MODULE FPAdder(   (*NW 2.11.2014*)
+MODULE FPAdder(   (*NW  28.9.2015*)
   IN clk, run, u, v: BIT; x, y: WORD;
   OUT stall: BIT; z: WORD);
 
-  REG (clk) Sum: [27] BIT;  (*pipe reg*)
-    stallR: BIT;
+  REG (clk) State: [2] BIT;
+    x3, y3, t3: [25] BIT;
+    Sum: [27] BIT;
 
   VAR xs, ys: BIT;  (*signs*)
     xe, ye: [9] BIT;  (*exponents*)
@@ -13,13 +14,13 @@ MODULE FPAdder(   (*NW 2.11.2014*)
     sx, sy: [9] BIT;  (*shift counts*)
     sx0, sx1, sy0, sy1: [2] BIT;
     sxh, syh: BIT;
-    x0, x1,x2, x3, y0, y1, y2, y3: [25] BIT;
+    x0, x1,x2,  y0, y1, y2: [25] BIT;
     s: [27] BIT;
 
     z24, z22, z20, z18, z16, z14, z12, z10, z8, z6, z4, z2: BIT;
     sc: [5] BIT;  (*shift count*)
     sc0, sc1: [2] BIT;
-    t1, t2, t3: [25] BIT;
+    t1, t2: [25] BIT;
 
 BEGIN  (*unpack*)
   xs := x.31;
@@ -88,8 +89,8 @@ BEGIN  (*unpack*)
     (sc1 = 1) -> {t1[20:0], 0'4} : t1;
   t3 := sc.4 -> {t2[8:0], 0'16} : t2;
 
-  stall := run & ~stallR;
-  stallR := stall;
+  stall := run & (State # 3);
+  State := run -> State+1 : 0;
 
   z := v -> {Sum.26 ! 7, Sum[25:1]} :   (*FLOOR*)
     x[30:0] = 0 -> (~u -> y : 0) :

BlackBox/Po/Files/FPAdder.v

@@ -0,0 +1,130 @@
+`timescale 1ns / 1ps  // NW 20.9.2015  pipelined
+// u = 1: FLT; v = 1: FLOOR
+
+module FPAdder(
+  input clk, run, u, v,
+  input [31:0] x, y,
+  output stall,
+  output [31:0] z);
+
+reg [1:0] State;
+
+wire xs, ys;  // signs
+wire [7:0] xe, ye;
+wire [24:0] xm, ym;
+
+wire [8:0] dx, dy, e0, e1;
+wire [7:0] sx, sy;  // shift counts
+wire [1:0] sx0, sx1, sy0, sy1;
+wire sxh, syh;
+wire [24:0] x0, x1, x2, y0, y1, y2;
+reg [24:0] x3, y3;
+
+reg [26:0] Sum;
+wire [26:0] s;
+
+wire z24, z22, z20, z18, z16, z14, z12, z10, z8, z6, z4, z2;
+wire [4:0] sc;  // shift count
+wire [1:0] sc0, sc1;
+wire [24:0] t1, t2;
+reg [24:0] t3;
+
+assign xs = x[31];  // sign x
+assign xe = u ? 8'h96 : x[30:23];  // expo x
+assign xm = {~u|x[23], x[22:0], 1'b0};  //mant x
+assign ys = y[31];  // sign y
+assign ye = y[30:23];  // expo y
+assign ym = {~u&~v, y[22:0], 1'b0};  //mant y
+
+assign dx = xe - ye;
+assign dy = ye - xe;
+assign e0 = (dx[8]) ? ye : xe;
+assign sx = dy[8] ? 0 : dy;
+assign sy = dx[8] ? 0 : dx;
+assign sx0 = sx[1:0];
+assign sx1 = sx[3:2];
+assign sy0 = sy[1:0];
+assign sy1 = sy[3:2];
+assign sxh = sx[7] | sx[6] | sx[5];
+assign syh = sy[7] | sy[6] | sy[5];
+
+// denormalize, shift right
+assign x0 = xs&~u ? -xm : xm;
+assign x1 = (sx0 == 3) ? {{3{xs}}, x0[24:3]} :
+  (sx0 == 2) ? {{2{xs}}, x0[24:2]} : (sx0 == 1) ? {xs, x0[24:1]} : x0;
+assign x2 = (sx1 == 3) ? {{12{xs}}, x1[24:12]} :
+  (sx1 == 2) ? {{8{xs}}, x1[24:8]} : (sx1 == 1) ? {{4{xs}}, x1[24:4]} : x1;
+always @ (posedge(clk))
+  x3 <= sxh ? {25{xs}} : (sx[4] ? {{16{xs}}, x2[24:16]} : x2);
+
+assign y0 = ys&~u ? -ym : ym;
+assign y1 = (sy0 == 3) ? {{3{ys}}, y0[24:3]} :
+  (sy0 == 2) ? {{2{ys}}, y0[24:2]} : (sy0 == 1) ? {ys, y0[24:1]} : y0;
+assign y2 = (sy1 == 3) ? {{12{ys}}, y1[24:12]} :
+  (sy1 == 2) ? {{8{ys}}, y1[24:8]} : (sy1 == 1) ? {{4{ys}}, y1[24:4]} : y1;
+always @ (posedge(clk))
+	y3 <= syh ? {25{ys}} : (sy[4] ? {{16{ys}}, y2[24:16]} : y2);
+	
+// add
+always @ (posedge(clk)) Sum <= {xs, xs, x3} + {ys, ys, y3};
+assign s = (Sum[26] ? -Sum : Sum) + 1;
+
+// post-normalize
+assign z24 = ~s[25] & ~ s[24];
+assign z22 = z24 & ~s[23] & ~s[22];
+assign z20 = z22 & ~s[21] & ~s[20];
+assign z18 = z20 & ~s[19] & ~s[18];
+assign z16 = z18 & ~s[17] & ~s[16];
+assign z14 = z16 & ~s[15] & ~s[14];
+assign z12 = z14 & ~s[13] & ~s[12];
+assign z10 = z12 & ~s[11] & ~s[10];
+assign z8 = z10 & ~s[9] & ~s[8];
+assign z6 = z8 & ~s[7] & ~s[6];
+assign z4 = z6 & ~s[5] & ~s[4];
+assign z2 = z4 & ~s[3] & ~s[2];
+
+assign sc[4] = z10;  // sc = shift count of post normalization
+assign sc[3] = z18 & (s[17] | s[16] | s[15] | s[14] | s[13] | s[12] | s[11] | s[10])
+      | z2;
+assign sc[2] = z22 & (s[21] | s[20] | s[19] | s[18])
+      | z14 & (s[13] | s[12] | s[11] | s[10])
+      | z6 & (s[5] | s[4] | s[3] | s[2]);
+assign sc[1] = z24 & (s[23] | s[22])
+      | z20 & (s[19] | s[18])
+      | z16 & (s[15] | s[14])
+      | z12 & (s[11] | s[10])
+      | z8 & (s[7] | s[6])
+      | z4 & (s[3] | s[2]);
+assign sc[0] = ~s[25] & s[24]
+      | z24 & ~s[23] & s[22]
+      | z22 & ~s[21] & s[20]
+      | z20 & ~s[19] & s[18]
+      | z18 & ~s[17] & s[16]
+      | z16 & ~s[15] & s[14]
+      | z14 & ~s[13] & s[12]
+      | z12 & ~s[11] & s[10]
+      | z10 & ~s[9] & s[8]
+      | z8 & ~s[7] & s[6]
+      | z6 & ~s[5] & s[4]
+      | z4 & ~s[3] & s[2];
+
+assign e1 = e0 - sc + 1;
+assign sc0 = sc[1:0];
+assign sc1 = sc[3:2];
+
+assign t1 = (sc0 == 3) ? {s[22:1], 3'b0} :
+  (sc0 == 2) ? {s[23:1], 2'b0} : (sc0 == 1) ? {s[24:1], 1'b0} : s[25:1];
+assign t2 = (sc1 == 3) ? {t1[12:0], 12'b0} :
+  (sc1 == 2) ? {t1[16:0], 8'b0} : (sc1 == 1) ? {t1[20:0], 4'b0} : t1;
+always @ (posedge(clk)) t3 <= sc[4] ? {t2[8:0], 16'b0} : t2;
+
+assign stall = run & ~(State == 3);
+always @ (posedge(clk)) State <= run ? State + 1 : 0;
+
+assign z = v ? {{7{Sum[26]}}, Sum[25:1]} :  // FLOOR
+    (x[30:0] == 0) ? (~u ? y : 0) :
+    (y[30:0] == 0) ? x :
+    ((t3 == 0) | e1[8]) ? 0 : 
+	 {Sum[26], e1[7:0], t3[23:1]};
+endmodule
+

BlackBox/Po/Files/FPDivider.Lola.txt

@@ -1,35 +1,36 @@
-MODULE FPDivider(
+MODULE FPDivider(   (*NW 19.9.2015*)
   IN clk, run: BIT; x, y: WORD;
   OUT stall: BIT; z: WORD);
 
   REG (clk) S: [5] BIT;   (*state*)
-    R, Q: [24] BIT;   (*remainder, quotient*)
+    R: [24] BIT;   (*remainder*)
+    Q: [25] BIT;   (*quotient*)
 
   VAR sign: BIT;
     xe, ye: [8] BIT;
     e0, e1: [9] BIT;
-    q0, q1, q2: [24] BIT;
-    r0, r1, r2, d: [25] BIT;
+    z0: [24] BIT;
+    r0, r1, d, q0: [25] BIT;
 
-BEGIN sign := x.31 ^ y.31;   (*xor*)
+BEGIN
+  sign := x.31 ^ y.31;   (*xor*)
   xe := x[30:23]; ye := y[30:23];
   e0 := {0'1, xe} - {0'1, ye};
-  e1 := e0 + 126 + q1.23;
+  e1 := e0 + 126 + Q.24;
+  stall := run & (S # 25);
 
-  r0 := (S = 0) -> {1'2, x[22:0]} : r2;
+  r0 := (S = 0) -> {1'2, x[22:0]} : {R, 0'1};
   d := r0 - {1'2, y[22:0]};
   r1 := d.24 -> r0 : d;
-  r2 := {R, 0'1};
   q0 := (S = 0) -> 0 : Q;
-  q1 := {q0[22:0], ~d.24};
-  q2 := q1.23 -> q1[23:0] : {q1[22:0], 0'1};
 
+  z0 := Q.24 -> Q[24:1] : Q[23:0];  (*post norm*)
   z := (xe = 0) -> 0 :
-    (ye = 0) -> {sign, $FF'8, 0'23} :  (*divide by 0*)
-    ~e1.8 -> {sign, e1[7:0], q2[22:0]} :
-    ~e1.7 -> {sign, $FF'8, q2[22:0]} : 0;   (*overflow*)
-  stall := run & (S # 23);
+    (ye = 0) -> {sign, 0FFH'8, 0'23} :  (*divide by 0*)
+    ~e1.8 -> {sign, e1[7:0], z0[22:0]} :
+    ~e1.7 -> {sign, 0FFH'8, z0[22:0]} : 0;   (*overflow*)
 
-  R := r1[23:0]; Q := q1;
+  R := r1[23:0];
+  Q := {q0[23:0], ~d.24};
   S := run -> S+1 : 0
 END FPDivider.

BlackBox/Po/Files/FPDivider.v

@@ -0,0 +1,43 @@
+`timescale 1ns / 1ps   // NW 18.9.2015
+
+module FPDivider(
+    input clk, run,
+    input [31:0] x,
+    input [31:0] y,
+    output stall,
+    output [31:0] z);
+
+reg [4:0] S;  // state
+reg [23:0] R;
+reg [24:0] Q;
+
+wire sign;
+wire [7:0] xe, ye;
+wire [8:0] e0, e1;
+wire [24:0] r0, r1, d, q0;
+wire [23:0] z0;
+
+assign sign = x[31]^y[31];
+assign xe = x[30:23];
+assign ye = y[30:23];
+assign e0 = {1'b0, xe} - {1'b0, ye};
+assign e1 = e0 + 126 + Q[24];
+assign stall = run & ~(S == 25);
+
+assign r0 = (S == 0) ? {2'b1, x[22:0]} : {R, 1'b0};
+assign d = r0 - {2'b1, y[22:0]};
+assign r1 = d[24] ? r0 : d;
+assign q0 = (S == 0) ? 0 : Q;
+
+assign z0 = Q[24] ? Q[24:1] : Q[23:0];
+assign z = (xe == 0) ? 0 :
+  (ye == 0) ? {sign, 8'b11111111, 23'b0} :
+  (~e1[8]) ? {sign, e1[7:0], z0[22:0]} :
+  (~e1[7]) ? {sign, 8'b11111111, z0[22:0]} : 0;
+
+always @ (posedge(clk)) begin
+  R <= r1[23:0];
+  Q <= {q0[23:0], ~d[24]};
+  S <= run ? S+1 : 0;
+end
+endmodule

BlackBox/Po/Files/FPMultiplier.Lola.txt

@@ -1,34 +1,29 @@
-MODULE FPMultiplier(
+MODULE FPMultiplier(   (*NW 15.9.2015*)
   IN clk, run: BIT; x, y: WORD;
   OUT stall: BIT; z: WORD);
 
   REG (clk) S: [5] BIT;   (*state*)
-    B2, A2: [24] BIT;
+    P: [48] BIT;   (*product*)
 
   VAR sign: BIT;
     xe, ye: [8] BIT;
     e0, e1: [9] BIT;
-    B0: [25] BIT;
-    B00, B01, B1, A1, A0, z0: [24] BIT;
+    w0, z0: [24] BIT;
+    w1: [25] BIT;
 
 BEGIN sign := x.31 ^ y.31;   (*xor*)
-  xe := x[30:23]; ye := y[30:23]; e0 := {0'1, xe} + {0'1, ye};
-  B00 := (S = 0) -> 0 : B2;
-  B01 := A0.0 -> {1'1, y[22:0]} : 0;
-  B0 := {0'1, B00} + {0'1, B01};
-  B1 := B0[24:1];
-  A0 := (S = 0) -> {1'1, x[22:0]} : A2;
-  A1 := {B0.0, A0[23:1]};
+  xe := x[30:23]; ye := y[30:23];
+  e0 := {0'1, xe} + {0'1, ye};
+  e1 := e0 - 127 + P.47;
+  stall := run & (S # 25);
+  w0 := P.0 -> {1'1, y[22:0]} : 0;
+  w1 := {0'1, P[47:24]} + {0'1, w0};
 
-  e1 := e0 - 127 + B1.23;
-  z0 := B1.23 -> B1 : {B1[22:0], A1.23};
+  P := (S = 0) -> {0'24, 1'1, x[22:0]} : {w1, P[23:1]};
+  S := run -> S+1 : 0;
+
+  z0 := P.47 -> P[47:24] : P[46:23];  (*post norm*)
   z := (xe = 0) | (ye = 0) -> 0 :
     ~e1.8 -> {sign, e1[7:0], z0[22:0]} :
     ~e1.7 -> {sign, 0FFH'8, z0[22:0]} : 0;  (*overflow*)
-  stall := run & (S # 23);
-
-  B2 := B1; A2 := A1;
-  S := run -> S+1 : 0;
 END FPMultiplier.
-
-  

BlackBox/Po/Files/FPMultiplier.v

@@ -0,0 +1,34 @@
+`timescale 1ns / 1ps  // NW 15.9.2015
+module FPMultiplier(
+  input clk, run,
+  input [31:0] x, y,
+  output stall,
+  output [31:0] z);
+
+reg [4:0] S;  // state
+reg [47:0] P; // product
+
+wire sign;
+wire [7:0] xe, ye;
+wire [8:0] e0, e1;
+wire [23:0] w0, z0;
+wire [24:0] w1;
+
+assign sign = x[31] ^ y[31];
+assign xe = x[30:23];
+assign ye = y[30:23];
+assign e0 = xe + ye;
+assign e1 = e0 - 127 + P[47];
+
+assign stall = run & ~(S == 25);
+assign w0 = P[0] ? {1'b1, y[22:0]} : 0;
+assign w1 = {1'b0, P[47:24]} + {1'b0, w0};
+assign z0 = P[47] ? P[47:24] : P[46:23];
+assign z = (xe == 0) | (ye == 0) ? 0 :
+   (~e1[8]) ? {sign, e1[7:0], z0[22:0]} :
+   (~e1[7]) ? {sign, 8'b11111111, z0[22:0]} : 0;
+always @ (posedge(clk)) begin
+    P <= (S == 0) ? {24'b0, 1'b1, x[22:0]} : {w1, P[23:1]};
+    S <= run ? S+1 : 0;
+end
+endmodule

BlackBox/Po/Files/IOBUF32.v

@@ -1,9 +0,0 @@
-module IOBUF32 (input [31:0] I, output [31:0] O, inout [31:0] IO, input T);
-genvar k;
-generate // tri-state buffer for SRAM
-  for (k = 0; k < 32; k = k+1)
-  begin: bufblock
-    IOBUF SRbuf (.I(I[k]), .O(O[k]), .IO(IO[k]), .T(T));
-  end
-endgenerate
-endmodule

BlackBox/Po/Files/IOBUF8.v

@@ -1,10 +0,0 @@
-module IOBUF8 (input [7:0] I, output [7:0] O, inout [7:0] IO, input [7:0] T);
-genvar k;
-generate // tri-state buffer for parallel port
-  for (k = 0; k < 8; k = k+1)
-  begin: gpioblock
-    IOBUF gpiobuf (.I(I[k]), .O(O[k]), .IO(IO[k]), .T(T[k]));
-  end
-endgenerate
-endmodule
-

BlackBox/Po/Files/LSB.Mod.txt

@@ -1,4 +1,4 @@
-MODULE LSB;  (*Lola System Compiler Base LSBX, 5.2.2015*)
+MODULE LSB;  (*Lola System Compiler Base LSBX, 26.9.2015*)
   IMPORT Texts, Oberon;
   
   CONST
@@ -7,7 +7,7 @@ MODULE LSB;  (*Lola System Compiler Base LSBX, 5.2.2015*)
     (*tags in output*) const* = 1; typ* = 2; var* = 3; lit* = 4; sel* = 7; range* = 8; cons* = 9;
     repl* = 10; not* = 11; and* = 12; mul* = 13; div* = 14; or* = 15; xor* = 16; add* = 17; sub* = 18;
     eql* = 20; neq* = 21; lss* = 22; geq* = 23; leq* = 24; gtr* = 25;
-    then* = 30; else* = 31; next* = 32;
+    then* = 30; else* = 31; ts* = 32; next* = 33;
 
   TYPE
     Item* = POINTER TO ItemDesc;

BlackBox/Po/Files/LSC.Mod.txt

@@ -1,4 +1,4 @@
-MODULE LSC;  (*Lola System Compiler, NW 8.1.95 / 25.2.2015 for RISC (LSCX)*)
+MODULE LSC;  (*Lola System Compiler, NW 8.1.95 / 26.9.2015 for RISC (LSCX)*)
   IMPORT Texts, Oberon, LSB, LSS;
   
   VAR sym: INTEGER;
@@ -186,7 +186,9 @@ MODULE LSC;  (*Lola System Compiler, NW 8.1.95 / 25.2.2015 for RISC (LSCX)*)
     VAR y, z: LSB.Item; op: INTEGER;
   BEGIN
     IF sym = LSS.minus THEN LSS.Get(sym); term(y);
-      IF y.tag = LSB.lit THEN x := y; x.val := -y.val ELSE x := New(LSB.sub, NIL, y); x.type := y.type END
+      IF y.tag = LSB.lit THEN x := y; x.val := -y.val
+      ELSE x := New(LSB.sub, NIL, y); x.type := y.type; x.size := y.siz
+      END
     ELSIF sym = LSS.plus THEN LSS.Get(sym); term(x);
     ELSE term(x)
     END ;
@@ -294,15 +296,33 @@ MODULE LSC;  (*Lola System Compiler, NW 8.1.95 / 25.2.2015 for RISC (LSCX)*)
         END
       ELSE LSS.Mark("bad statement")
       END
+    ELSIF sym = LSS.ts THEN  (*tri-state*) LSS.Get(sym);
+      IF sym = LSS.lparen THEN LSS.Get(sym) ELSE LSS.Mark("( missing") END ;
+      IF sym = LSS.ident THEN
+        x := ThisObj(LSS.id); x.b := undef;  (*INOUT parameter*)
+        IF x.val # 5 THEN LSS.Mark("not INOUT") END ;
+        LSS.Get(sym);
+        IF sym = LSS.comma THEN LSS.Get(sym) END ;
+        IF sym = LSS.ident THEN y := ThisObj(LSS.id); CheckAssign(x, y); y.b := undef END ;  (*output from gate*)
+        LSS.Get(sym);
+        IF sym = LSS.comma THEN LSS.Get(sym) END ;
+        expression(z);
+        IF (z.tag = LSB.lit) & (z.val <= 1) THEN z.type := LSB.bitType END ;
+        CheckAssign(x, z); LSS.Get(sym);
+        IF sym = LSS.comma THEN LSS.Get(sym) END ;
+        expression(w);  (*control*)
+        IF w.type # LSB.bitType THEN CheckAssign(x, w) END ;
+        w := New(LSB.next, z, w); x.b := New(LSB.ts, y, w);
+        IF sym = LSS.rparen THEN LSS.Get(sym) ELSE LSS.Mark(") missing") END
+      END
     END
   END Statement;
 
   PROCEDURE StatSequence;
   BEGIN Statement;
     WHILE sym <= LSS.semicolon DO
-      IF sym = LSS.semicolon THEN LSS.Get(sym)
-      ELSIF sym < LSS.semicolon THEN LSS.Mark("semicolon missing?");
-      END ; 
+      IF sym < LSS.semicolon THEN LSS.Mark("semicolon missing?") END ;
+      WHILE sym = LSS.semicolon DO LSS.Get(sym) END ;
       Statement
     END ;
     IF sym = LSS.end THEN LSS.Get(sym) ELSE LSS.Mark("END ?") END
@@ -310,6 +330,15 @@ MODULE LSC;  (*Lola System Compiler, NW 8.1.95 / 25.2.2015 for RISC (LSCX)*)
 
   (*---------------------------------------------------*)
   
+  (* for variables and registers,, obj.val has the meaning
+    0  register
+    1  register with imlicit clock "clk"
+    2  variable
+    3  output parameter
+    4  output parameter with register
+    5  inout parameter
+    6  input parameter  *)
+  
   PROCEDURE ConstDeclaration;
     VAR obj: LSB.Object;
   BEGIN
@@ -382,8 +411,12 @@ MODULE LSC;  (*Lola System Compiler, NW 8.1.95 / 25.2.2015 for RISC (LSCX)*)
   PROCEDURE ParamList;
     VAR kind: INTEGER;
   BEGIN
-    IF sym = LSS.in THEN kind := 6 ELSIF sym = LSS.out THEN kind := 3 ELSIF sym = LSS.inout THEN kind := 4 END ;
-    LSS.Get(sym); VarList(kind, NIL)
+    IF sym = LSS.in THEN LSS.Get(sym); kind := 6
+    ELSIF sym = LSS.out THEN LSS.Get(sym);
+      IF sym = LSS.reg THEN LSS.Get(sym); kind := 4 ELSE kind := 3 END
+    ELSIF sym = LSS.inout THEN LSS.Get(sym); kind := 5
+    END ;
+    VarList(kind, NIL)
   END ParamList;
 
   PROCEDURE Traverse(x: LSB.Item);
@@ -496,7 +529,6 @@ MODULE LSC;  (*Lola System Compiler, NW 8.1.95 / 25.2.2015 for RISC (LSCX)*)
   END Compile;
 
 BEGIN Texts.OpenWriter(W);
-  Texts.WriteString(W, "Lola compiler; NW 20.2.2015"); Texts.WriteLn(W);
-  NEW(top); bot := LSB.root; NEW(undef); undef.tag := 2; undef.type := LSB.bitType;
-  factor := factor0; expression := expression0; Unit := Unit0
+  Texts.WriteString(W, "Lola compiler; NW 6.7.2015"); Texts.WriteLn(W);
+  NEW(top); bot := LSB.root; NEW(undef); undef.tag := 2; undef.type := LSB.bitType
 END LSC.

BlackBox/Po/Files/LSP.Mod.txt

@@ -1,4 +1,4 @@
-MODULE LSP;  (*display data structure;  NW 5.2.2014*)
+MODULE LSP;  (*display data structure;  NW 28.8.2015*)
   IMPORT Texts, Oberon, LSB;
 
   VAR W: Texts.Writer;
@@ -81,5 +81,5 @@ BEGIN Texts.OpenWriter(W);
   C[LSB.or] := "| "; C[LSB.xor] := "^ "; C[LSB.and] := "& ";  C[LSB.not] := "~ ";
   C[LSB.add] := "+ "; C[LSB.sub] := "- "; C[LSB.mul] := "* "; C[LSB.div] := "/ ";
   C[LSB.eql] := "= "; C[LSB.neq] := "# "; C[LSB.lss] := "< "; C[LSB.geq] := ">="; C[LSB.leq] := "<="; C[LSB.gtr] := "> ";
-  C[LSB.then] := " -> "; C[LSB.else] := " :: "; C[LSB.next] := "--"
+  C[LSB.then] := " -> "; C[LSB.else] := " :: "; C[LSB.ts] := "TS "; C[LSB.next] := "--"
 END LSP.

BlackBox/Po/Files/LSS.Mod.txt

@@ -1,15 +1,15 @@
-MODULE LSS; (* NW 16.10.93 / 12.4.2015*)
+MODULE LSS; (* NW 16.10.93 / 1.9.2015*)
   IMPORT Texts, Oberon;
   
-  CONST IdLen* = 32; NofKeys = 10;
+  CONST IdLen* = 32; NofKeys = 11;
     (*symbols*) null = 0;
     arrow* = 1; times* = 2; div* = 3; and* = 4; plus* = 5; minus* = 6; or* = 7; xor* = 8;  not* = 9;
     eql* = 10; neq* = 11; lss* = 12; leq* = 13; gtr* = 14; geq* = 15;
     at* = 16; apo* = 17; period* = 18; comma* = 19; colon* = 20; rparen* = 21; rbrak* = 22; rbrace* = 23; 
     then* = 24; lparen* = 26; lbrak* = 27; lbrace* = 28; repl* = 29; becomes* = 30;
-    ident* = 31; integer* = 32; reg* = 35; semicolon* = 40; end* = 41;
-    const* = 51; type* = 52; var* = 53; out* = 54; inout* = 55; in* = 56;
-    begin* = 57; module* = 58; eof = 59;
+    ident* = 31; integer* = 32; ts* = 33; semicolon* = 40; end* = 41;
+    const* = 51; type* = 52; reg* = 53; var* = 54; out* = 55; inout* = 56; in* = 57;
+    begin* = 58; module* = 59; eof = 60;
 
   TYPE Ident* = ARRAY IdLen OF CHAR;
 
@@ -55,21 +55,25 @@ MODULE LSS; (* NW 16.10.93 / 12.4.2015*)
   END identifier;
 
   PROCEDURE Number(VAR sym: INTEGER);
-    VAR i, k, h, n: INTEGER;
-      d: ARRAY 16 OF INTEGER;
-  BEGIN sym := integer; i := 0; k := 0; n := 0;
+    VAR i, k, h, n, d: LONGINT;
+      hex: BOOLEAN;
+      dig: ARRAY 16 OF LONGINT;
+  BEGIN sym := integer; i := 0; k := 0; n := 0; hex := FALSE;
     REPEAT
-      IF n < 16 THEN d[n] := ORD(ch)-30H; INC(n) ELSE Mark("too many digits"); n := 0 END ;
+      IF n < 16 THEN d := ORD(ch)-30H;
+        IF d >= 10 THEN hex := TRUE ; d := d - 7 END ;
+        dig[n] := d; INC(n)
+      ELSE Mark("too many digits"); n := 0
+      END ;
       Texts.Read(R, ch)
     UNTIL (ch < "0") OR (ch > "9") & (ch < "A") OR (ch > "F");
     IF ch = "H" THEN (*hex*)
-      REPEAT h := d[i];
-        IF h >= 10 THEN h := h-7 END ;
-        k := k*10H + h; INC(i) (*no overflow check*)
+      REPEAT h := dig[i]; k := k*10H + h; INC(i) (*no overflow check*)
       UNTIL i = n;
       Texts.Read(R, ch)
     ELSE
-      REPEAT k := k*10 + d[i]; INC(i) UNTIL i = n
+      IF hex THEN Mark("illegal hex digit") END ;
+      REPEAT k := k*10 + dig[i]; INC(i) UNTIL i = n
     END ;
     val := k
   END Number;
@@ -157,4 +161,5 @@ BEGIN Texts.OpenWriter(W);
   key[7] := "REG"; symno[7] := reg;
   key[8] := "TYPE"; symno[8] := type;
   key[9] := "VAR"; symno[9] := var;
+  key[10] := "TS"; symno[10] := ts
 END LSS.

BlackBox/Po/Files/LSV.Mod.txt

@@ -1,7 +1,8 @@
-MODULE LSV;  (*Lola System: display Verilog; generate txt-File; NW 20.2.2015*)
+MODULE LSV;  (*Lola System: display Verilog; generate txt-File; NW 31.8.2015*)
   IMPORT Files, Texts, Oberon, LSB;
 
   VAR W: Texts.Writer;
+    nofgen: INTEGER;;
     Constructor: PROCEDURE (VAR x: LSB.Item);   (*to avoid forward reference*)
     F: Files.File; R: Files.Rider;
     C: ARRAY 64, 6 OF CHAR;
@@ -78,8 +79,7 @@ MODULE LSV;  (*Lola System: display Verilog; generate txt-File; NW 20.2.2015*)
           Expression(x.a);
           IF x.tag = LSB.sel THEN Write("["); Expression(x.b); Write("]")
           ELSIF x.tag = LSB.lit THEN
-            IF x.size # 0 THEN
-              WriteInt(x.size); Write("'"); Write("h"); WriteHex(x.val)
+            IF x.size # 0 THEN WriteInt(x.size); Write("'"); Write("h"); WriteHex(x.val)
             ELSE WriteInt(x.val)
             END
           ELSE WriteString(C[x.tag]); Expression(x.b)
@@ -125,7 +125,8 @@ MODULE LSV;  (*Lola System: display Verilog; generate txt-File; NW 20.2.2015*)
         IF obj.val <= 1 THEN WriteString("reg ")
         ELSIF obj.val = 2 THEN WriteString("wire ")
         ELSIF obj.val = 3 THEN WriteString("output ")
-        ELSIF obj.val = 4 THEN WriteString("inout ")
+        ELSIF obj.val = 4 THEN WriteString("output reg ")
+        ELSIF obj.val = 5 THEN WriteString("inout ")
         ELSIF obj.val = 6 THEN WriteString("input ")
         ELSE WriteString("??? ")
         END ;
@@ -150,7 +151,7 @@ MODULE LSV;  (*Lola System: display Verilog; generate txt-File; NW 20.2.2015*)
   END ActParam;
 
   PROCEDURE ObjList1(obj: LSB.Object);  (*assignments to variables*)
-    VAR apar: LSB.Item; fpar: LSB.Object;
+    VAR apar, x: LSB.Item; fpar: LSB.Object; size: LONGINT;
   BEGIN
     WHILE obj # LSB.root DO
       IF (obj.tag = LSB.var) OR (obj.tag = LSB.const) THEN
@@ -160,6 +161,28 @@ MODULE LSV;  (*Lola System: display Verilog; generate txt-File; NW 20.2.2015*)
           Write("("); ActParam(apar.b, fpar); apar := apar.a; fpar := fpar.next;  (*actual param list*)
           WHILE apar # NIL DO WriteString(", "); ActParam(apar.b, fpar); apar := apar.a; fpar := fpar.next END ;
           Write(")"); Write(";"); WriteLn
+        ELSIF (obj.b # NIL) & (obj.val = 5) THEN  (*tri-state*)
+          size := obj.type.size; x := obj.b;
+        IF x.tag = LSB.ts THEN
+            IF obj.type = LSB.bitType THEN
+              WriteString("IOBUF block"); INC(nofgen); WriteInt(nofgen); WriteString(" (.IO("); WriteString(obj.name);
+              WriteString("), .O("); WriteString(x.a(LSB.Object).name); WriteString("), .I("); x := x.b; 
+              IF x.a.type = LSB.bitType THEN Expression(x.a) ELSE WriteString(x.a(LSB.Object).name) END ;
+              WriteString("), .T(");
+              IF x.b.type = LSB.bitType THEN Expression(x.b) ELSE  WriteString(x.b(LSB.Object).name) END ;
+              WriteString("));")
+            ELSE  (*array type*)
+              IF nofgen = 0 THEN WriteString("genvar i;"); WriteLn END ;
+              INC(nofgen); WriteString("generate"); WriteLn;
+              WriteString("for (i = 0; i < "); WriteInt(size); WriteString("; i = i+1) begin : bufblock"); WriteInt(nofgen); WriteLn;
+              WriteString("IOBUF block (.IO("); WriteString(obj.name);
+              WriteString("[i]), .O("); WriteString(x.a(LSB.Object).name); WriteString("[i]), .I("); x := x.b;
+              WriteString(x.a(LSB.Object).name); WriteString("[i]), .T(");
+              IF x.b.type = LSB.bitType THEN Expression(x.b) ELSE WriteString(x.b(LSB.Object).name); WriteString("[i]") END ;
+              WriteString("));"); WriteLn; WriteString("end"); WriteLn; WriteString("endgenerate")
+            END ;
+            WriteLn
+          END
         ELSIF (obj.b # NIL) & (obj.val >= 2) THEN
           WriteString("assign "); WriteString(obj.name);
           IF (obj.a # NIL) THEN Write("["); Expression(obj.a); Write("]") END ;
@@ -197,7 +220,7 @@ MODULE LSV;  (*Lola System: display Verilog; generate txt-File; NW 20.2.2015*)
     IF (S.class = Texts.Name) OR (S.class = Texts.String) THEN
       Texts.WriteString(W, LSB.modname); Texts.WriteString(W, " translating to  "); Texts.WriteString(W, S.s);
       F := Files.New(S.s); Files.Set(R, F, 0);
-      WriteString("`timescale 1ns / 1 ps"); WriteLn;
+      WriteString("`timescale 1ns / 1 ps"); WriteLn; nofgen := 0;
       WriteString("module "); WriteString(LSB.modname); WriteString("(   // translated from Lola"); WriteLn;
       ObjList0(LSB.top); ObjList1(LSB.top); ObjList2(LSB.top);
       WriteString("endmodule"); WriteLn;
@@ -211,5 +234,5 @@ BEGIN Texts.OpenWriter(W); Constructor := Constructor0;
   C[LSB.or] := " | "; C[LSB.xor] := " ^ "; C[LSB.and] := " & ";  C[LSB.not] := "~";
   C[LSB.add] := " + "; C[LSB.sub] := " - "; C[LSB.mul] := " * "; C[LSB.div] := " / ";
   C[LSB.eql] := " == "; C[LSB.neq] := " != "; C[LSB.lss] := " <  "; C[LSB.geq] := " >= "; C[LSB.leq] := " <= "; C[LSB.gtr] := " >  ";
-  C[LSB.then] := " ? "; C[LSB.else] := " : "; C[LSB.next] := "--"
+  C[LSB.then] := " ? "; C[LSB.else] := " : "; C[LSB.ts] := "TS"; C[LSB.next] := "--"
 END LSV.

BlackBox/Po/Files/MouseP.Lola.txt

@@ -1,31 +1,30 @@
-MODULE MouseP (   (*version on Web without PS2Buf*)
+MODULE MouseP (   (*NW 7.9.2015*)
   IN clk, rst: BIT;
-  INOUT io: [2] BIT;
+  INOUT msclk, msdat: BIT;
   OUT out: [28] BIT);
   (* init mouse cmd F4 (start reporting) with start, parity and stop bits added *)
   CONST InitBuf := 0FFFFFDE8H;  (* 1...1 1 0 1111 0100 0 *)
-  TYPE IOBUF = MODULE (IN I: BIT; OUT O: BIT; INOUT IO: BIT; IN T: BIT) ^;
   REG (clk) x, y: [10] BIT;   (*counters*)
     btns: [3] BIT;
     Q0, Q1, run: BIT;
     shreg: [32] BIT;
-  VAR buf0, buf1: IOBUF;
-    msclk, msdat: BIT;
-    shift, endbit, reply: BIT;
+  VAR shift, endbit, reply: BIT;
     dx, dy: [10] BIT;
-BEGIN
-  buf0 (0, msclk, io.0, rst);
-  buf1 (0, msdat, io.1, run | shreg.0);
+    msclk0, msdat0: BIT;
+BEGIN TS(msclk, msclk0, 0'1, rst);
+  TS(msdat, msdat0, 0'1, run | shreg.0);
   shift := Q1 & ~Q0;   (*falling edge detector*)
-  reply := ~run & ~shreg.11;   (*start bit of echoed initBuf, if response*)
+  reply := ~run & ~shreg.1;   (*start bit of echoed initBuf, if response*)
   endbit := run & ~shreg.0;   (*normal packet received*)
   dx := {shreg.5 !2, shreg.7 -> 0'8 : shreg[19:12]};   (*sign + ovfl*)
   dy := {shreg.6 !2, shreg.8 -> 0'8 : shreg[30:23]};   (*sign + ovfl*)
   out := {run, btns, 0'2, y, 0'2, x};
-
+  
   run := rst & (reply | run);
-  Q0 := msclk; Q1 := Q0;
-  shreg := ~rst -> InitBuf : (endbit | reply) -> 0FFFFFFFFH'32: shift -> {msdat, shreg[31:1]} : shreg;
+  Q0 := msclk0; Q1 := Q0;  (*edhe detector*)
+  shreg := ~rst -> 0FFFFFDE8H:
+    (endbit | reply) -> 0FFFFFFFFH'32:
+    shift -> {msdat0, shreg[31:1]} : shreg;
   x := ~rst -> 0'10 : endbit -> x + dx : x;
   y := ~rst -> 0'10 : endbit -> y + dy : y;
   btns := ~rst -> 0'3 : endbit -> {shreg.1, shreg.3, shreg.2} : btns

BlackBox/Po/Files/MouseP.v

@@ -0,0 +1,44 @@
+`timescale 1ns / 1ps  // PS/2 Logitech mouse PDR 14.10.2013 / 8.9.2015
+module MouseP(
+  input clk, rst,
+  inout msclk, msdat,
+  output [27:0] out);
+
+  reg [9:0] x, y;
+  reg [2:0] btns;
+  reg Q0, Q1, run;
+  reg [31:0] shreg;
+  wire shift, endbit, reply;
+  wire [9:0] dx, dy;
+
+// 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1                 bit
+// 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+// ===============================================================
+// p y y y y y y y y 0 1 p x x x x x x x x 0 1 p Y X t s 1 M R L 0 normal
+// ---------------------------------------------------------------
+// p ----response--- 0 1 --InitBuf echoed--- 1 1 1 1 1 1 1 1 1 1 1 init
+// ---------------------------------------------------------------
+// p = parity (ignored); X, Y = overflow; s, t = x, y sign bits
+
+  // initially need to send F4 cmd (start reporting); add start and parity bits
+  localparam InitBuf = 32'b11111111111111111111110_11110100_0;
+  assign msclk = ~rst ? 0 : 1'bz;  // initial drive clock low
+  assign msdat = ~run & ~shreg[0] ? 0 : 1'bz;
+  assign shift = Q1 & ~Q0;  // falling edge detector
+  assign reply = ~run & ~shreg[11];  // start bit of echoed InitBuf, if response
+  assign endbit = run & ~shreg[0];  // normal packet received
+  assign dx = {{2{shreg[5]}}, shreg[7] ? 8'b0 : shreg[19:12]};  //sign+overfl
+  assign dy = {{2{shreg[6]}}, shreg[8] ? 8'b0 : shreg[30:23]};  //sign+overfl
+  assign out = {run, btns, 2'b0, y, 2'b0, x};
+
+  always @ (posedge clk) begin
+    run <= rst & (reply | run); Q0 <= msclk; Q1 <= Q0;
+    shreg <= ~rst ? InitBuf : (endbit | reply) ? -1 : shift ? {msdat,
+shreg[31:1]} : shreg;
+    x <= ~rst ? 0 : endbit ? x + dx : x;  y <= ~rst ? 0 : endbit ? y + dy
+: y;
+    btns <= ~rst ? 0 : endbit ? {shreg[1], shreg[3], shreg[2]} : btns;
+  end
+
+endmodule
+

BlackBox/Po/Files/MouseX.v

@@ -0,0 +1,28 @@
+`timescale 1ns / 1ps
+// N.Wirth  10.10.2012
+module MouseX(
+  input clk,
+  input [6:0] in,
+  output [27:0] out);
+
+  reg x00, x01, x10, x11, y00, y01, y10, y11;
+  reg ML, MM, MR;  // keys
+  reg [9:0] x, y;  // counters
+
+  wire xup, xdn, yup, ydn;
+
+  assign xup = ~x00&~x01&~x10&x11 | ~x00&x01&x10&x11 | x00&~x01&~x10&~x11 | x00&x01&x10&~x11;
+  assign yup = ~y00&~y01&~y10&y11 | ~y00&y01&y10&y11 | y00&~y01&~y10&~y11 | y00&y01&y10&~y11;
+  assign xdn = ~x00&~x01&x10&~x11 | ~x00&x01&~x10&~x11 | x00&~x01&x10&x11 | x00&x01&~x10&x11;
+  assign ydn = ~y00&~y01&y10&~y11 | ~y00&y01&~y10&~y11 | y00&~y01&y10&y11 | y00&y01&~y10&y11;
+  assign out = {1'b0, ML, MM, MR, 2'b0, y, 2'b0, x};
+  
+  always @ (posedge clk) begin
+    x00 <= in[3]; x01 <= x00; x10 <= in[2]; x11 <= x10;
+    y00 <= in[1]; y01 <= y00; y10 <= in[0]; y11 <= y10;
+    MR <= ~in[4]; MM <= ~in[5]; ML <= ~in[6];
+    x <= xup ? x+1 : xdn ? x-1 : x; 
+    y <= yup ? y+1 : ydn ? y-1 : y;
+  end
+endmodule
+

BlackBox/Po/Files/Multiplier.Lola.txt

@@ -1,47 +1,18 @@
-MODULE Multiplier (     (*NW 7.9.2014*)
+MODULE Multiplier (     (*NW 13.9.2014*)
   IN clk, run, u: BIT;
   OUT stall: BIT;
   IN x, y: WORD;   (*32 bit*)
   OUT z: [64] BIT);
 
-  VAR b0, b00, b01: [33] BIT;
-    b1, a0, a1: WORD;
-  REG (clk) S: [5] BIT;   (*state*)
-    B, A: WORD;   (*high and low parts of partial product*)
+  REG (clk) S: [6] BIT;   (*state*)
+    P: [64] BIT;   (*product*)
+  VAR w0: WORD;
+    w1: [33] BIT;
 
-BEGIN stall := run & ~(S = 31);
-  b00 := (S = 0) -> 0'33 : {B.31, B};
-  b01 := a0.0 -> {y.31 & u, y} : 0'33;
-  b0 := ((S = 31) & u) -> b00 - b01: b00 + b01;
-  b1 := b0[32:1];
-  a0 := (S = 0) -> x : A;
-  a1 := {b0.0, a0[31:1]};
-  z := {b1, a1};
-  B := b1; A := a1;
-  S := run -> S+1 : 0
+BEGIN stall := run & (S # 33);
+  w0 := P.0 -> y : 0;
+  w1 := (S =32) & u -> {P.63, P[63:32]} - {w0.31, w0} : {P.63, P[63:32]} + {w0.31, w0};
+  S := run -> S+1 : 0;
+  P := (S = 0) -> {0'32, x} : {w1[32:0], P[31:1]};
+  z := P
 END Multiplier.
-
-MODULE Multiplier1 (     (*NW 5.10.2014*)
-  IN clk, run, u: BIT;
-  OUT stall: BIT;
-  IN x, y: WORD;   (*32 bit*)
-  OUT z: [64] BIT);
-
-  TYPE MULT18X18 := MODULE (OUT P: [36] BIT; IN A, B: [18] BIT) ^;
-
-  VAR M0, M1, M2, M3: MULT18X18;
-    p0, p1, p2, p3: [36] BIT;
-  REG (clk) S: BIT;   (*state*)
-    z0: [16] BIT; z1, z2: [48] BIT;
-BEGIN 
-  M0(p0, {0'2, x[15:0]}, {0'2, y[15:0]});
-  M1(p1, {u&x.31, u&x.31, x[31:16]}, {0'2, y[15:0]});
-  M2(p2, {0'2, x[15:0]}, {u&y.31, u&y.31, y[31:16]});
-  M3(p3, {u&x.31, u&x.1, x[31:16]}, {u&y.31, u&y.31, y[31:16]});
-  stall := run & ~S;
-  z := {z1 + z2, z0};
-  S := stall;
-  z0 := p0[15:0];
-  z1 := {0'32, p0[31:16]} + {(u&p1.31)!16, p1[31:0]};
-  z2 := {u&p2.31!16, p2[31:0]} + {p3[31:0], 0'16}
-END Multiplier1.

BlackBox/Po/Files/Multiplier.v

@@ -0,0 +1,25 @@
+`timescale 1ns / 1ps   // NW 14.9.2015
+
+module Multiplier(
+  input clk, run, u,
+  output stall,
+  input [31:0] x, y,
+  output [63:0] z);
+
+reg [5:0] S;    // state
+reg [63:0] P;   // product
+wire [31:0] w0;
+wire [32:0] w1;
+
+assign stall = run & ~(S == 33);
+assign w0 = P[0] ? y : 0;
+assign w1 = (S == 32) & u ? {P[63], P[63:32]} - {w0[31], w0} :
+       {P[63], P[63:32]} + {w0[31], w0};
+assign z = P;
+
+always @ (posedge(clk)) begin
+  P <= (S == 0) ? {32'b0, x} : {w1[32:0], P[31:1]};
+  S <= run ? S+1 : 0;
+end
+
+endmodule

BlackBox/Po/Files/Multiplier1.v

@@ -0,0 +1,28 @@
+`timescale 1ns / 1ps  // NW 29.4.2011
+module Multiplier1(
+  input clk, run, u,
+  output stall,
+  input [31:0] x, y,
+  output [63:0] z);
+	 
+reg S;  // state
+reg [15:0] z0;
+reg [47:0] z1, z2;
+wire [35:0] p0, p1, p2, p3;
+
+assign stall = run & ~S;
+assign z[15:0] = z0;
+assign z[63:16] = z1 + z2;
+
+MULT18X18 mult0(.P(p0), .A({2'b0, x[15:0]}), .B({2'b0, y[15:0]}));
+MULT18X18 mult1(.P(p1), .A({{2{u&x[31]}}, x[31:16]}), .B({2'b0, y[15:0]}));
+MULT18X18 mult2(.P(p2), .A({2'b0, x[15:0]}), .B({{2{u&y[31]}}, y[31:16]}));
+MULT18X18 mult3(.P(p3), .A({{2{u&x[31]}}, x[31:16]}), .B({{2{u&y[31]}}, y[31:16]}));
+
+always @(posedge clk) begin
+  S <= stall;
+  z0 <= p0[15:0];
+  z1 <= {{32'b0}, p0[31:16]} + {{16{u&p1[31]}}, p1[31:0]};
+  z2 <= {{16{u&p2[31]}}, p2[31:0]} + {p3[31:0], 16'b0};
+end
+endmodule

BlackBox/Po/Files/PIO.Mod.txt

@@ -0,0 +1,42 @@
+MODULE PIO;   (*NW 16.10.2014  PIC Input/Output for RISC*)
+  IMPORT SYSTEM;
+  
+(* PIC interface, output:
+  D0  =  PIC B7  data out
+  D1  =  PIC B6  clk  out
+  D2  =  PIC A4  data in *)
+
+  CONST gpio = -32; gpoc = -28;  (*I/O addresses*)
+
+  PROCEDURE del(i: INTEGER);
+  BEGIN
+    REPEAT DEC(i) UNTIL i = 0
+  END del;
+
+  PROCEDURE Send*(x: LONGINT);
+    VAR i: INTEGER;
+  BEGIN (*send byte*)
+    FOR i := 0 TO 7 DO
+      SYSTEM.PUT(gpio, x MOD 2 + 2); del(60); SYSTEM.PUT(gpio, x MOD 2); del(25); x := x DIV 2
+    END ;
+    SYSTEM.PUT(gpio, 0); del(100)
+  END Send;
+
+  PROCEDURE Receive*(VAR x: LONGINT);
+    VAR i, x0: INTEGER;
+  BEGIN (*receive byte*) x0 := 0;
+    REPEAT UNTIL ~SYSTEM.BIT(gpio, 2);
+    FOR i := 0 TO 7 DO
+      SYSTEM.PUT(gpio, 2); del(60);
+      IF SYSTEM.BIT(gpio, 2) THEN x0 := x0 + 100H END ;
+      SYSTEM.PUT(gpio, 0); del(25); x0 := ROR(x0, 1)
+    END ;
+    x := x0
+  END Receive;
+
+  PROCEDURE Reset*;
+  BEGIN SYSTEM.PUT(gpio, 0); SYSTEM.PUT(gpoc, 3)  (*set bit 0, 1 to output*)
+  END Reset;
+
+BEGIN Reset
+END PIO.

BlackBox/Po/Files/PROM.v

@@ -0,0 +1,12 @@
+`timescale 1ns / 1ps // 32-bit PROM initialised from hex file  PDR 23.12.13
+
+module PROM (input clk,
+  input [8:0] adr,
+  output reg [31:0] data);
+  
+reg [31:0] mem [511: 0];
+initial $readmemh("../prom.mem", mem);
+always @(posedge clk) data <= mem[adr];
+
+endmodule
+

BlackBox/Po/Files/PS2.v

@@ -0,0 +1,33 @@
+`timescale 1ns / 1ps  // NW 20.10.2012
+// PS2 receiver for keyboard, 8 bit data
+// clock is 25 MHz; 25000 / 1302 = 19.2 KHz
+
+module PS2(
+    input clk, rst,
+    input done,   // "byte has been read"
+    output rdy,   // "byte is available"
+    output shift, // shift in, tramsmitter
+    output [7:0] data,
+    input PS2C,   // serial input
+    input PS2D);
+	 
+reg Q0, Q1;  // synchronizer and falling edge detector
+reg [10:0] shreg;
+reg [3:0] inptr, outptr;
+reg [7:0] fifo [15:0];  // 16 byte buffer
+wire endbit;
+
+assign endbit = ~shreg[0];  //start bit reached correct pos
+assign shift = Q1 & ~Q0;
+assign data = fifo[outptr];
+assign rdy = ~(inptr == outptr);
+
+always @ (posedge clk) begin
+  Q0 <= PS2C; Q1 <= Q0;
+  shreg <= (~rst | endbit) ? 11'h7FF :
+    shift ? {PS2D, shreg[10:1]} : shreg;
+  outptr <= ~rst ? 0 : rdy & done ? outptr+1 : outptr;
+  inptr <= ~rst ? 0 : endbit ? inptr+1 : inptr;
+  if (endbit) fifo[inptr] <= shreg[8:1];
+end	 
+endmodule

BlackBox/Po/Files/PS2BUF.v

@@ -1,6 +0,0 @@
-//PS/2 2-wire open-collector interface from tri-state buffers PDR 26.11.14
-//if T[x]=0, drive the IO[x] line with a 0; if I[x]=1, be tri-state (PULLUP in ucf)
-module PS2BUF (output [1:0] O, inout [1:0] IO, input [1:0] T);
-  IOBUF buf0 (.I(0), .O(O[0]), .IO(IO[0]), .T(T[0]));
-  IOBUF buf1 (.I(0), .O(O[1]), .IO(IO[1]), .T(T[1]));    
-endmodule

BlackBox/Po/Files/RISC5.Lola.txt

@@ -1,19 +1,21 @@
-MODULE RISC5 (IN clk, rst, stallX: BIT;  (*NW 31.10.2014*)
+MODULE RISC5 (IN clk, rst, stallX: BIT;  (*NW 25.9.2015*)
   IN inbus, codebus: WORD;
-  OUT adr: [20] BIT;
+  OUT adr: [24] BIT;
     rd, wr, ben: BIT;
     outbus: WORD);
   
-  CONST StartAdr = 3F800H'18;
+  CONST StartAdr = 3FF800H'22;
 
-  TYPE PROM := MODULE (IN adr: [11] BIT; OUT data: WORD; IN clk: BIT) ^;
-
-    Multiplier1 := MODULE (IN clk, run, u: BIT;
+  TYPE PROM := MODULE (IN clk: BIT;
+      IN adr: [9] BIT;
+      OUT data: WORD) ^;
+  
+    Multiplier := MODULE (IN clk, run, u: BIT;
       OUT stall: BIT;
       IN x, y: WORD;
       OUT z: [64] BIT) ^;
 
-    Divider := MODULE (IN clk, run: BIT;
+    Divider := MODULE (IN clk, run, u: BIT;
       OUT stall: BIT;
       IN x, y: WORD;
       OUT quot, rem: WORD) ^;
@@ -27,65 +29,70 @@ MODULE RISC5 (IN clk, rst, stallX: BIT;  (*NW 31.10.2014*)
     FPDivider := MODULE (IN clk, run: BIT; OUT stall: BIT;
       IN x, y: WORD; OUT z: WORD) ^;
 
-
-  REG (clk) PC: [18] BIT;
-    IRBuf: WORD;
-    N, Z, C, OV: BIT;
+  REG (clk) PC: [22] BIT;  (*program counter*)
+    IR: WORD;   (*instruction register*)
+    N, Z, C, OV: BIT;   (*condition flags*)
     stall1, PMsel: BIT;
-    R: [16] WORD;
-    H: WORD;
+    R: [16] WORD;   (*data registers*)
+    H: WORD;  (*auxiliary register*)
 
-  VAR IR, pmout: WORD;
-    pcmux, nxpc: [18] BIT;
+  VAR PM: PROM;  (*mem for boot loader*)
+    mulUnit: Multiplier;
+    divUnit: Divider;
+    faddUnit: FPAdder;
+    fmulUnit: FPMultiplier;
+    fdivUnit: FPDivider;
+
+    pcmux, nxpc: [22] BIT;
     cond, S: BIT;
     sa, sb, sc: BIT;
 
-    p, q, u, v, w: BIT;
+    ins, pmout: WORD;
+    p, q, u, v, w: BIT;   (*instruction fields*)
     op, ira, ira0, irb, irc: [4] BIT;
     cc: [3] BIT;
     imm: [16] BIT;
     off: [20] BIT;
-    
+    offL: [24] BIT;
+
     regwr, stall, stallL, stallM, stallD, stallFA, stallFM, stallFD: BIT;
     sc1, sc0: [2] BIT;  (*shift counts*)
-    
+
+    a0, a1, a2, a3: BIT;
+    inbusL, outbusB0, outbusB1, outbusB2, outbusB3: BYTE;
+    inbusH: [24] BIT;
+
     A, B, C0, C1, aluRes, regmux: WORD;
-    s1, s2, s3, t1, t2, t3: WORD;
+    s1, s2, s3, t1, t2, t3: WORD;  (*shifting*)
     quotient, remainder: WORD;
     product: [64] BIT;
     fsum, fprod, fquot: WORD;
-    
-    Mov, Lsl, Asr, Ror, And, Ann, Ior, Xor, Add, Sub, Mul, Div: BIT;
-    Fadd, Fsub, Fmul, Fdiv, Ldr, Str, Br: BIT;
 
-    PM: PROM;
-    mulUnit: Multiplier1;
-    divUnit: Divider;
-    faddUnit: FPAdder;
-    fmulUnit: FPMultiplier;
-    fdivUnit: FPDivider;
+    Mov, Lsl, Asr, Ror, And, Ann, Ior, Xor, Add, Sub, Mul, Div: BIT;
+    Fadd, Fsub, Fmul, Fdiv: BIT; 
+    Ldr, Str, Br: BIT;
 
-BEGIN
-  PM (pcmux[10:0], pmout, clk);
+BEGIN PM(clk, pcmux[8:0], pmout);
   mulUnit (clk, Mul, ~u, stallM, B, C1, product);
-  divUnit (clk, Div, stallD, B, C1, quotient, remainder);
+  divUnit (clk, Div, ~u, stallD, B, C1, quotient, remainder);
   faddUnit (clk, Fadd|Fsub, u, v, stallFA, B, {Fsub^C0.31, C0[30:0]}, fsum);
   fmulUnit (clk, Fmul, stallFM, B, C0, fprod);
   fdivUnit (clk, Fdiv, stallFD, B, C0, fquot);
 
-  IR := PMsel -> pmout : IRBuf;
-  p := IR.31;  (*instruction fields*)
-  q := IR.30;
-  u := IR.29;
-  v := IR.28;
-  w := IR.16;
-  cc:= IR[26:24];
-  ira := IR[27:24];
-  irb := IR[23:20];
-  op := IR[19:16];
-  irc := IR[3:0];
-  imm := IR[15:0];
-  off := IR[19:0];
+  ins := PMsel -> pmout : IR;  (*current instruction*)
+  p := ins.31;  (*instruction fields*)
+  q := ins.30;
+  u := ins.29;
+  v := ins.28;
+  w := ins.16;
+  cc:= ins[26:24];
+  ira := ins[27:24];
+  irb := ins[23:20];
+  op := ins[19:16];
+  irc := ins[3:0];
+  imm := ins[15:0];  (*reg instr*)
+  off := ins[19:0];    (*mem instr*)
+  offL := ins[23:0];  (*branch instr*)
 
   Mov := ~p & (op = 0);  (*instruction signals*)
   Lsl := ~p & (op = 1);
@@ -103,23 +110,20 @@ BEGIN
   Fsub := ~p & (op = 13);
   Fmul := ~p & (op = 14);
   Fdiv := ~p & (op = 15);
-
   Ldr := p & ~q & ~u;
   Str := p & ~q & u;
   Br := p & q;
 
+  (*ALU*)
   A := R[ira0];  (*main data path*)
   B := R[irb];
   C0 := R[irc];
-
-  (*ALU*)
-  ira0 := Br -> 15'4 : ira;
   C1 := q -> {v!16, imm} : C0 ;
-  adr := stallL -> B[19:0] + off : {pcmux, 0'2};
+  ira0 := Br -> 15'4 : ira;
+  adr := stallL -> B[23:0] + {0'4, off} : {pcmux, 0'2};
   rd := Ldr & ~stallX & ~stall1;
   wr := Str & ~stallX & ~stall1;
   ben := p & ~q & v & ~stallX & ~stall1; (*byte enable*)
-  outbus := A;
 
   sc0 := C1[1:0];
   sc1 := C1[3:2];
@@ -145,7 +149,7 @@ BEGIN
   aluRes :=
     Mov -> (q ->
       (~u -> {v!16, imm} : {imm, 0'16}) :
-      (~u -> C0 : (~v -> H : {N, Z, C, OV, 0'20, 54H'8}))):
+      (~u -> C0 : (~v -> H : {N, Z, C, OV, 0'20, 58H'8}))):
     Lsl -> t3 :
     (Asr | Ror) -> s3 :
     And -> B & C1 :
@@ -158,15 +162,27 @@ BEGIN
     Div -> quotient :
     (Fadd|Fsub) -> fsum :
     Fmul -> fprod :
-    Fdiv -> fquot : 0;
-
-  regwr := ~p & ~stall | (Ldr & ~stallX & ~stall1) | (Br & cond & v);
-  regmux := Ldr -> inbus : (Br & v) -> {0'12, nxpc, 0'2} : aluRes;
+    Fdiv -> fquot :  0;
+
+  regwr := ~p & ~stall | (Ldr & ~stallX & ~stall1) | (Br & cond & v & ~stallX);
+  a0 := ~adr.1 & ~adr.0;
+  a1 := ~adr.1 & adr.0;
+  a2 := adr.1 & ~adr.0;
+  a3 := adr.1 & adr.0;
+  inbusL := (~ben | a0) -> inbus[7:0] : a1 -> inbus[15:8] : a2 -> inbus[23:16] : inbus[31:24];
+  inbusH := ~ben -> inbus[31:8] : 0'24;
+  regmux := Ldr -> {inbusH, inbusL} : (Br & v) -> {0'8, nxpc, 0'2} : aluRes;
+
+  outbusB0 := A[7:0];
+  outbusB1 := ben & a1 -> A[7:0] : A[15:8];
+  outbusB2 := ben & a2 -> A[7:0] : A[23:16];
+  outbusB3 := ben & a3 -> A[7:0] : A[31:24];
+  outbus := {outbusB3, outbusB2, outbusB1, outbusB0};
 
   (*control unit*)
   S := N ^ OV;
   nxpc := PC + 1;
-  cond := IR.27 ^ (
+  cond := ins.27 ^ (
       (cc = 0) & N  |  (*MI, PL*)
       (cc = 1) & Z  |  (*EQ, NE*)
       (cc = 2) & C  |  (*CS, CC*)
@@ -175,20 +191,22 @@ BEGIN
       (cc = 5) & S  |  (*LT, GE*)
       (cc = 6) & (S|Z) | (*LE, GT*)
       (cc = 7));
-  pcmux := ~rst -> StartAdr :
+  pcmux := ~rst -> 3FF800H'22 :
     stall -> PC :
-    (Br & cond & u) -> off[17:0] + nxpc :
-    (Br & cond & ~u) -> C0[19:2] : nxpc;
+    (Br & cond & u) -> offL[21:0]  + nxpc :
+    (Br & cond & ~u) -> C0[23:2] : nxpc;
 
   sa := aluRes.31;
   sb := B.31;
   sc := C1.31;
+
   stall := stallL | stallM | stallD | stallFA | stallFM | stallFD | stallX;
   stallL := (Ldr | Str) & ~stall1;
   
+  (*assignments to registers*)
   PC := pcmux;
-  PMsel := ~rst | (pcmux[17:11] = 7FH'7);
-  IRBuf := stall -> IRBuf : codebus;
+  PMsel := ~rst | (pcmux[21:12] = 03FFH'10);
+  IR := stall -> IR : codebus;
   stall1 := stallX -> stall1 : stallL;
   R[ira0] := regwr -> regmux : A;
   N := regwr -> regmux.31 : N;
@@ -196,6 +214,6 @@ BEGIN
   C := Add -> (sb&sc) | (~sa&~sb&sc) | (~sa&sb&~sc&sa) :
     Sub -> (~sb&sc) | (sa&~sb&~sc) | (sa&sb&sc) : C;
   OV := Add -> (sa&~sb&~sc) | (~sa&sb&sc) :
-    Sub -> (sa&~sb&sc) | (~sa&sb&~sc) : OV;;
+    Sub -> (sa&~sb&sc) | (~sa&sb&~sc) : OV;
   H := Mul -> product[63:32] : Div -> remainder : H
 END RISC5.

BlackBox/Po/Files/RISC5.ucf

@@ -0,0 +1,121 @@
+NET "CLK50M" LOC = "T9" ;
+
+NET "TxD" LOC = "R13";
+NET "RxD" LOC = "T13";
+
+NET "btn[0]" LOC = "M13";
+NET "btn[1]" LOC = "M14";
+NET "btn[2]" LOC = "L13";
+NET "btn[3]" LOC = "L14";
+
+NET "swi[0]" LOC = "F12";
+NET "swi[1]" LOC = "G12";
+NET "swi[2]" LOC = "H14";
+NET "swi[3]" LOC = "H13";
+NET "swi[4]" LOC = "J14";
+NET "swi[5]" LOC = "J13";
+NET "swi[6]" LOC = "K14";
+NET "swi[7]" LOC = "K13";
+
+NET "leds[0]" LOC = "K12";
+NET "leds[1]" LOC = "P14";
+NET "leds[2]" LOC = "L12";
+NET "leds[3]" LOC = "N14";
+NET "leds[4]" LOC = "P13";
+NET "leds[5]" LOC = "N12";
+NET "leds[6]" LOC = "P12";
+NET "leds[7]" LOC = "P11";
+
+# SRAM
+NET "SRce0" LOC = "P7";
+NET "SRce1" LOC = "N5";
+NET "SRwe" LOC = "G3";
+NET "SRoe" LOC = "K4";
+NET "SRbe[0]" LOC = "P6";
+NET "SRbe[1]" LOC = "T4";
+NET "SRbe[2]" LOC = "P5";
+NET "SRbe[3]" LOC = "R4";
+NET "SRadr[0]" LOC = "L5";
+NET "SRadr[1]" LOC = "N3";
+NET "SRadr[2]" LOC = "M4";
+NET "SRadr[3]" LOC = "M3";
+NET "SRadr[4]" LOC = "L4";
+NET "SRadr[5]" LOC = "G4";
+NET "SRadr[6]" LOC = "F3";
+NET "SRadr[7]" LOC = "F4";
+NET "SRadr[8]" LOC = "E3";
+NET "SRadr[9]" LOC = "E4";
+NET "SRadr[10]" LOC = "G5";
+NET "SRadr[11]" LOC = "H3";
+NET "SRadr[12]" LOC = "H4";
+NET "SRadr[13]" LOC = "J4";
+NET "SRadr[14]" LOC = "J3";
+NET "SRadr[15]" LOC = "K3";
+NET "SRadr[16]" LOC = "K5";
+NET "SRadr[17]" LOC = "L3";
+NET "SRdat[0]" LOC = "N7";
+NET "SRdat[1]" LOC = "T8";
+NET "SRdat[2]" LOC = "R6";
+NET "SRdat[3]" LOC = "T5";
+NET "SRdat[4]" LOC = "R5";
+NET "SRdat[5]" LOC = "C2";
+NET "SRdat[6]" LOC = "C1";
+NET "SRdat[7]" LOC = "B1";
+NET "SRdat[8]" LOC = "D3";
+NET "SRdat[9]" LOC = "P8";
+NET "SRdat[10]" LOC = "F2";
+NET "SRdat[11]" LOC = "H1";
+NET "SRdat[12]" LOC = "J2";
+NET "SRdat[13]" LOC = "L2";
+NET "SRdat[14]" LOC = "P1";
+NET "SRdat[15]" LOC = "R1";
+NET "SRdat[16]" LOC = "P2";
+NET "SRdat[17]" LOC = "N2";
+NET "SRdat[18]" LOC = "M2";
+NET "SRdat[19]" LOC = "K1";
+NET "SRdat[20]" LOC = "J1";
+NET "SRdat[21]" LOC = "G2";
+NET "SRdat[22]" LOC = "E1";
+NET "SRdat[23]" LOC = "D1";
+NET "SRdat[24]" LOC = "D2";
+NET "SRdat[25]" LOC = "E2";
+NET "SRdat[26]" LOC = "G1";
+NET "SRdat[27]" LOC = "F5";
+NET "SRdat[28]" LOC = "C3";
+NET "SRdat[29]" LOC = "K2";
+NET "SRdat[30]" LOC = "M1";
+NET "SRdat[31]" LOC = "N1";
+
+# VGA port
+NET "Hsync"  LOC = "R9";
+NET "Vsync"  LOC = "T10";
+NET "RGB[0]" LOC = "R11";
+NET "RGB[1]" LOC = "T12";
+NET "RGB[2]" LOC = "R12";
+
+# keyboard
+NET "PS2C" LOC = "M16" |PULLUP;
+NET "PS2D" LOC = "M15" |PULLUP;
+
+# PS/2 mouse and SPI (SD-Card and Network) on A2 connector
+NET "msclk" LOC = "E6" |PULLUP;  # pin 4
+NET "msdat" LOC = "C5" |PULLUP;  # pin 6
+NET "MOSI[0]" LOC = "D6";  # pin 7
+NET "MOSI[1]" LOC = "B11";  # pin 29
+NET "SCLK[0]" LOC = "D8";  # pin 13
+NET "SCLK[1]" LOC = "B12";  # pin 30
+NET "SS[0]" LOC = "D5";  # pin 5
+NET "SS[1]" LOC = "A12";  # pin 31
+NET "MISO[0]" LOC = "B4" |PULLUP;  # pin 17
+NET "MISO[1]" LOC = "A10" |PULLUP;  # pin 28
+NET "NEN" LOC = "B13";  # pin 32
+
+# general-purpose I/O port
+NET "gpio[0]" LOC = "C10";
+NET "gpio[1]" LOC = "E10";
+NET "gpio[2]" LOC = "C11";
+NET "gpio[3]" LOC = "D11";
+NET "gpio[4]" LOC = "C12";
+NET "gpio[5]" LOC = "D12";
+NET "gpio[6]" LOC = "E11";
+NET "gpio[7]" LOC = "B16";

BlackBox/Po/Files/RISC5.v

@@ -0,0 +1,210 @@
+`timescale 1ns / 1ps  // 25.9.2015
+
+module RISC5(
+input clk, rst, stallX,
+input [31:0] inbus, codebus,
+output [23:0] adr,
+output rd, wr, ben,
+output [31:0] outbus);
+
+localparam StartAdr = 22'h3FF800;
+
+reg [21:0] PC;
+reg [31:0] IR;  // instruction register
+reg N, Z, C, OV;  // condition flags 
+reg [31:0] R [0:15];  // array of 16 registers
+reg [31:0] H;  // aux register
+reg stall1, PMsel;
+
+wire [31:0] ins, pmout;
+wire [21:0] pcmux, nxpc;
+wire cond, S;
+wire sa, sb, sc;
+
+wire p, q, u, v, w;  // instruction fields
+wire [3:0] op, ira, ira0, irb, irc;
+wire [2:0] cc;
+wire [15:0] imm;
+wire [19:0] off;
+wire [23:0] offL;
+
+wire regwr;
+wire stall, stallL, stallM, stallD, stallFA, stallFM, stallFD;
+wire [1:0] sc1, sc0;  // shift counts
+
+wire a0, a1, a2, a3;
+wire [7:0] inbusL, outbusB0, outbusB1, outbusB2, outbusB3;
+wire [23:0] inbusH;
+
+wire [31:0] A, B, C0, C1, aluRes, regmux;
+wire [31:0] s1, s2, s3, t1, t2, t3;
+wire [31:0] quotient, remainder;
+wire [63:0] product;
+wire [31:0] fsum, fprod, fquot;
+
+wire MOV, LSL, ASR, ROR, AND, ANN, IOR, XOR;  // operation signals
+wire ADD, SUB, MUL, DIV; wire FAD, FSB, FML, FDV;
+wire LDR, STR, BR;
+
+PROM PM (.adr(pcmux[8:0]), .data(pmout), .clk(clk));
+
+Multiplier mulUnit (.clk(clk), .run(MUL), .stall(stallM),
+   .u(~u), .x(B), .y(C1), .z(product));
+
+Divider divUnit (.clk(clk), .run(DIV), .stall(stallD),
+   .u(~u), .x(B), .y(C1), .quot(quotient), .rem(remainder));
+
+FPAdder fpaddx (.clk(clk), .run(FAD|FSB), .u(u), .v(v), .stall(stallFA),
+   .x(B), .y({FSB^C0[31], C0[30:0]}), .z(fsum));
+
+FPMultiplier fpmulx (.clk(clk), .run(FML), .stall(stallFM),
+   .x(B), .y(C0), .z(fprod));
+
+FPDivider fpdivx (.clk(clk), .run(FDV), .stall(stallFD),
+   .x(B), .y(C0), .z(fquot));
+
+assign ins = PMsel ? pmout : IR;  // decoding
+assign p = ins[31];
+assign q = ins[30];
+assign u = ins[29];
+assign v = ins[28];
+assign w = ins[16];
+assign cc  = ins[26:24];
+assign ira = ins[27:24];
+assign irb = ins[23:20];
+assign op  = ins[19:16];
+assign irc = ins[3:0];
+assign imm = ins[15:0];   // reg instr.
+assign off = ins[19:0];   // mem instr.
+assign offL = ins[23:0];  // branch instr.
+
+assign MOV = ~p & (op == 0);
+assign LSL = ~p & (op == 1);
+assign ASR = ~p & (op == 2);
+assign ROR = ~p & (op == 3);
+assign AND = ~p & (op == 4);
+assign ANN = ~p & (op == 5);
+assign IOR = ~p & (op == 6);
+assign XOR = ~p & (op == 7);
+
+assign ADD = ~p & (op == 8);
+assign SUB = ~p & (op == 9);
+assign MUL = ~p & (op == 10);
+assign DIV = ~p & (op == 11);
+assign FAD = ~p & (op == 12);
+assign FSB = ~p & (op == 13);
+assign FML = ~p & (op == 14);
+assign FDV = ~p & (op == 15);
+
+assign LDR = p & ~q & ~u;
+assign STR = p & ~q & u;
+assign BR = p & q;
+
+assign A = R[ira0];  // register data signals
+assign B = R[irb];
+assign C0 = R[irc];
+
+// Arithmetic-logical unit (ALU)
+assign ira0 = BR ? 15 : ira;
+assign C1 = q ? {{16{v}}, imm} : C0;
+assign adr = stallL ? B[23:0] + {4'b0, off} : {pcmux, 2'b00};
+assign rd = LDR & ~stallX & ~stall1;
+assign wr = STR & ~stallX & ~stall1;
+assign ben = p & ~q & v & ~stallX & ~stall1;  // byte enable
+
+assign sc0 = C1[1:0];
+assign sc1 = C1[3:2];
+
+// shifter for ASR and ROR
+assign s1 = (sc0 == 3) ? {(w ? B[2:0] : {3{B[31]}}), B[31:3]} :
+    (sc0 == 2) ? {(w ? B[1:0] : {2{B[31]}}), B[31:2]} :
+    (sc0 == 1) ? {(w ? B[0] : B[31]), B[31:1]} : B;
+assign s2 = (sc1 == 3) ? {(w ? s1[11:0] : {12{s1[31]}}), s1[31:12]} :
+    (sc1 == 2) ? {(w ? s1[7:0] : {8{s1[31]}}), s1[31:8]} :
+    (sc1 == 1) ? {(w ? s1[3:0] : {4{s1[31]}}), s1[31:4]} : s1;
+assign s3 = C1[4] ? {(w ? s2[15:0] : {16{s2[31]}}), s2[31:16]} : s2;
+
+// shifter for LSL
+assign t1 = (sc0 == 3) ? {B[28:0], 3'b0} :
+    (sc0 == 2) ? {B[29:0], 2'b0} :
+    (sc0 == 1) ? {B[30:0], 1'b0} : B;
+assign t2 = (sc1 == 3) ? {t1[19:0], 12'b0} :
+    (sc1 == 2) ? {t1[23:0], 8'b0} :
+    (sc1 == 1) ? {t1[27:0], 4'b0} : t1;
+assign t3 = C1[4] ? {t2[15:0], 16'b0} : t2;
+
+assign aluRes =
+  MOV ? (q ?
+    (~u ? {{16{v}}, imm} : {imm, 16'b0}) :
+    (~u ? C0 : (~v ? H : {N, Z, C, OV, 20'b0, 8'h50}))) :
+  LSL ? t3 :
+  (ASR|ROR) ? s3 :
+  AND ? B & C1 :
+  ANN ? B & ~C1 :
+  IOR  ? B | C1 :
+  XOR ? B ^ C1 :
+  ADD ? B + C1 + (u & C) :
+  SUB ? B - C1 - (u & C) :
+  MUL ? product[31:0] :
+  DIV ? quotient :
+ (FAD|FSB) ? fsum :
+  FML ? fprod :
+  FDV ? fquot :
+  0;
+  
+assign regwr = ~p & ~stall | (LDR & ~stallX & ~stall1) | (BR & cond & v & ~stallX);
+assign a0 = ~adr[1] & ~adr[0];
+assign a1 = ~adr[1] & adr[0];
+assign a2 = adr[1] & ~adr[0];
+assign a3 = adr[1] & adr[0];
+assign inbusL = (~ben | a0) ? inbus[7:0] :
+  a1 ? inbus[15:8] : a2 ? inbus[23:16] : inbus[31:24];
+assign inbusH = ~ben ? inbus[31:8] : 24'b0;
+assign regmux = LDR ? {inbusH, inbusL} : (BR & v) ? {8'b0, nxpc, 2'b0} : aluRes;
+
+assign outbusB0 = A[7:0];
+assign outbusB1 = ben & a1 ? A[7:0] : A[15:8];
+assign outbusB2 = ben & a2 ? A[7:0] : A[23:16];
+assign outbusB3 = ben & a3 ? A[7:0] : A[31:24];
+assign outbus = {outbusB3, outbusB2, outbusB1, outbusB0};
+
+// Control unit CU
+assign S = N ^ OV;
+assign nxpc = PC + 1;
+assign cond = ins[27] ^
+  ((cc == 0) & N | // MI, PL
+   (cc == 1) & Z | // EQ, NE
+   (cc == 2) & C | // CS, CC
+   (cc == 3) & OV | // VS, VC
+   (cc == 4) & (C|Z) | // LS, HI
+   (cc == 5) & S | // LT, GE
+   (cc == 6) & (S|Z) | // LE, GT
+   (cc == 7)); // T, F
+
+assign pcmux = ~rst ? StartAdr :
+  stall ? PC :
+  (BR & cond & u) ? offL[21:0] + nxpc :
+  (BR & cond & ~u) ? C0[23:2] : nxpc;
+  
+assign sa = aluRes[31];
+assign sb = B[31];
+assign sc = C1[31];
+
+assign stall = stallL | stallM | stallD | stallX | stallFA | stallFM | stallFD;
+assign stallL = (LDR|STR) & ~stall1;
+
+always @ (posedge clk) begin
+  PC <= pcmux;
+  PMsel <= ~rst | (pcmux[21:12] == 10'h3FF);
+  IR <= stall ? IR : codebus;
+  stall1 <= stallX ? stall1 : stallL;
+  R[ira0] <= regwr ? regmux : A;
+  N <= regwr ? regmux[31] : N;
+  Z <= regwr ? (regmux == 0) : Z;
+  C <= ADD ? (~sb&sc&~sa) | (sb&sc&sa) | (sb&~sa) :
+	 SUB ? (~sb&sc&~sa) | (sb&sc&sa) | (~sb&sa) : C;
+  OV <= ADD ? (sa&~sb&~sc) | (~sa&sb&sc): 
+	 SUB ? (sa&~sb&sc) | (~sa&sb&~sc) : OV;
+  H <= MUL ? product[63:32] : DIV ? remainder : H;
+end 
+endmodule 

BlackBox/Po/Files/RISC5Top.Lola.txt

@@ -1,4 +1,4 @@
-MODULE RISC5Top(   (*NW 4.12.2014*)
+MODULE RISC5Top(   (*NW 23.9.2015*)
   IN CLK50M: BIT;
   IN btn: [4] BIT;
   IN swi: BYTE;
@@ -8,14 +8,14 @@ MODULE RISC5Top(   (*NW 4.12.2014*)
   OUT SRce0, SRce1, SRwe, SRoe: BIT;  (*SRAM*)
   OUT SRbe: [4] BIT;
   OUT SRadr: [18] BIT;
-  OUT SRdat: WORD;
+  INOUT SRdat: WORD;
   IN MISO: [2] BIT;   (*SPI - SD card & network*)
   OUT SCLK, MOSI, SS: [2] BIT;
   OUT NEN: BIT;   (*network enable*)
   OUT hsync, vsync: BIT;   (*video control*)
   OUT RGB: [3] BIT;
-  INOUT PS2C, PS2D: BIT;   (*keyboard*)
-  INOUT mouse: [2] BIT;
+  IN PS2C, PS2D: BIT;   (*keyboard*)
+  INOUT msclk, msdat: BIT;
   INOUT gpio: BYTE);
 
 (* I/O addresses:
@@ -33,7 +33,7 @@ MODULE RISC5Top(   (*NW 4.12.2014*)
 TYPE RISC5 := MODULE (
     IN clk, rst, stallX: BIT;
       inbus, codebus: WORD;
-    OUT adr: [20] BIT;
+    OUT adr: [24] BIT;
       rd, wr, ben: BIT;
       outbus: WORD) ^;
 
@@ -57,7 +57,8 @@ TYPE RISC5 := MODULE (
       hsync, vsync: BIT; RGB: [3] BIT) ^;
 
   MouseP := MODULE ( 
-    IN clk, rst: BIT; INOUT io: [2] BIT;
+    IN clk, rst: BIT;
+    INOUT msclk, msdat: BIT;
     OUT out: [28] BIT) ^;
 
   PS2 = MODULE (
@@ -65,18 +66,7 @@ TYPE RISC5 := MODULE (
     OUT rdy, shift: BIT; data: BYTE;
     IN PS2C, PS2D: BIT) ^;
 
-  IOBUF32 = MODULE (
-    IN I: WORD; OUT O: WORD; INOUT IO: WORD; IN T: BIT) ^;
-
-  IOBUF8 = MODULE (
-    IN I: BYTE; OUT O: BYTE; INOUT IO: BYTE; IN T: BYTE) ^;
-
-  IBUFG := MODULE (IN I: BIT; OUT O: BIT) ^;
-  BUFG := MODULE (IN I: BIT; OUT O: BIT) ^;
-  IOBUF := MODULE (IN I: BIT; OUT O: BIT; INOUT IO: BIT; IN T: BIT) ^;
-
-VAR clk, clk50: BIT;
-REG (clk50) clk25: BIT;
+REG (CLK50M) clk: BIT;
 REG (clk) rst: BIT;
   bitrate: BIT;   (*RS-232*)
   Lreg: BYTE;  (*LED*)
@@ -92,20 +82,14 @@ VAR riscx: RISC5;
   vid: VID;
   kbd: PS2;
   Ms: MouseP;
-  clkInBuf: IBUFG;
-  clk150buf: BUFG;
-  sramBuf: IOBUF32;
-  gpioBuf: IOBUF8;
 
   dmy: BIT;
-  adr: [20] BIT;
+  adr: [24] BIT;
   iowadr: [4] BIT;  (*word adress*)
-  rd, wr, be, ioenb, dspreq: BIT;
+  rd, wr, ben, ioenb, dspreq: BIT;
   be0, be1: BIT;
-  a0, a1, a2, a3: BIT;
-  inbus, inbus0, inbus1, outbus, outbus1: WORD;
-  inbusL, outbusB0, outbusB1, outbusB2, outbusB3: BYTE;
-  inbusH: [24] BIT;
+  inbus, inbus0: WORD;  (*data to RISC6 core*)
+  outbus: WORD;   (*data from RISC6 core*)
 
   dataTx, dataRx, dataKbd: BYTE;
   rdyRx, doneRx, startTx, rdyTx, rdyKbd, doneKbd: BIT;
@@ -117,18 +101,18 @@ VAR riscx: RISC5;
   gpin: BYTE;
 
 BEGIN
-  riscx (clk, rst, dspreq, inbus, inbus1, adr, rd, wr, be, outbus);
+  riscx (clk, rst, dspreq, inbus, inbus0, adr, rd, wr, ben, outbus);
   receiver (clk, rst, doneRx, RxD, bitrate, rdyRx, dataRx);
   transmitter (clk, rst, startTx, bitrate, dataTx, rdyTx, TxD);
   spi (clk, rst, spiStart, spiCtrl.2, outbus, spiRx, spiRdy, MISO.0 & MISO.1, MOSI1, SCLK1); 
-  vid (clk, swi.7, inbus1, dspreq, vidadr, hsync, vsync, RGB);
+  vid (clk, swi.7, inbus0, dspreq, vidadr, hsync, vsync, RGB);
   kbd (clk, rst, doneKbd, rdyKbd, dmy, dataKbd, PS2C, PS2D);
-  Ms (clk, rst, mouse, dataMs);
-  sramBuf (outbus1, inbus1, SRdat, ~wr);
-  gpioBuf (gpout, gpin, gpio, ~gpoc);
+  Ms (clk, rst, msclk, msdat, dataMs);
+  TS(SRdat, inbus0, outbus, ~wr);
+  TS(gpio, gpin, gpout, gpoc);
 
   iowadr := adr[5:2];
-  ioenb := (adr[19:6] = 3FFFH'14);
+  ioenb := (adr[23:6] = 3FFFFH'18);
   inbus := ~ioenb -> inbus0 :
     ((iowadr = 0) -> cnt1 :
     (iowadr = 1) -> {0'20, btn, swi} :
@@ -142,31 +126,15 @@ BEGIN
     (iowadr = 9) -> {0'24, gpoc} : 0'32);
 
 (*access to SRAM*)
-  a0 := ~adr[1] & ~adr[0];
-  a1 := ~adr[1] & adr[0];
-  a2 := adr[1] & ~adr[0];
-  a3 := adr[1] & adr[0];
-  be0 := be & adr.0;
-  be1 := be & ~adr.0;
-  SRce0 := be & adr[1];
-  SRce1 := be & ~adr[1];
-  SRwe := ~wr | clk25;
+  be0 := ben & adr.0;
+  be1 := ben & ~adr.0;
+  SRce0 := ben & adr.1;
+  SRce1 := ben & ~adr.1;
+  SRwe := ~wr | clk;
   SRoe := wr;
   SRbe := {be1, be0, be1, be0};
   SRadr := dspreq -> vidadr : adr[19:2];
 
-  inbusL := (~be | a0) -> inbus1[7:0] :
-    a1 -> inbus1[15:8] :
-    a2 -> inbus1[23:16] : inbus1[31:24];
-  inbusH := ~be -> inbus1[31:8] : 0'24;
-  inbus0 := {inbusH, inbusL};
-
-  outbusB0 := outbus[7:0];
-  outbusB1 := be & a1 -> outbus[7:0] : outbus[15:8];
-  outbusB2 := be & a2 -> outbus[7:0] : outbus[23:16];
-  outbusB3 := be & a3 -> outbus[7:0] : outbus[31:24];
-  outbus1 := {outbusB3, outbusB2, outbusB1, outbusB0};
-
   dataTx := outbus[7:0];
   startTx := wr & ioenb & (iowadr = 2);
   doneRx := rd & ioenb & (iowadr = 2);
@@ -187,8 +155,5 @@ BEGIN
   cnt0 := limit -> 0 : cnt0 + 1;
   cnt1 := cnt1 + limit;
 
-(* The clocks *)
-  clkInBuf (CLK50M, clk50);
-  clk25 := ~clk25;  (* @ 50 MHz *)
-  clk150buf (clk25, clk);
+  clk := ~clk  (* @ 50 MHz *)
 END RISC5Top.

BlackBox/Po/Files/RISC5Top.v

@@ -0,0 +1,138 @@
+`timescale 1ns / 1ps  // 22.9.2015
+// with SRAM, byte access, flt.-pt., and gpio
+// PS/2 mouse and network 7.1.2014 PDR
+
+module RISC5Top(
+  input CLK50M,
+  input [3:0] btn,
+  input [7:0] swi,
+  input  RxD,   // RS-232
+  output TxD,
+  output [7:0] leds,
+  output SRce0, SRce1, SRwe, SRoe,  //SRAM
+  output [3:0] SRbe,
+  output [17:0] SRadr,
+  inout [31:0] SRdat,
+  input [1:0] MISO,          // SPI - SD card & network
+  output [1:0] SCLK, MOSI,
+  output [1:0] SS,
+  output NEN,  // network enable
+  output hsync, vsync, // video controller
+  output [2:0] RGB,
+  input PS2C, PS2D,    // keyboard
+  inout msclk, msdat,
+  inout [7:0] gpio);
+
+// IO addresses for input / output
+// 0  milliseconds / --
+// 1  switches / LEDs
+// 2  RS-232 data / RS-232 data (start)
+// 3  RS-232 status / RS-232 control
+// 4  SPI data / SPI data (start)
+// 5  SPI status / SPI control
+// 6  PS2 keyboard / --
+// 7  mouse / --
+// 8  general-purpose I/O data
+// 9  general-purpose I/O tri-state control
+
+reg rst, clk;
+wire[23:0] adr;
+wire [3:0] iowadr; // word address
+wire [31:0] inbus, inbus0;  // data to RISC core
+wire [31:0] outbus;  // data from RISC core
+wire rd, wr, ben, ioenb, dspreq;
+
+wire [7:0] dataTx, dataRx, dataKbd;
+wire rdyRx, doneRx, startTx, rdyTx, rdyKbd, doneKbd;
+wire [27:0] dataMs;
+reg bitrate;  // for RS232
+wire limit;  // of cnt0
+
+reg [7:0] Lreg;
+reg [15:0] cnt0;
+reg [31:0] cnt1; // milliseconds
+
+wire [31:0] spiRx;
+wire spiStart, spiRdy;
+reg [3:0] spiCtrl;
+wire [17:0] vidadr;
+reg [7:0] gpout, gpoc;
+wire [7:0] gpin;
+
+RISC5 riscx(.clk(clk), .rst(rst), .rd(rd), .wr(wr), .ben(ben), .stallX(dspreq),
+   .adr(adr), .codebus(inbus0), .inbus(inbus), .outbus(outbus));
+RS232R receiver(.clk(clk), .rst(rst), .RxD(RxD), .fsel(bitrate), .done(doneRx),
+   .data(dataRx), .rdy(rdyRx));
+RS232T transmitter(.clk(clk), .rst(rst), .start(startTx), .fsel(bitrate),
+   .data(dataTx), .TxD(TxD), .rdy(rdyTx));
+SPI spi(.clk(clk), .rst(rst), .start(spiStart), .dataTx(outbus),
+   .fast(spiCtrl[2]), .dataRx(spiRx), .rdy(spiRdy),
+ 	.SCLK(SCLK[0]), .MOSI(MOSI[0]), .MISO(MISO[0] & MISO[1]));
+VID vid(.clk(clk), .req(dspreq), .inv(swi[7]),
+   .vidadr(vidadr), .viddata(inbus0), .RGB(RGB), .hsync(hsync), .vsync(vsync));
+PS2 kbd(.clk(clk), .rst(rst), .done(doneKbd), .rdy(rdyKbd), .shift(),
+   .data(dataKbd), .PS2C(PS2C), .PS2D(PS2D));
+MouseP Ms(.clk(clk), .rst(rst), .msclk(msclk), .msdat(msdat), .out(dataMs));
+
+assign iowadr = adr[5:2];
+assign ioenb = (adr[23:6] == 18'h3FFFF);
+assign inbus = ~ioenb ? inbus0 :
+   ((iowadr == 0) ? cnt1 :
+    (iowadr == 1) ? {20'b0, btn, swi} :
+    (iowadr == 2) ? {24'b0, dataRx} :
+    (iowadr == 3) ? {30'b0, rdyTx, rdyRx} :
+    (iowadr == 4) ? spiRx :
+    (iowadr == 5) ? {31'b0, spiRdy} :
+    (iowadr == 6) ? {3'b0, rdyKbd, dataMs} :
+    (iowadr == 7) ? {24'b0, dataKbd} :
+    (iowadr == 8) ? {24'b0, gpin} :
+    (iowadr == 9) ? {24'b0, gpoc} : 0);
+	 
+assign SRce0 = ben & adr[1];
+assign SRce1 = ben & ~adr[1];
+assign SRbe0 = ben & adr[0];
+assign SRbe1 = ben & ~adr[0];
+assign SRwe = ~wr | clk;
+assign SRoe = wr;
+assign SRbe = {SRbe1, SRbe0, SRbe1, SRbe0};
+assign SRadr = dspreq ? vidadr : adr[19:2];
+
+genvar i;
+generate // tri-state buffer for SRAM
+  for (i = 0; i < 32; i = i+1)
+  begin: bufblock
+    IOBUF SRbuf (.I(outbus[i]), .O(inbus0[i]), .IO(SRdat[i]), .T(~wr));
+  end
+endgenerate
+
+generate // tri-state buffer for gpio port
+  for (i = 0; i < 8; i = i+1)
+  begin: gpioblock
+    IOBUF gpiobuf (.I(gpout[i]), .O(gpin[i]), .IO(gpio[i]), .T(~gpoc[i]));
+  end
+endgenerate
+
+assign dataTx = outbus[7:0];
+assign startTx = wr & ioenb & (iowadr == 2);
+assign doneRx = rd & ioenb & (iowadr == 2);
+assign limit = (cnt0 == 24999);
+assign leds = Lreg;
+assign spiStart = wr & ioenb & (iowadr == 4);
+assign SS = ~spiCtrl[1:0];  //active low slave select
+assign MOSI[1] = MOSI[0], SCLK[1] = SCLK[0], NEN = spiCtrl[3];
+assign doneKbd = rd & ioenb & (iowadr == 7);
+
+always @(posedge clk)
+begin
+  rst <= ((cnt1[4:0] == 0) & limit) ? ~btn[3] : rst;
+  Lreg <= ~rst ? 0 : (wr & ioenb & (iowadr == 1)) ? outbus[7:0] : Lreg;
+  cnt0 <= limit ? 0 : cnt0 + 1;
+  cnt1 <= cnt1 + limit;
+  spiCtrl <= ~rst ? 0 : (wr & ioenb & (iowadr == 5)) ? outbus[3:0] : spiCtrl;
+  bitrate <= ~rst ? 0 : (wr & ioenb & (iowadr == 3)) ? outbus[0] : bitrate;
+  gpout <= (wr & ioenb & (iowadr == 8)) ? outbus[7:0] : gpout;
+  gpoc <= ~rst ? 0 : (wr & ioenb & (iowadr == 9)) ? outbus[7:0] : gpoc;
+end
+
+always @ (posedge CLK50M) clk <= ~clk;
+endmodule

BlackBox/Po/Files/RS232R.Lola.txt

@@ -1,7 +1,8 @@
-MODULE RS232R (    (*NW 15.9.2014*)
+MODULE RS232R (    (*NW 10.8.2015*)
   IN clk, rst, done, RxD, fsel: BIT;
   OUT rdy: BIT; data: BYTE);
   REG (clk) run, stat: BIT;
+    Q0, Q1: BIT;   (*synchronizer and edge detector*)
     tick: [12] BIT;
     bitcnt: [4] BIT;
     shreg: BYTE;
@@ -15,11 +16,12 @@ BEGIN
   data := shreg;
   rdy := stat;
 
-  run := ~RxD | ~(~rst | endtick & endbit) & run;
+  Q0 := RxD; Q1 := Q0;
+  run := (Q1 & ~Q0) | ~(~rst | endtick & endbit) & run;
   tick := (run & ~endtick) -> tick + 1 : 0;
   bitcnt := (endtick & ~endbit) -> bitcnt + 1 :
     (endtick & endbit) -> 0 : bitcnt;
-  shreg := midtick -> {RxD, shreg[7:1]} : shreg;
+  shreg := midtick -> {Q1, shreg[7:1]} : shreg;
   stat := (endtick & endbit) | ~(~rst | done) & stat
 END RS232R.
 

BlackBox/Po/Files/RS232R.v

@@ -0,0 +1,38 @@
+`timescale 1ns / 1ps  // NW 4.5.09 / 15.11.10
+
+// RS232 receiver for 19200 or 115200 bps, 8 bit data
+// clock is 25 MHz
+
+module RS232R(
+    input clk, rst,
+	 input RxD,
+    input fsel,
+    input done,   // "byte has been read"
+    output rdy,
+    output [7:0] data);
+
+wire endtick, midtick, endbit;
+wire [11:0] limit;
+reg run, stat;
+reg Q0, Q1;  // synchronizer and edge detector
+reg [11:0] tick;
+reg [3:0] bitcnt;
+reg [7:0] shreg;
+
+assign limit = fsel ? 217 : 1302;
+assign endtick = tick == limit;
+assign midtick = tick == {1'b0, limit[11:1]};  // limit/2
+assign endbit = bitcnt == 8;
+assign data = shreg;
+assign rdy = stat;
+
+always @ (posedge clk) begin
+  Q0 <= RxD; Q1 <= Q0;
+  run <= (Q1 & ~Q0) | ~(~rst | endtick & endbit) & run;
+  tick <= (run & ~endtick) ? tick+1 : 0;
+  bitcnt <= (endtick & ~endbit) ? bitcnt + 1 :
+    (endtick & endbit) ? 0 : bitcnt;
+  shreg <= midtick ? {Q1, shreg[7:1]} : shreg;
+  stat <= (endtick & endbit) | ~(~rst | done) & stat;
+end
+endmodule

BlackBox/Po/Files/RS232T.v

@@ -0,0 +1,35 @@
+`timescale 1ns / 1ps  // NW 4.5.09 / 15.8.10 / 15.11.10
+
+// RS232 transmitter for 19200 bps, 8 bit data
+// clock is 25 MHz; 25000 / 1302 = 19.2 KHz
+
+module RS232T(
+    input clk, rst,
+    input start, // request to accept and send a byte
+	 input fsel,  // frequency selection
+    input [7:0] data,
+    output rdy,
+    output TxD);
+
+wire endtick, endbit;
+wire [11:0] limit;
+reg run;
+reg [11:0] tick;
+reg [3:0] bitcnt;
+reg [8:0] shreg;
+
+assign limit = fsel ? 217 : 1302;
+assign endtick = tick == limit;
+assign endbit = bitcnt == 9;
+assign rdy = ~run;
+assign TxD = shreg[0];
+
+always @ (posedge clk) begin
+  run <= (~rst | endtick & endbit) ? 0 : start ? 1 : run;
+  tick <= (run & ~endtick) ? tick + 1 : 0;
+  bitcnt <= (endtick & ~endbit) ? bitcnt + 1 :
+    (endtick & endbit) ? 0 : bitcnt;
+  shreg <= (~rst) ? 1 : start ? {data, 1'b0} :
+    endtick ? {1'b1, shreg[8:1]} : shreg;
+end
+endmodule

BlackBox/Po/Files/SPI.v

@@ -0,0 +1,36 @@
+`timescale 1ns / 1ps
+
+// Motorola Serial Peripheral Interface (SPI) PDR 23.3.12 / 16.10.13
+// transmitter / receiver of words (fast, clk/3) or bytes (slow, clk/64)
+// e.g 8.33MHz or ~400KHz respectively at 25MHz (slow needed for SD-card init)
+// note: bytes are always MSbit first; but if fast, words are LSByte first
+
+module SPI(
+  input clk, rst,
+  input start, fast,
+  input [31:0] dataTx,
+  output [31:0] dataRx,
+  output reg rdy,
+  input MISO, output MOSI, output SCLK);
+
+wire endbit, endtick;
+reg [31:0] shreg;
+reg [5:0] tick;
+reg [4:0] bitcnt;
+
+assign endtick = fast ? (tick == 2) : (tick == 63);  //25MHz clk
+assign endbit = fast ? (bitcnt == 31) : (bitcnt == 7);
+assign dataRx = fast ? shreg : {24'b0, shreg[7:0]};
+assign MOSI = (~rst | rdy) ? 1 : shreg[7];
+assign SCLK = (~rst | rdy) ? 0 : fast ? endtick : tick[5];
+
+always @ (posedge clk) begin
+  tick <= (~rst | rdy | endtick) ? 0 : tick + 1;
+  rdy <= (~rst | endtick & endbit) ? 1 : start ? 0 : rdy;
+  bitcnt <= (~rst | start) ? 0 : (endtick & ~endbit) ? bitcnt + 1 : bitcnt;
+  shreg <= ~rst ? -1 : start ? dataTx : endtick ?
+    {shreg[30:24], MISO, shreg[22:16], shreg[31], shreg[14:8],
+       shreg[23], shreg[6:0], (fast ? shreg[15] : MISO)} : shreg;
+end
+
+endmodule

BlackBox/Po/Files/SmallPrograms.Lola.txt

@@ -0,0 +1,36 @@
+(*  LSC.Compile @    LSV.List Test.Lola.v  *)
+
+MODULE Counter (IN CLK50M, rstIn: BIT;
+  IN swi: BYTE; OUT leds: BYTE);
+REG (CLK50M) rst: BIT;
+  cnt0: [16] BIT;  (*milliseconds*)
+  cnt1: [10] BIT;  (*half seconds*)
+  cnt2: [8] BIT;
+VAR tick0, tick1: BIT;
+  BEGIN leds := swi.7 -> swi :  cnt2;
+  tick0 := (cnt0 = 24999);
+  tick1 := tick0 & (cnt1 = 499);
+  rst := ~rstIn;
+  cnt0 := ~rst -> 0 : tick0 -> 0 : cnt0 + 1;
+  cnt1 := ~rst -> 0 : tick1 -> 0 : cnt1 + tick0;
+  cnt2 := ~rst -> 0 : cnt2 + tick1
+END Counter.
+
+MODULE Shifter(IN CLK50M, rstIn: BIT;
+  IN swi: BYTE; OUT leds: BYTE);
+REG (CLK50M) rst, up: BIT;
+  cnt0: [16] BIT;  (*milliseconds*)
+  cnt1: [10] BIT;  (*half seconds*)
+  shreg: [8] BIT;
+VAR tick0, tick1: BIT;
+BEGIN leds := swi.7 -> swi :  shreg;
+  tick0 := (cnt0 = 24999);
+  tick1 := tick0 & (cnt1 = 499);
+  rst := ~rstIn;
+  cnt0 := ~rst -> 0 : tick0 -> 0 : cnt0 + 1;
+  cnt1 := ~rst -> 0 : tick1 -> 0 : cnt1 + tick0;
+  shreg := ~rst -> 1'8 :
+    ~tick1 -> shreg  :
+    up -> {shreg[6:0], 0'1} : {0'1, shreg[7:1]};
+  up := shreg.0 -> 1 : shreg.7 -> 0 : up
+END Shifter.

BlackBox/Po/Files/TextFrames.Mod.txt

@@ -1,4 +1,4 @@
-MODULE TextFrames; (*JG 8.10.90 / NW 10.5.2013*)
+MODULE TextFrames; (*JG 8.10.90 / NW 10.5.2013 / 15.10.2015*)
   IMPORT Modules, Input, Display, Viewers, Fonts, Texts, Oberon, MenuViewers;
 
   CONST replace* = 0; insert* = 1; delete* = 2; unmark* = 3; (*message id*)
@@ -116,7 +116,7 @@ MODULE TextFrames; (*JG 8.10.90 / NW 10.5.2013*)
     VAR R: Texts.Reader; X, Y: INTEGER; len: LONGINT);
     VAR patadr, NX, Xlim, dx, x, y, w, h: INTEGER;
   BEGIN NX := F.X + F.W; Xlim := NX - 40;
-    WHILE (nextCh # CR) & ((nextCh > " ") OR (X < Xlim)) & (R.fnt # NIL) DO
+    WHILE (nextCh # CR) & (R.fnt # NIL) DO
       Fonts.GetPat(R.fnt, nextCh, dx, x, y, w, h, patadr);
       IF (X + x + w <= NX) & (h # 0) THEN
         Display.CopyPattern(R.col, patadr, X + x, Y + y, Display.invert)

BlackBox/Po/Files/VID.v

@@ -0,0 +1,46 @@
+`timescale 1ns / 1ps
+// 1024x768 display controller NW/PR 24.1.2014
+
+module VID(
+    input clk, inv,
+    input [31:0] viddata,
+    output reg req,  // SRAM read request
+    output [17:0] vidadr,
+    output hsync, vsync,  // to display
+    output [2:0] RGB);
+
+localparam Org = 18'b1101_1111_1111_0000_00;  // DFF00: adr of vcnt=1023
+reg [10:0] hcnt;
+reg [9:0] vcnt;
+reg [4:0] hword;  // from hcnt, but latched in the clk domain
+reg [31:0] vidbuf, pixbuf;
+reg hblank;
+wire pclk, hend, vend, vblank, xfer, vid;
+
+assign hend = (hcnt == 1343), vend = (vcnt == 801);
+assign vblank = (vcnt[8] & vcnt[9]);  // (vcnt >= 768)
+assign hsync = ~((hcnt >= 1080+6) & (hcnt < 1184+6));  // -ve polarity
+assign vsync = (vcnt >= 771) & (vcnt < 776);  // +ve polarity
+assign xfer = (hcnt[4:0] == 6);  // data delay > hcnt cycle + req cycle
+assign vid = (pixbuf[0] ^ inv) & ~hblank & ~vblank;
+assign RGB = {vid, vid, vid};
+assign vidadr = Org + {3'b0, ~vcnt, hword};
+
+always @(posedge pclk) begin  // pixel clock domain
+  hcnt <= hend ? 0 : hcnt+1;
+  vcnt <= hend ? (vend ? 0 : (vcnt+1)) : vcnt;
+  hblank <= xfer ? hcnt[10] : hblank;  // hcnt >= 1024
+  pixbuf <= xfer ? vidbuf : {1'b0, pixbuf[31:1]};
+end
+
+always @(posedge clk) begin  // CPU (SRAM) clock domain
+  hword <= hcnt[9:5];
+  req <= ~vblank & ~hcnt[10] & (hcnt[5] ^ hword[0]);  // i.e. adr changed
+  vidbuf <= req ? viddata : vidbuf;
+end
+
+// pixel clock generation
+(* LOC = "DCM_X1Y1" *) DCM #(.CLKFX_MULTIPLY(3), .CLK_FEEDBACK("NONE"))
+  dcm(.CLKIN(clk), .CLKFX(pclk));
+
+endmodule