FoxAMDBackend.Mod 142 KB

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  1. MODULE FoxAMDBackend; (** AUTHOR ""; PURPOSE ""; *)
  2. IMPORT
  3. Basic := FoxBasic, Scanner := FoxScanner, SyntaxTree := FoxSyntaxTree, Global := FoxGlobal, Backend := FoxBackend, Sections := FoxSections,
  4. IntermediateCode := FoxIntermediateCode, IntermediateBackend := FoxIntermediateBackend, BinaryCode := FoxBinaryCode,
  5. InstructionSet := FoxAMD64InstructionSet, Assembler := FoxAMD64Assembler, SemanticChecker := FoxSemanticChecker, Formats := FoxFormats,
  6. Diagnostics, Streams, Options, Strings, ObjectFileFormat := FoxBinaryObjectFile, Compiler,
  7. Machine, D := Debugging, CodeGenerators := FoxCodeGenerators, ObjectFile;
  8. CONST
  9. (* constants for the register allocator *)
  10. none=-1;
  11. RAX=InstructionSet.regRAX; RCX=InstructionSet.regRCX; RDX=InstructionSet.regRDX; RBX=InstructionSet.regRBX;
  12. RSP=InstructionSet.regRSP; RBP=InstructionSet.regRBP; RSI=InstructionSet.regRSI; RDI=InstructionSet.regRDI;
  13. R8=InstructionSet.regR8; R9=InstructionSet.regR9; R10=InstructionSet.regR10; R11=InstructionSet.regR11;
  14. R12=InstructionSet.regR12; R13=InstructionSet.regR13; R14=InstructionSet.regR14; R15=InstructionSet.regR15;
  15. EAX=InstructionSet.regEAX; ECX=InstructionSet.regECX; EDX=InstructionSet.regEDX; EBX=InstructionSet.regEBX;
  16. ESP=InstructionSet.regESP; EBP=InstructionSet.regEBP; ESI=InstructionSet.regESI; EDI=InstructionSet.regEDI;
  17. R8D=InstructionSet.regR8D; R9D=InstructionSet.regR9D; R10D=InstructionSet.regR10D; R11D=InstructionSet.regR11D;
  18. R12D=InstructionSet.regR12D; R13D=InstructionSet.regR13D; R14D=InstructionSet.regR14D; R15D=InstructionSet.regR15D;
  19. AX=InstructionSet.regAX; CX=InstructionSet.regCX; DX=InstructionSet.regDX; BX=InstructionSet.regBX;
  20. SI=InstructionSet.regSI; DI=InstructionSet.regDI; BP=InstructionSet.regBP; SP=InstructionSet.regSP;
  21. R8W=InstructionSet.regR8W; R9W=InstructionSet.regR9W; R10W=InstructionSet.regR10W; R11W=InstructionSet.regR11W;
  22. R12W=InstructionSet.regR12W; R13W=InstructionSet.regR13W; R14W=InstructionSet.regR14W; R15W=InstructionSet.regR15W;
  23. AL=InstructionSet.regAL; CL=InstructionSet.regCL; DL=InstructionSet.regDL; BL=InstructionSet.regBL; SIL=InstructionSet.regSIL;
  24. DIL=InstructionSet.regDIL; BPL=InstructionSet.regBPL; SPL=InstructionSet.regSPL;
  25. R8B=InstructionSet.regR8B; R9B=InstructionSet.regR9B; R10B=InstructionSet.regR10B; R11B=InstructionSet.regR11B;
  26. R12B=InstructionSet.regR12B; R13B=InstructionSet.regR13B; R14B=InstructionSet.regR14B; R15B=InstructionSet.regR15B;
  27. AH=InstructionSet.regAH; CH=InstructionSet.regCH; DH=InstructionSet.regDH; BH=InstructionSet.regBH;
  28. ST0=InstructionSet.regST0;
  29. XMM0 = InstructionSet.regXMM0;
  30. XMM7 = InstructionSet.regXMM7;
  31. YMM0 = InstructionSet.regYMM0;
  32. YMM7 = InstructionSet.regYMM7;
  33. Low=0; High=1;
  34. FrameSpillStack=TRUE;
  35. VAR registerOperands: ARRAY InstructionSet.numberRegisters OF Assembler.Operand;
  36. usePool: BOOLEAN;
  37. opEAX, opECX, opEDX, opEBX, opESP, opEBP,
  38. opESI, opEDI, opAX, opCX, opDX, opBX, opSI, opDI, opAL, opCL, opDL, opBL, opAH, opCH, opDH, opBH,opST0
  39. , opRSP, opRBP: Assembler.Operand;
  40. unusable,split,blocked,free: CodeGenerators.Ticket;
  41. traceStackSize: LONGINT;
  42. TYPE
  43. Ticket=CodeGenerators.Ticket;
  44. PhysicalRegisters*=OBJECT (CodeGenerators.PhysicalRegisters)
  45. VAR
  46. toVirtual: ARRAY InstructionSet.numberRegisters OF Ticket; (* registers real register -> none / reserved / split / blocked / virtual register (>0) *)
  47. reserved: ARRAY InstructionSet.numberRegisters OF BOOLEAN;
  48. hint: LONGINT;
  49. useFPU: BOOLEAN;
  50. PROCEDURE &InitPhysicalRegisters(fpu,cooperative: BOOLEAN);
  51. VAR i: LONGINT;
  52. BEGIN
  53. FOR i := 0 TO LEN(toVirtual)-1 DO
  54. toVirtual[i] := NIL;
  55. reserved[i] := FALSE;
  56. END;
  57. (* reserve stack and base pointer registers *)
  58. toVirtual[BPL] := unusable;
  59. toVirtual[SPL] := unusable;
  60. toVirtual[BP] := unusable;
  61. toVirtual[SP] := unusable;
  62. toVirtual[EBP] := unusable;
  63. toVirtual[ESP] := unusable;
  64. toVirtual[RBP] := unusable;
  65. toVirtual[RSP] := unusable;
  66. hint := none;
  67. useFPU := fpu
  68. END InitPhysicalRegisters;
  69. PROCEDURE AllocationHint*(index: LONGINT);
  70. BEGIN hint := index
  71. END AllocationHint;
  72. PROCEDURE NumberRegisters*(): LONGINT;
  73. BEGIN
  74. RETURN LEN(toVirtual)
  75. END NumberRegisters;
  76. END PhysicalRegisters;
  77. PhysicalRegisters32=OBJECT (PhysicalRegisters) (* 32 bit implementation *)
  78. PROCEDURE & InitPhysicalRegisters32(fpu,cooperative: BOOLEAN);
  79. VAR i: LONGINT;
  80. BEGIN
  81. InitPhysicalRegisters(fpu,cooperative);
  82. (* disable registers that are only usable in 64 bit mode *)
  83. FOR i := 0 TO 31 DO
  84. toVirtual[i+RAX] := unusable;
  85. END;
  86. FOR i := 8 TO 15 DO
  87. toVirtual[i+AL] := unusable;
  88. toVirtual[i+AH] := unusable;
  89. toVirtual[i+EAX] := unusable;
  90. toVirtual[i+AX] := unusable;
  91. END;
  92. FOR i := 4 TO 7 DO
  93. toVirtual[i+AL] := unusable;
  94. toVirtual[i+AH] := unusable;
  95. END;
  96. FOR i := 0 TO LEN(reserved)-1 DO reserved[i] := FALSE END;
  97. END InitPhysicalRegisters32;
  98. PROCEDURE Allocate*(index: LONGINT; virtualRegister: Ticket);
  99. BEGIN
  100. (*
  101. D.String("allocate register x : index="); D.Int(index,1); D.Ln;
  102. *)
  103. Assert(toVirtual[index] = free,"register already allocated");
  104. toVirtual[index] := virtualRegister;
  105. IF index DIV 32 = 2 THEN (* 32 bit *)
  106. Assert(toVirtual[index MOD 32 + AX] = free,"free register split");
  107. toVirtual[index MOD 32 + AX] := blocked;
  108. IF index MOD 32 < 4 THEN
  109. Assert(toVirtual[index MOD 32 + AL] = free,"register already allocated");
  110. Assert(toVirtual[index MOD 32 + AH] = free,"register already allocated");
  111. toVirtual[index MOD 32 + AL] := blocked;
  112. toVirtual[index MOD 32 + AH] := blocked;
  113. END;
  114. ELSIF index DIV 32 = 1 THEN (* 16 bit *)
  115. Assert(toVirtual[index MOD 8 + EAX] = free,"free register split");
  116. toVirtual[index MOD 32 + EAX] := split;
  117. IF index MOD 32 < 4 THEN
  118. Assert(toVirtual[index MOD 32 + AL] = free,"register already allocated");
  119. Assert(toVirtual[index MOD 32 + AH] = free,"register already allocated");
  120. toVirtual[index MOD 32 + AL] := blocked;
  121. toVirtual[index MOD 32 + AH] := blocked;
  122. END;
  123. ELSIF index DIV 32 = 0 THEN (* 8 bit *)
  124. Assert((toVirtual[index MOD 4 + EAX] = free) OR (toVirtual[index MOD 4 + EAX] = split),"free register blocked");
  125. Assert((toVirtual[index MOD 4 + AX] = free) OR (toVirtual[index MOD 4 + AX] = split),"free register blocked");
  126. toVirtual[index MOD 4 + EAX] := split;
  127. toVirtual[index MOD 4 + AX] := split;
  128. ELSIF (index >= XMM0) & (index <= XMM7) THEN (* vector register *)
  129. ELSIF (index >= YMM0) & (index <= YMM7) THEN (* vector register *)
  130. ELSE Assert( (index >=InstructionSet.regST0) & (index <= InstructionSet.regST7 ),"not a float register"); (* floats *)
  131. END;
  132. END Allocate;
  133. PROCEDURE SetReserved*(index: LONGINT; res: BOOLEAN);
  134. BEGIN
  135. IF index DIV 32 <=2 THEN
  136. index := index MOD 16;
  137. reserved[index+AH] := res;
  138. reserved[index+AL] := res;
  139. reserved[index+AX] := res;
  140. reserved[index+EAX] := res;
  141. ELSE
  142. reserved[index] := res;
  143. END;
  144. END SetReserved;
  145. PROCEDURE Reserved*(index: LONGINT): BOOLEAN;
  146. BEGIN
  147. RETURN (index>0) & reserved[index]
  148. END Reserved;
  149. PROCEDURE Free*(index: LONGINT);
  150. VAR x: Ticket;
  151. BEGIN
  152. (*
  153. D.String("free register x : index="); D.Int(index,1); D.Ln;
  154. *)
  155. x := toVirtual[index];
  156. Assert((toVirtual[index] # NIL),"register not reserved");
  157. toVirtual[index] := free;
  158. IF index DIV 32 =2 THEN (* 32 bit *)
  159. Assert(toVirtual[index MOD 32 + AX] = blocked,"reserved register did not block");
  160. toVirtual[index MOD 32 + AX] := free;
  161. IF index MOD 32 < 4 THEN
  162. Assert(toVirtual[index MOD 32 + AL] = blocked,"reserved register did not block");
  163. Assert(toVirtual[index MOD 32 + AH] = blocked,"reserved register did not block");
  164. toVirtual[index MOD 32 + AL] := free;
  165. toVirtual[index MOD 32 + AH] := free;
  166. END;
  167. ELSIF index DIV 32 = 1 THEN (* 16 bit *)
  168. Assert(toVirtual[index MOD 32 + EAX] = split,"reserved register did not split");
  169. toVirtual[index MOD 32 + EAX] := free;
  170. IF index MOD 32 < 4 THEN
  171. Assert(toVirtual[index MOD 32 + AL] = blocked,"reserved register did not block");
  172. Assert(toVirtual[index MOD 32 + AH] = blocked,"reserved register did not block");
  173. toVirtual[index MOD 32 + AL] := free;
  174. toVirtual[index MOD 32 + AH] := free;
  175. END;
  176. ELSIF index DIV 32 = 0 THEN (* 8 bit *)
  177. IF (toVirtual[index MOD 4 + AL] = free) & (toVirtual[index MOD 4 + AH] = free) THEN
  178. Assert(toVirtual[index MOD 4 + EAX] = split,"reserved register did not split");
  179. Assert(toVirtual[index MOD 4 + AX] = split,"reserved register did not split");
  180. toVirtual[index MOD 4 + EAX] := free;
  181. toVirtual[index MOD 4 + AX] := free;
  182. END;
  183. ELSIF (index >= XMM0) & (index <= XMM7) THEN (* vector register *)
  184. ELSIF (index >= YMM0) & (index <= YMM7) THEN (* vector register *)
  185. ELSE Assert( (index >=InstructionSet.regST0) & (index <= InstructionSet.regST7 ),"not a float register"); (* floats *)
  186. END;
  187. END Free;
  188. PROCEDURE NextFree*(CONST type: IntermediateCode.Type):LONGINT;
  189. VAR i,sizeInBits,length, form: LONGINT;
  190. PROCEDURE GetGPHint(offset: LONGINT): LONGINT;
  191. VAR res: LONGINT;
  192. BEGIN
  193. IF (hint # none) & (hint >= AL) & (hint <= EDI) & (toVirtual[hint MOD 32 + offset]=free) & ~Reserved(hint) THEN res := hint MOD 32 + offset ELSE res := none END;
  194. hint := none;
  195. RETURN res
  196. END GetGPHint;
  197. PROCEDURE GetHint(from,to: LONGINT): LONGINT;
  198. VAR res: LONGINT;
  199. BEGIN
  200. IF (hint # none) & (hint >= from) & (hint <= to) & (toVirtual[hint]=free) & ~Reserved(hint) THEN res := hint ELSE res := none END;
  201. hint := none;
  202. RETURN res
  203. END GetHint;
  204. PROCEDURE Get(from,to: LONGINT): LONGINT;
  205. VAR i: LONGINT;
  206. BEGIN
  207. i := from;
  208. IF from <= to THEN
  209. WHILE (i <= to) & ((toVirtual[i]#free) OR Reserved(i)) DO INC(i) END;
  210. IF i > to THEN i := none END;
  211. ELSE
  212. WHILE (i >=to) & ((toVirtual[i]#free) OR Reserved(i)) DO DEC(i) END;
  213. IF i < to THEN i := none END;
  214. END;
  215. RETURN i
  216. END Get;
  217. BEGIN
  218. length := type.length;
  219. sizeInBits := type.sizeInBits;
  220. form := type.form;
  221. IF (type.length > 1) THEN
  222. IF (* (type.form = IntermediateCode.Float) &*) (type.sizeInBits<=32) & (type.length =4) THEN
  223. i := Get(XMM7, XMM0);
  224. ELSIF (* (type.form = IntermediateCode.Float) &*) (type.sizeInBits<=32) & (type.length =8) THEN
  225. i := Get(YMM7, YMM0);
  226. ELSE
  227. HALT(100)
  228. END
  229. ELSIF type.form IN IntermediateCode.Integer THEN
  230. sizeInBits := type.sizeInBits;
  231. IF type.sizeInBits = IntermediateCode.Bits8 THEN
  232. i := GetGPHint(AL);
  233. IF i = none THEN i := Get(BL, AL) END;
  234. IF i = none THEN i := Get(BH, AH) END;
  235. ELSIF type.sizeInBits = IntermediateCode.Bits16 THEN
  236. i := GetGPHint(AX);
  237. IF i = none THEN i := Get(DI, SI) END;
  238. IF i = none THEN i := Get(BX, AX) END;
  239. ELSIF type.sizeInBits = IntermediateCode.Bits32 THEN
  240. i := GetGPHint(EAX);
  241. IF i = none THEN i := Get(EDI,ESI) END;
  242. IF i = none THEN i := Get(EBX,EAX) END;
  243. ELSE HALT(100)
  244. END;
  245. ELSE
  246. ASSERT(type.form = IntermediateCode.Float);
  247. IF useFPU THEN
  248. i := Get(InstructionSet.regST0, InstructionSet.regST6);
  249. (* ST7 unusable as it is overwritten during arithmetic instructions *)
  250. ELSE
  251. i := GetHint(XMM0, XMM7);
  252. IF i = none THEN i := Get(XMM7, XMM0) END
  253. END;
  254. END;
  255. hint := none; (* reset *)
  256. RETURN i
  257. END NextFree;
  258. PROCEDURE Mapped*(physical: LONGINT): Ticket;
  259. VAR virtual: Ticket;
  260. BEGIN
  261. virtual := toVirtual[physical];
  262. IF virtual = blocked THEN virtual := Mapped(physical+32)
  263. ELSIF virtual = split THEN
  264. IF physical < 32 THEN virtual := Mapped(physical+16 MOD 32)
  265. ELSE virtual := Mapped(physical-32)
  266. END;
  267. END;
  268. ASSERT((virtual = free) OR (virtual = unusable) OR (toVirtual[virtual.register] = virtual));
  269. RETURN virtual
  270. END Mapped;
  271. PROCEDURE Dump*(w: Streams.Writer);
  272. VAR i: LONGINT; virtual: Ticket;
  273. BEGIN
  274. w.String("; ---- registers ----"); w.Ln;
  275. FOR i := 0 TO LEN(toVirtual)-1 DO
  276. virtual := toVirtual[i];
  277. IF virtual # unusable THEN
  278. w.String("reg "); w.Int(i,1); w.String(": ");
  279. IF virtual = free THEN w.String("free")
  280. ELSIF virtual = blocked THEN w.String("blocked")
  281. ELSIF virtual = split THEN w.String("split")
  282. ELSE w.String(" r"); w.Int(virtual.register,1);
  283. END;
  284. IF reserved[i] THEN w.String("reserved") END;
  285. w.Ln;
  286. END;
  287. END;
  288. END Dump;
  289. END PhysicalRegisters32;
  290. PhysicalRegisters64=OBJECT (PhysicalRegisters) (* 64 bit implementation *)
  291. PROCEDURE & InitPhysicalRegisters64(fpu,cooperative: BOOLEAN);
  292. BEGIN
  293. InitPhysicalRegisters(fpu,cooperative);
  294. END InitPhysicalRegisters64;
  295. PROCEDURE SetReserved*(index: LONGINT; res: BOOLEAN);
  296. BEGIN
  297. (*
  298. IF res THEN D.String("reserve ") ELSE D.String("unreserve ") END;
  299. D.String("register: index="); D.Int(index,1); D.Ln;
  300. *)
  301. IF index DIV 32 <=2 THEN
  302. index := index MOD 16;
  303. reserved[index+AH] := res;
  304. reserved[index+AL] := res;
  305. reserved[index+AX] := res;
  306. reserved[index+EAX] := res;
  307. reserved[index+RAX] := res;
  308. ELSE
  309. reserved[index] := res
  310. END;
  311. END SetReserved;
  312. PROCEDURE Reserved*(index: LONGINT): BOOLEAN;
  313. BEGIN
  314. RETURN reserved[index]
  315. END Reserved;
  316. PROCEDURE Allocate*(index: LONGINT; virtualRegister: Ticket);
  317. BEGIN
  318. (*
  319. D.String("allocate register x : index="); D.Int(index,1); D.Ln;
  320. *)
  321. Assert(toVirtual[index] = free,"register already allocated");
  322. toVirtual[index] := virtualRegister;
  323. IF index DIV 32 = 3 THEN (* 64 bit *)
  324. Assert(toVirtual[index MOD 32 + EAX] = free,"free register split");
  325. toVirtual[index MOD 32 + EAX] := blocked;
  326. toVirtual[index MOD 32 + AX] := blocked;
  327. toVirtual[index MOD 32 + AL] := blocked;
  328. ELSIF index DIV 32 = 2 THEN (* 32 bit *)
  329. Assert(toVirtual[index MOD 32 + AX] = free,"free register split");
  330. toVirtual[index MOD 32 + RAX] := split;
  331. toVirtual[index MOD 32 + AX] := blocked;
  332. toVirtual[index MOD 32 + AL] := blocked;
  333. ELSIF index DIV 32 = 1 THEN (* 16 bit *)
  334. toVirtual[index MOD 32 + RAX] := split;
  335. toVirtual[index MOD 32 + EAX] := split;
  336. toVirtual[index MOD 32 + AL] := blocked;
  337. ELSIF index DIV 32 = 0 THEN (* 8 bit *)
  338. toVirtual[index MOD 32 + RAX] := split;
  339. toVirtual[index MOD 32 + EAX] := split;
  340. toVirtual[index MOD 32 + AX] := split;
  341. ELSIF (index >= XMM0) & (index <= XMM7) THEN (* vector register *)
  342. ELSIF (index >= YMM0) & (index <= YMM7) THEN (* vector register *)
  343. ELSE Assert( (index >=InstructionSet.regST0) & (index <= InstructionSet.regST7 ),"not a float register"); (* floats *)
  344. END;
  345. END Allocate;
  346. PROCEDURE Free*(index: LONGINT);
  347. BEGIN
  348. (*
  349. D.String("release register x : index="); D.Int(index,1); D.Ln;
  350. *)
  351. Assert(toVirtual[index]#NIL,"register not reserved");
  352. toVirtual[index] := free;
  353. IF index DIV 32 =3 THEN (* 64 bit *)
  354. Assert(toVirtual[index MOD 32 + EAX] = blocked,"reserved register did not block");
  355. toVirtual[index MOD 32 + EAX] := free;
  356. toVirtual[index MOD 32 + AX] := free;
  357. toVirtual[index MOD 32 + AL] := free;
  358. ELSIF index DIV 32 =2 THEN (* 32 bit *)
  359. Assert(toVirtual[index MOD 32 + RAX] = split,"reserved register did not split");
  360. Assert(toVirtual[index MOD 32 + AX] = blocked,"reserved register did not block");
  361. Assert(toVirtual[index MOD 32 + AL] = blocked,"reserved register did not block");
  362. toVirtual[index MOD 32 + RAX] := free;
  363. toVirtual[index MOD 32 + AX] := free;
  364. toVirtual[index MOD 32 + AL] := free;
  365. ELSIF index DIV 32 = 1 THEN (* 16 bit *)
  366. Assert(toVirtual[index MOD 32 + RAX] = split,"reserved register did not split");
  367. Assert(toVirtual[index MOD 32 + EAX] = split,"reserved register did not split");
  368. Assert(toVirtual[index MOD 32 + AL] = blocked,"reserved register did not split");
  369. toVirtual[index MOD 32 + RAX] := free;
  370. toVirtual[index MOD 32 + EAX] := free;
  371. toVirtual[index MOD 32 + AL] := free;
  372. ELSIF index DIV 32 = 0 THEN (* 8 bit *)
  373. Assert(toVirtual[index MOD 32 + RAX] = split,"reserved register did not split");
  374. Assert(toVirtual[index MOD 32 + EAX] = split,"reserved register did not split");
  375. Assert(toVirtual[index MOD 32 + AX] = split,"reserved register did not split");
  376. toVirtual[index MOD 32 + RAX] := free;
  377. toVirtual[index MOD 32 + EAX] := free;
  378. toVirtual[index MOD 32 + AX] := free;
  379. ELSIF (index >= XMM0) & (index <= XMM7) THEN (* vector register *)
  380. ELSIF (index >= YMM0) & (index <= YMM7) THEN (* vector register *)
  381. ELSE Assert( (index >=InstructionSet.regST0) & (index <= InstructionSet.regST7 ),"not a float register"); (* floats *)
  382. END;
  383. END Free;
  384. PROCEDURE NextFree*(CONST type: IntermediateCode.Type): LONGINT;
  385. VAR i: LONGINT;
  386. PROCEDURE GetGPHint(offset: LONGINT): LONGINT;
  387. VAR res: LONGINT;
  388. BEGIN
  389. IF (hint # none) & (hint >= AL) & (hint <= R15) & (toVirtual[hint MOD 32 + offset]=free) & ~Reserved(hint) THEN res := hint MOD 32 + offset ELSE res := none END;
  390. hint := none;
  391. RETURN res
  392. END GetGPHint;
  393. PROCEDURE Get(from,to: LONGINT): LONGINT;
  394. VAR i: LONGINT;
  395. BEGIN
  396. i := from;
  397. IF from <= to THEN
  398. WHILE (i <= to) & ((toVirtual[i]#free) OR Reserved(i)) DO INC(i) END;
  399. IF i > to THEN i := none END;
  400. ELSE
  401. WHILE (i >=to) & ((toVirtual[i]#free) OR Reserved(i)) DO DEC(i) END;
  402. IF i < to THEN i := none END;
  403. END;
  404. RETURN i
  405. END Get;
  406. BEGIN
  407. IF type.form IN IntermediateCode.Integer THEN
  408. IF type.sizeInBits = IntermediateCode.Bits8 THEN
  409. i := GetGPHint(AL);
  410. IF i = none THEN i := Get(BL, AL) END;
  411. IF i = none THEN i := Get(BH, AH) END;
  412. IF i = none THEN
  413. i := Get(AL,R15B)
  414. END;
  415. ELSIF type.sizeInBits = IntermediateCode.Bits16 THEN
  416. i := GetGPHint(AX);
  417. IF i = none THEN i := Get(DI, SI) END;
  418. IF i = none THEN i := Get(BX, AX) END;
  419. IF i = none THEN
  420. i := Get(AX,R15W);
  421. END;
  422. ELSIF type.sizeInBits = IntermediateCode.Bits32 THEN
  423. i := GetGPHint(EAX);
  424. IF i = none THEN i := Get(EDI,ESI) END;
  425. IF i = none THEN i := Get(EBX,EAX) END;
  426. IF i = none THEN
  427. i := Get(EAX,R15D);
  428. END;
  429. ELSIF type.sizeInBits = IntermediateCode.Bits64 THEN
  430. i := GetGPHint(RAX);
  431. IF i = none THEN i := Get(RDI,RSI) END;
  432. IF i = none THEN i := Get(RBX,RAX) END;
  433. IF i = none THEN
  434. i := Get(RAX, R15)
  435. END;
  436. ELSE HALT(100)
  437. END;
  438. ELSE
  439. ASSERT(type.form = IntermediateCode.Float);
  440. IF useFPU THEN
  441. i := Get(InstructionSet.regST0, InstructionSet.regST6);
  442. (* ST7 unusable as it is overwritten during arithmetic instructions *)
  443. ELSE
  444. i := Get(XMM7, XMM0)
  445. END;
  446. END;
  447. RETURN i;
  448. END NextFree;
  449. PROCEDURE Mapped*(physical: LONGINT): Ticket;
  450. VAR virtual: Ticket;
  451. BEGIN
  452. virtual := toVirtual[physical];
  453. IF virtual = blocked THEN RETURN Mapped(physical+32) END;
  454. IF virtual = split THEN RETURN Mapped(physical-32) END;
  455. RETURN virtual
  456. END Mapped;
  457. END PhysicalRegisters64;
  458. CodeGeneratorAMD64 = OBJECT (CodeGenerators.GeneratorWithTickets)
  459. VAR
  460. (* static generator state variables, considered constant during generation *)
  461. runtimeModuleName: SyntaxTree.IdentifierString;
  462. cpuBits: LONGINT;
  463. opBP, opSP, opRA, opRB, opRC, opRD, opRSI, opRDI, opR8, opR9, opR10, opR11, opR12, opR13, opR14, opR15: Assembler.Operand; (* base pointer, stack pointer, register A, depends on cpuBits*)
  464. BP, SP, RA, RD, RS, RC: LONGINT; (* base pointer and stack pointer register index, depends on cpuBits *)
  465. emitter: Assembler.Emitter; (* assembler generating and containing the machine code *)
  466. backend: BackendAMD64;
  467. (* register spill state *)
  468. stackSize: LONGINT;
  469. spillStackStart: LONGINT;
  470. (* floating point stack state *)
  471. fpStackPointer: LONGINT; (* floating point stack pointer, increases with allocation, decreases with releasing, used to determine current relative position on stack (as is necessary for intel FP instructions) *)
  472. (*
  473. FP register usage scheme:
  474. sp=1> FP0 - temp
  475. sp=0> FP0 - reg0 FP1 - reg0 sp=0> FP0 - reg0
  476. FP1 - reg1 FP2 - reg1 FP1 - reg1
  477. FP2 - reg2 FP3 - reg2 FP2 - reg2
  478. FP3 - reg3 = load op1 => FP4 - reg3 = op => FP3 - reg3
  479. FP4 - reg4 FP5 - reg4 FP4 - reg4
  480. FP5 - reg5 FP6 - reg5 FP5 - reg5
  481. FP6 - reg6 FP7 - reg6 FP6 - reg6
  482. FP7 - reg7 (reg7 lost) FP7 - reg7
  483. *)
  484. ap: Ticket;
  485. (* -------------------------- constructor -------------------------------*)
  486. PROCEDURE &InitGeneratorAMD64(CONST runtime: SyntaxTree.IdentifierString; diagnostics: Diagnostics.Diagnostics; backend: BackendAMD64);
  487. VAR physicalRegisters: PhysicalRegisters; physicalRegisters32: PhysicalRegisters32; physicalRegisters64: PhysicalRegisters64;
  488. BEGIN
  489. SELF.backend := backend;
  490. runtimeModuleName := runtime;
  491. SELF.cpuBits := backend.bits;
  492. NEW(emitter,diagnostics);
  493. IF cpuBits=32 THEN
  494. NEW(physicalRegisters32, backend.forceFPU, backend.cooperative); physicalRegisters := physicalRegisters32; error := ~emitter.SetBits(32);
  495. opBP := opEBP; opSP := opESP; opRA := opEAX; opRB := opEBX; opRD := opEDX; opRDI := opEDI; opRSI := opESI; opRC := opECX;
  496. SP := ESP; BP := EBP; RA := EAX;
  497. RD := EDI; RS := ESI; RC := ECX;
  498. ASSERT(~error);
  499. ELSIF cpuBits=64 THEN
  500. NEW(physicalRegisters64, backend.forceFPU, backend.cooperative); physicalRegisters := physicalRegisters64; error := ~emitter.SetBits(64);
  501. opBP := opRBP; opSP := opRSP;
  502. opRA := registerOperands[RAX]; opRC := registerOperands[RCX];
  503. opRB := registerOperands[RBX]; opRD := registerOperands[RDX];
  504. opRDI := registerOperands[RDI]; opRSI := registerOperands[RSI];
  505. opR8 := registerOperands[R8]; opR9 := registerOperands[R9];
  506. opR10 := registerOperands[R10]; opR11 := registerOperands[R11];
  507. opR12 := registerOperands[R12]; opR13 := registerOperands[R13];
  508. opR14 := registerOperands[R14]; opR15 := registerOperands[R15];
  509. SP := RSP; BP := RBP; RA := RAX;
  510. RD := RDI; RS := RSI; RC := RCX;
  511. ASSERT(~error);
  512. ELSE Halt("no register allocator for bits other than 32 / 64 ");
  513. END;
  514. fpStackPointer := 0;
  515. InitTicketGenerator(diagnostics,backend.optimize,2,physicalRegisters);
  516. END InitGeneratorAMD64;
  517. (*------------------- overwritten methods ----------------------*)
  518. PROCEDURE Section*(in: IntermediateCode.Section; out: BinaryCode.Section);
  519. VAR oldSpillStackSize: LONGINT;
  520. PROCEDURE CheckEmptySpillStack;
  521. BEGIN
  522. IF spillStack.Size()#0 THEN Error(Basic.invalidPosition,"implementation error, spill stack not cleared") END;
  523. END CheckEmptySpillStack;
  524. BEGIN
  525. spillStack.Init;
  526. IF backend.cooperative THEN
  527. ap := ReservePhysicalRegister(IntermediateCode.GeneralPurposeRegister,IntermediateCode.UnsignedIntegerType(cpuBits),RC,in.pc);
  528. ap.spillable := FALSE;
  529. END;
  530. emitter.SetCode(out);
  531. Section^(in,out);
  532. IF FrameSpillStack & (spillStack.MaxSize() >0) THEN
  533. oldSpillStackSize := spillStack.MaxSize();
  534. out.Reset;
  535. CheckEmptySpillStack;
  536. Section^(in,out);
  537. ASSERT(spillStack.MaxSize() = oldSpillStackSize);
  538. END;
  539. ASSERT(fpStackPointer = 0);
  540. CheckEmptySpillStack;
  541. IF backend.cooperative THEN
  542. UnmapTicket(ap);
  543. END;
  544. error := error OR emitter.error;
  545. END Section;
  546. PROCEDURE Supported*(CONST instruction: IntermediateCode.Instruction; VAR moduleName, procedureName: ARRAY OF CHAR): BOOLEAN;
  547. BEGIN
  548. COPY(runtimeModuleName, moduleName);
  549. IF (cpuBits=32) & (instruction.op2.type.sizeInBits = IntermediateCode.Bits64) & (instruction.op2.type.form IN IntermediateCode.Integer) THEN
  550. CASE instruction.opcode OF
  551. IntermediateCode.div:
  552. procedureName := "DivH"; RETURN FALSE
  553. | IntermediateCode.mul:
  554. procedureName := "MulH"; RETURN FALSE
  555. | IntermediateCode.mod :
  556. procedureName := "ModH"; RETURN FALSE
  557. | IntermediateCode.abs :
  558. procedureName := "AbsH"; RETURN FALSE;
  559. | IntermediateCode.shl :
  560. IF instruction.op1.type.form = IntermediateCode.SignedInteger THEN
  561. procedureName := "AslH"; RETURN FALSE;
  562. ELSE
  563. procedureName := "LslH"; RETURN FALSE;
  564. END;
  565. | IntermediateCode.shr :
  566. IF instruction.op1.type.form = IntermediateCode.SignedInteger THEN
  567. procedureName := "AsrH"; RETURN FALSE;
  568. ELSE
  569. procedureName := "LsrH"; RETURN FALSE;
  570. END;
  571. | IntermediateCode.ror :
  572. procedureName := "RorH"; RETURN FALSE;
  573. | IntermediateCode.rol :
  574. procedureName := "RolH"; RETURN FALSE;
  575. | IntermediateCode.cas :
  576. procedureName := "CasH"; RETURN FALSE;
  577. ELSE RETURN TRUE
  578. END;
  579. ELSIF ~backend.forceFPU & (instruction.opcode = IntermediateCode.conv) & (instruction.op1.type.form IN IntermediateCode.Integer) & (instruction.op2.type.form = IntermediateCode.Float) & IsComplex(instruction.op1) THEN
  580. IF instruction.op2.type.sizeInBits=32 THEN
  581. procedureName := "EntierRH"
  582. ELSE
  583. procedureName := "EntierXH"
  584. END;
  585. RETURN FALSE
  586. END;
  587. RETURN TRUE
  588. END Supported;
  589. (* input: type (such as that of an intermediate operand), output: low and high type (such as in low and high type of an operand) *)
  590. PROCEDURE GetPartType*(CONST type: IntermediateCode.Type; part: LONGINT; VAR typePart: IntermediateCode.Type);
  591. BEGIN
  592. ASSERT(type.sizeInBits >0);
  593. IF (type.sizeInBits > cpuBits) & (type.form IN IntermediateCode.Integer) THEN
  594. IntermediateCode.InitType(typePart,type.form,32);
  595. ELSE ASSERT((type.form IN IntermediateCode.Integer) OR (type.form = IntermediateCode.Float));
  596. IF part=Low THEN typePart := type ELSE typePart := IntermediateCode.undef END;
  597. END;
  598. END GetPartType;
  599. (* simple move without conversion *)
  600. PROCEDURE Move(VAR dest, src: Assembler.Operand; CONST type: IntermediateCode.Type);
  601. BEGIN
  602. IF type.length > 1 THEN
  603. IF type.length = 4 THEN
  604. (*ASSERT(type.form = IntermediateCode.Float);*)
  605. IF (*(type.form = IntermediateCode.Float) & *) (type.sizeInBits = 32) THEN
  606. SpecialMove(InstructionSet.opMOVUPS, InstructionSet.opMOVUPS, TRUE, dest, src, type);
  607. ELSIF (type.sizeInBits = 16) THEN
  608. SpecialMove(InstructionSet.opMOVQ, InstructionSet.opMOVQ, TRUE, dest, src, type);
  609. ELSIF (type.sizeInBits = 8) THEN
  610. SpecialMove(InstructionSet.opMOVD, InstructionSet.opMOVD, TRUE, dest, src, type);
  611. END;
  612. ELSIF type.length = 8 THEN
  613. (*ASSERT(type.form = IntermediateCode.Float);*)
  614. IF (*(type.form = IntermediateCode.Float) & *) (type.sizeInBits = 32) THEN
  615. SpecialMove(InstructionSet.opVMOVUPS, InstructionSet.opVMOVUPS, TRUE, dest, src, type);
  616. ELSIF (type.sizeInBits = 16) THEN
  617. SpecialMove(InstructionSet.opVMOVQ, InstructionSet.opVMOVQ, TRUE, dest, src, type);
  618. ELSIF (type.sizeInBits = 8) THEN
  619. SpecialMove(InstructionSet.opVMOVD, InstructionSet.opVMOVD, TRUE, dest, src, type);
  620. END;
  621. ELSE
  622. (*
  623. ASSERT(type.form = IntermediateCode.Float);
  624. *)
  625. ASSERT(type.sizeInBits = 64);
  626. SpecialMove(InstructionSet.opMOVUPD, InstructionSet.opMOVUPS, TRUE, dest, src, type);
  627. END;
  628. ELSIF type.form = IntermediateCode.Float THEN
  629. IF type.sizeInBits = 32 THEN
  630. SpecialMove(InstructionSet.opMOVSS, InstructionSet.opMOVSS, TRUE, dest, src, type);
  631. ELSE
  632. SpecialMove(InstructionSet.opMOVSD, InstructionSet.opMOVSD, TRUE, dest, src, type);
  633. END;
  634. ELSE
  635. SpecialMove(InstructionSet.opMOV, InstructionSet.opMOV, TRUE, dest, src, type);
  636. END;
  637. END Move;
  638. PROCEDURE ToSpillStack*(ticket: Ticket);
  639. VAR op: Assembler.Operand;
  640. BEGIN
  641. IF (ticket.type.form = IntermediateCode.Float) & backend.forceFPU THEN
  642. emitter.Emit1(InstructionSet.opFLD,registerOperands[ticket.register]);
  643. INC(fpStackPointer);
  644. GetSpillOperand(ticket,op);
  645. emitter.Emit1(InstructionSet.opFSTP,op);
  646. DEC(fpStackPointer);
  647. ELSE
  648. GetSpillOperand(ticket,op);
  649. Move(op, registerOperands[ticket.register], ticket.type)
  650. END;
  651. END ToSpillStack;
  652. PROCEDURE AllocateSpillStack*(size: LONGINT);
  653. BEGIN
  654. IF ~FrameSpillStack THEN
  655. AllocateStack(cpuBits DIV 8*size)
  656. END;
  657. END AllocateSpillStack;
  658. PROCEDURE ToRegister*(ticket: Ticket);
  659. VAR op: Assembler.Operand;
  660. BEGIN
  661. GetSpillOperand(ticket,op);
  662. emitter.Emit2(InstructionSet.opMOV,registerOperands[ticket.register],op);
  663. END ToRegister;
  664. PROCEDURE ExchangeTickets*(ticket1,ticket2: Ticket);
  665. VAR op1,op2: Assembler.Operand;
  666. BEGIN
  667. TicketToOperand(ticket1, op1);
  668. TicketToOperand(ticket2, op2);
  669. emitter.Emit2(InstructionSet.opXCHG, op1,op2);
  670. END ExchangeTickets;
  671. (*------------------- particular register mappings / operands ----------------------*)
  672. (* returns if a virtual register is mapped to the register set described by virtualRegisterMapping*)
  673. PROCEDURE MappedTo(CONST virtualRegister: LONGINT; part:LONGINT; physicalRegister: LONGINT): BOOLEAN;
  674. VAR ticket: Ticket;
  675. BEGIN
  676. IF (virtualRegister > 0) THEN
  677. ticket := virtualRegisters.Mapped(virtualRegister,part);
  678. RETURN (ticket # NIL) & ~(ticket.spilled) & (ticket.register = physicalRegister)
  679. ELSIF (virtualRegister = IntermediateCode.FP) THEN
  680. RETURN physicalRegister= BP
  681. ELSIF (virtualRegister = IntermediateCode.SP) THEN
  682. RETURN physicalRegister = SP
  683. ELSIF (virtualRegister = IntermediateCode.AP) THEN
  684. ASSERT(backend.cooperative);
  685. RETURN ~(ap.spilled) & (ap.register = physicalRegister)
  686. ELSE
  687. RETURN FALSE
  688. END;
  689. END MappedTo;
  690. PROCEDURE ResultRegister(CONST type: IntermediateCode.Type; part: LONGINT): LONGINT;
  691. BEGIN
  692. IF type.form IN IntermediateCode.Integer THEN
  693. CASE type.sizeInBits OF
  694. | 64:
  695. IF cpuBits = 32 THEN
  696. IF part = Low THEN RETURN EAX
  697. ELSE RETURN EDX
  698. END;
  699. ELSE
  700. ASSERT(part = Low);
  701. RETURN RAX
  702. END;
  703. | 32: ASSERT(part=Low); RETURN EAX
  704. | 16: ASSERT(part=Low); RETURN AX
  705. | 8: ASSERT(part=Low); RETURN AL
  706. END;
  707. ELSIF ~backend.forceFPU THEN
  708. RETURN XMM0
  709. ELSE ASSERT(type.form = IntermediateCode.Float);ASSERT(part=Low);
  710. RETURN ST0
  711. END;
  712. END ResultRegister;
  713. (*------------------- operand reflection ----------------------*)
  714. PROCEDURE IsMemoryOperand(vop: IntermediateCode.Operand; part: LONGINT): BOOLEAN;
  715. VAR ticket: Ticket;
  716. BEGIN
  717. IF vop.mode = IntermediateCode.ModeMemory THEN RETURN TRUE
  718. ELSIF vop.mode = IntermediateCode.ModeRegister THEN
  719. ticket := virtualRegisters.Mapped(vop.register,part);
  720. RETURN (ticket # NIL) & (ticket.spilled);
  721. ELSE RETURN FALSE
  722. END;
  723. END IsMemoryOperand;
  724. PROCEDURE IsRegister(CONST vop: IntermediateCode.Operand): BOOLEAN;
  725. BEGIN
  726. RETURN (vop.mode = IntermediateCode.ModeRegister) & (vop.offset = 0)
  727. END IsRegister;
  728. (* infer intermediate code type from physical operand as far as possible *)
  729. PROCEDURE PhysicalOperandType(CONST op:Assembler.Operand): IntermediateCode.Type;
  730. VAR type:IntermediateCode.Type;
  731. BEGIN
  732. IF op.type = Assembler.sti THEN
  733. IntermediateCode.InitType(type, IntermediateCode.Float, op.sizeInBytes*8)
  734. ELSE
  735. IntermediateCode.InitType(type, IntermediateCode.SignedInteger, op.sizeInBytes*8)
  736. END;
  737. RETURN type
  738. END PhysicalOperandType;
  739. (*------------------- operand generation ----------------------*)
  740. PROCEDURE GetSpillOperand(ticket: Ticket; VAR op: Assembler.Operand);
  741. BEGIN
  742. IF FrameSpillStack THEN
  743. op := Assembler.NewMem(SHORTINT(ticket.type.sizeInBits*ticket.type.length DIV 8), BP , -(spillStackStart + cpuBits DIV 8 + ticket.offset*cpuBits DIV 8));
  744. ELSE
  745. op := Assembler.NewMem(SHORTINT(ticket.type.sizeInBits*ticket.type.length DIV 8),SP , (spillStack.Size()-ticket.offset)*cpuBits DIV 8);
  746. END;
  747. END GetSpillOperand;
  748. PROCEDURE TicketToOperand(ticket: Ticket; VAR op: Assembler.Operand);
  749. BEGIN
  750. IF (ticket = NIL) THEN
  751. Assembler.InitOperand(op)
  752. ELSIF ticket.spilled THEN
  753. GetSpillOperand(ticket,op)
  754. ELSE
  755. IF ticket.register = none THEN physicalRegisters.Dump(D.Log); tickets.Dump(D.Log); virtualRegisters.Dump(D.Log); D.Update; END;
  756. ASSERT(ticket.register # none);
  757. IF (ticket.type.form = IntermediateCode.Float) & backend.forceFPU THEN
  758. op := registerOperands[ticket.register+fpStackPointer]
  759. ELSE
  760. op := registerOperands[ticket.register];
  761. END;
  762. END;
  763. END TicketToOperand;
  764. PROCEDURE GetTemporaryRegister(type: IntermediateCode.Type; VAR op: Assembler.Operand);
  765. BEGIN
  766. TicketToOperand(TemporaryTicket(IntermediateCode.GeneralPurposeRegister,type),op)
  767. END GetTemporaryRegister;
  768. PROCEDURE GetImmediateMem(CONST vop: IntermediateCode.Operand; part: LONGINT; VAR imm: Assembler.Operand);
  769. VAR data: IntermediateCode.Section;pc: LONGINT; source, dest: Assembler.Operand; ticket: Ticket;
  770. BEGIN
  771. data := GetDataSection();
  772. pc := IntermediateBackend.EnterImmediate(data,vop);
  773. IF cpuBits = 64 THEN
  774. Assembler.InitImm(source,8,0);
  775. Assembler.SetSymbol(source,data.name,0,pc,0);
  776. ticket := TemporaryTicket(IntermediateCode.GeneralPurposeRegister,IntermediateBackend.GetType(module.system,module.system.addressType));
  777. TicketToOperand(ticket,dest);
  778. emitter.Emit2(InstructionSet.opMOV,dest,source);
  779. Assembler.InitMem(imm, SHORT(vop.type.sizeInBits DIV 8), ticket.register, 0);
  780. ELSE
  781. Assembler.InitMem(imm, SHORT(vop.type.sizeInBits DIV 8) , Assembler.none,0);
  782. Assembler.SetSymbol(imm,data.name,0,pc,0);
  783. END;
  784. END GetImmediateMem;
  785. PROCEDURE GetImmediate(CONST virtual: IntermediateCode.Operand; part: LONGINT; VAR physical: Assembler.Operand; forbidden16Bit: BOOLEAN);
  786. VAR type: IntermediateCode.Type; temp: Assembler.Operand; size: SHORTINT; value: HUGEINT;
  787. PROCEDURE IsImm8(value: HUGEINT): BOOLEAN;
  788. BEGIN
  789. RETURN (value >= -80H) & (value < 80H)
  790. END IsImm8;
  791. PROCEDURE IsImm16(value: HUGEINT): BOOLEAN;
  792. BEGIN
  793. RETURN (value >= -8000H) & (value < 10000H)
  794. END IsImm16;
  795. PROCEDURE IsImm32(value: HUGEINT): BOOLEAN;
  796. BEGIN
  797. value := value DIV 10000H DIV 10000H;
  798. RETURN (value = 0) OR (value=-1);
  799. END IsImm32;
  800. BEGIN
  801. ASSERT(virtual.mode = IntermediateCode.ModeImmediate);
  802. GetPartType(virtual.type,part,type);
  803. IF virtual.type.form IN IntermediateCode.Integer THEN
  804. IF IsComplex(virtual) THEN
  805. IF part = High THEN value := SHORT(virtual.intValue DIV 10000H DIV 10000H)
  806. ELSE value := virtual.intValue
  807. END;
  808. ELSE value := virtual.intValue
  809. END;
  810. IF virtual.symbol.name # "" THEN size := SHORT(type.sizeInBits DIV 8);
  811. ELSIF forbidden16Bit & IsImm16(value) & ~(IsImm8(value)) THEN size := Assembler.bits32;
  812. ELSIF (type.sizeInBits = 64) & (type.form = IntermediateCode.UnsignedInteger) & (value > MAX(LONGINT)) THEN
  813. size := 8; (* don't use negative signed 32-bit value to encode 64-bit unsigned value! *)
  814. ELSE size := 0
  815. END;
  816. Assembler.InitImm(physical,size ,value);
  817. IF virtual.symbol.name # "" THEN Assembler.SetSymbol(physical,virtual.symbol.name,virtual.symbol.fingerprint,virtual.symbolOffset,virtual.offset+part*Assembler.bits32) END;
  818. IF (cpuBits=64) & ((physical.sizeInBytes=8) OR ~IsImm32(value)) THEN
  819. ASSERT(cpuBits=64);
  820. GetTemporaryRegister(IntermediateCode.int64,temp);
  821. emitter.Emit2(InstructionSet.opMOV,temp,physical);
  822. physical := temp;
  823. END;
  824. ELSE
  825. GetImmediateMem(virtual,part,physical);
  826. END;
  827. END GetImmediate;
  828. PROCEDURE GetMemory(CONST virtual: IntermediateCode.Operand; part: LONGINT; VAR physical: Assembler.Operand);
  829. VAR type: IntermediateCode.Type; virtualRegister, physicalRegister,offset: LONGINT; ticket,orig: Ticket; dest, source: Assembler.Operand;
  830. BEGIN
  831. ASSERT(virtual.mode = IntermediateCode.ModeMemory);
  832. GetPartType(virtual.type,part,type);
  833. IF virtual.register # IntermediateCode.None THEN
  834. virtualRegister := virtual.register;
  835. IF virtualRegister = IntermediateCode.FP THEN physicalRegister := BP;
  836. ELSIF virtualRegister = IntermediateCode.SP THEN physicalRegister := SP;
  837. ELSE
  838. IF virtualRegister = IntermediateCode.AP THEN
  839. ticket := ap;
  840. ELSE
  841. ticket := virtualRegisters.Mapped(virtualRegister,Low);
  842. END;
  843. IF ticket.spilled THEN
  844. IF physicalRegisters.Reserved(ticket.register) THEN
  845. orig := ticket;
  846. ticket := TemporaryTicket(IntermediateCode.GeneralPurposeRegister,IntermediateBackend.GetType(module.system,module.system.addressType));
  847. TicketToOperand(orig,source);
  848. TicketToOperand(ticket,dest);
  849. Move(dest,source,PhysicalOperandType(dest));
  850. physicalRegister := ticket.register;
  851. ELSE
  852. UnSpill(ticket);
  853. physicalRegister := ticket.register;
  854. END;
  855. ELSE
  856. physicalRegister := ticket.register;
  857. END;
  858. END;
  859. offset := virtual.offset;
  860. ASSERT(virtual.intValue = 0);
  861. ELSIF virtual.symbol.name = "" THEN
  862. physicalRegister := Assembler.none;
  863. offset := SHORT(virtual.intValue);
  864. ASSERT(virtual.offset = 0);
  865. ELSIF cpuBits = 64 THEN
  866. Assembler.InitImm(source,8,0);
  867. Assembler.SetSymbol(source,virtual.symbol.name,virtual.symbol.fingerprint,virtual.symbolOffset,virtual.offset);
  868. ticket := TemporaryTicket(IntermediateCode.GeneralPurposeRegister,IntermediateBackend.GetType(module.system,module.system.addressType));
  869. TicketToOperand(ticket,dest);
  870. emitter.Emit2(InstructionSet.opMOV,dest,source);
  871. physicalRegister := ticket.register;
  872. offset := 0;
  873. ASSERT(virtual.intValue = 0);
  874. ELSE
  875. physicalRegister := Assembler.none;
  876. offset := virtual.offset;
  877. ASSERT(virtual.intValue = 0);
  878. END;
  879. Assembler.InitMem(physical, SHORTINT(type.length * type.sizeInBits DIV 8) , physicalRegister, offset+4*part);
  880. IF (virtual.symbol.name # "") & (cpuBits # 64) THEN
  881. Assembler.SetSymbol(physical,virtual.symbol.name,virtual.symbol.fingerprint,virtual.symbolOffset,virtual.offset+4*part);
  882. END;
  883. END GetMemory;
  884. PROCEDURE GetRegister(CONST virtual: IntermediateCode.Operand; part:LONGINT; VAR physical: Assembler.Operand; VAR ticket: Ticket);
  885. VAR type: IntermediateCode.Type; virtualRegister, tempReg: LONGINT;
  886. tmp,imm: Assembler.Operand; index: LONGINT;
  887. BEGIN
  888. ASSERT(virtual.mode = IntermediateCode.ModeRegister);
  889. GetPartType(virtual.type,part,type);
  890. virtualRegister := virtual.register;
  891. IF (virtual.register > 0) THEN
  892. TicketToOperand(virtualRegisters.Mapped(virtual.register,part), physical);
  893. ELSIF virtual.register = IntermediateCode.FP THEN
  894. Assert(part=Low,"forbidden partitioned register on BP");
  895. physical := opBP;
  896. ELSIF virtual.register = IntermediateCode.SP THEN
  897. Assert(part=Low,"forbidden partitioned register on SP");
  898. physical := opSP;
  899. ELSIF virtual.register = IntermediateCode.AP THEN
  900. ASSERT(backend.cooperative);
  901. Assert(part=Low,"forbidden partitioned register on AP");
  902. TicketToOperand(ap, physical);
  903. ELSE HALT(100);
  904. END;
  905. IF virtual.offset # 0 THEN
  906. Assert(type.form # IntermediateCode.Float,"forbidden offset on float");
  907. IF ticket = NIL THEN
  908. tempReg := ForceFreeRegister(type);
  909. TicketToOperand(ReservePhysicalRegister(IntermediateCode.GeneralPurposeRegister,type,tempReg,inPC),tmp);
  910. ELSE
  911. TicketToOperand(ticket, tmp);
  912. ticket := NIL;
  913. END;
  914. IF Assembler.IsRegisterOperand(physical) & (type.sizeInBits > 8) THEN
  915. Assembler.InitMem(physical,SHORTINT(type.length * type.sizeInBits DIV 8) , physical.register, virtual.offset);
  916. emitter.Emit2(InstructionSet.opLEA, tmp,physical);
  917. ELSE
  918. emitter.Emit2(InstructionSet.opMOV,tmp,physical);
  919. Assembler.InitImm(imm,0 ,virtual.offset);
  920. emitter.Emit2(InstructionSet.opADD,tmp,imm);
  921. END;
  922. physical := tmp;
  923. END;
  924. END GetRegister;
  925. (* make physical operand from virtual operand, if ticket given then write result into phyiscal register represented by ticket *)
  926. PROCEDURE MakeOperand(CONST vop: IntermediateCode.Operand; part: LONGINT; VAR op: Assembler.Operand; ticket: Ticket);
  927. VAR tmp: Assembler.Operand;
  928. BEGIN
  929. TryAllocate(vop,part);
  930. CASE vop.mode OF
  931. IntermediateCode.ModeMemory: GetMemory(vop,part,op);
  932. |IntermediateCode.ModeRegister: GetRegister(vop,part,op,ticket);
  933. |IntermediateCode.ModeImmediate: GetImmediate(vop,part,op,FALSE);
  934. END;
  935. IF ticket # NIL THEN
  936. TicketToOperand(ticket, tmp);
  937. emitter.Emit2(InstructionSet.opMOV, tmp, op);
  938. (* should work but does not
  939. IF Assembler.IsRegisterOperand(op) THEN ReleaseHint(op.register) END;
  940. *)
  941. op := tmp;
  942. END;
  943. END MakeOperand;
  944. (* make physical register operand from virtual operand *)
  945. PROCEDURE MakeRegister(CONST vop: IntermediateCode.Operand; part: LONGINT; VAR op: Assembler.Operand);
  946. VAR previous: Assembler.Operand; temp: Ticket;
  947. BEGIN
  948. MakeOperand(vop,part,op,NIL);
  949. IF ~Assembler.IsRegisterOperand(op) THEN
  950. previous := op;
  951. temp := TemporaryTicket(vop.registerClass,vop.type);
  952. TicketToOperand(temp,op);
  953. Move(op, previous, vop.type);
  954. END;
  955. END MakeRegister;
  956. (*------------------- helpers for code generation ----------------------*)
  957. (* move, potentially with conversion. parameter back used for moving back from temporary operand*)
  958. PROCEDURE SpecialMove(op, back: LONGINT; canStoreToMemory: BOOLEAN; VAR dest,src: Assembler.Operand; type: IntermediateCode.Type);
  959. VAR temp: Assembler.Operand; ticket: Ticket;
  960. BEGIN
  961. IF Assembler.SameOperand(src,dest) THEN (* do nothing *)
  962. ELSIF ~Assembler.IsMemoryOperand(dest) OR (~Assembler.IsMemoryOperand(src) & canStoreToMemory) THEN
  963. emitter.Emit2(op,dest,src);
  964. ELSE
  965. ticket := TemporaryTicket(IntermediateCode.GeneralPurposeRegister,type);
  966. TicketToOperand(ticket,temp);
  967. emitter.Emit2(op,temp,src);
  968. emitter.Emit2(back,dest,temp);
  969. UnmapTicket(ticket);
  970. END;
  971. END SpecialMove;
  972. PROCEDURE AllocateStack(sizeInBytes: LONGINT);
  973. VAR sizeOp: Assembler.Operand; opcode: LONGINT;
  974. BEGIN
  975. ASSERT(sizeInBytes MOD 4 (* (cpuBits DIV 8) *) = 0);
  976. IF sizeInBytes < 0 THEN
  977. sizeInBytes := -sizeInBytes; opcode := InstructionSet.opADD;
  978. ELSIF sizeInBytes > 0 THEN
  979. opcode := InstructionSet.opSUB;
  980. ELSE RETURN
  981. END;
  982. IF sizeInBytes < 128 THEN sizeOp := Assembler.NewImm8(sizeInBytes);
  983. ELSE sizeOp := Assembler.NewImm32(sizeInBytes);
  984. END;
  985. emitter.Emit2(opcode,opSP,sizeOp);
  986. END AllocateStack;
  987. (*------------------- generation = emit dispatch / emit procedures ----------------------*)
  988. PROCEDURE IsFloat(CONST operand: IntermediateCode.Operand): BOOLEAN;
  989. BEGIN RETURN operand.type.form = IntermediateCode.Float
  990. END IsFloat;
  991. PROCEDURE IsComplex(CONST operand: IntermediateCode.Operand): BOOLEAN;
  992. BEGIN RETURN (operand.type.form IN IntermediateCode.Integer) & (operand.type.sizeInBits > cpuBits)
  993. END IsComplex;
  994. PROCEDURE Generate*(VAR instruction: IntermediateCode.Instruction);
  995. VAR opcode: SHORTINT; ticket: Ticket; hwreg, lastUse, i, part: LONGINT;
  996. BEGIN
  997. (*!IF ((instruction.opcode = IntermediateCode.mov) OR (instruction.opcode = IntermediateCode.pop)) & (instruction.op1.register <= IntermediateCode.ParameterRegister) THEN
  998. hwreg := ParameterRegister(IntermediateCode.ParameterRegister-instruction.op1.register, instruction.op1.type);
  999. Spill(physicalRegisters.Mapped(hwreg));
  1000. lastUse := inPC+1;
  1001. WHILE (lastUse < in.pc) &
  1002. ((in.instructions[lastUse].opcode # IntermediateCode.push) OR (in.instructions[lastUse].op1.register # instruction.op1.register)) & (in.instructions[lastUse].opcode # IntermediateCode.call) DO
  1003. INC(lastUse)
  1004. END;
  1005. ticket := ReservePhysicalRegister(instruction.op1.type,hwreg,lastUse);
  1006. END;
  1007. *)
  1008. ReserveOperandRegisters(instruction.op1,TRUE); ReserveOperandRegisters(instruction.op2,TRUE);ReserveOperandRegisters(instruction.op3,TRUE);
  1009. (*TryAllocate(instruction.op1,Low);
  1010. IF IsComplex(instruction.op1) THEN TryAllocate(instruction.op1,High) END;
  1011. *)
  1012. opcode := instruction.opcode;
  1013. CASE opcode OF
  1014. IntermediateCode.nop: (* do nothing *)
  1015. |IntermediateCode.mov:
  1016. IF IsFloat(instruction.op1) OR IsFloat(instruction.op2) THEN
  1017. EmitMovFloat(instruction.op1,instruction.op2)
  1018. ELSE EmitMov(instruction.op1,instruction.op2,Low);
  1019. IF IsComplex(instruction.op1) THEN EmitMov(instruction.op1,instruction.op2, High) END;
  1020. END;
  1021. |IntermediateCode.conv:
  1022. IF IsFloat(instruction.op1) OR IsFloat(instruction.op2) THEN
  1023. EmitConvertFloat(instruction)
  1024. ELSE
  1025. EmitConvert(instruction.op1,instruction.op2,Low);
  1026. IF IsComplex(instruction.op1) THEN EmitConvert(instruction.op1,instruction.op2,High) END;
  1027. END;
  1028. |IntermediateCode.call: EmitCall(instruction);
  1029. |IntermediateCode.enter: EmitEnter(instruction);
  1030. |IntermediateCode.leave: EmitLeave(instruction);
  1031. |IntermediateCode.exit: EmitExit(instruction);
  1032. |IntermediateCode.result:
  1033. IF IsFloat(instruction.op1) & backend.forceFPU THEN
  1034. EmitResultFPU(instruction)
  1035. ELSE
  1036. EmitResult(instruction);
  1037. END;
  1038. |IntermediateCode.return:
  1039. IF IsFloat(instruction.op1) & backend.forceFPU THEN
  1040. EmitReturnFPU(instruction)
  1041. ELSE
  1042. EmitReturn(instruction,Low);
  1043. IF IsComplex(instruction.op1) THEN EmitReturn(instruction, High) END;
  1044. END;
  1045. |IntermediateCode.trap: EmitTrap(instruction);
  1046. |IntermediateCode.br .. IntermediateCode.brlt: EmitBr(instruction)
  1047. |IntermediateCode.pop:
  1048. IF IsFloat(instruction.op1) THEN
  1049. EmitPopFloat(instruction.op1)
  1050. ELSE
  1051. EmitPop(instruction.op1,Low);
  1052. IF IsComplex(instruction.op1) THEN
  1053. EmitPop(instruction.op1,High)
  1054. END;
  1055. END;
  1056. |IntermediateCode.push:
  1057. IF IsFloat(instruction.op1) THEN
  1058. EmitPushFloat(instruction.op1)
  1059. ELSE
  1060. IF IsComplex(instruction.op1) THEN
  1061. EmitPush(instruction.op1,High);
  1062. END;
  1063. EmitPush(instruction.op1,Low)
  1064. END;
  1065. |IntermediateCode.neg:
  1066. IF IsFloat(instruction.op1) THEN
  1067. IF backend.forceFPU THEN
  1068. EmitArithmetic2FPU(instruction,InstructionSet.opFCHS)
  1069. ELSE
  1070. EmitNegXMM(instruction)
  1071. END;
  1072. ELSE EmitNeg(instruction);
  1073. END;
  1074. |IntermediateCode.not:
  1075. Assert(~IsFloat(instruction.op1),"instruction not supported for float");
  1076. EmitArithmetic2(instruction,Low,InstructionSet.opNOT);
  1077. IF IsComplex(instruction.op1) THEN EmitArithmetic2(instruction, High, InstructionSet.opNOT) END;
  1078. |IntermediateCode.abs:
  1079. IF IsFloat(instruction.op1) THEN
  1080. IF backend.forceFPU THEN
  1081. EmitArithmetic2FPU(instruction,InstructionSet.opFABS)
  1082. ELSE
  1083. EmitAbsXMM(instruction)
  1084. END;
  1085. ELSE EmitAbs(instruction);
  1086. END;
  1087. |IntermediateCode.mul:
  1088. IF IsFloat(instruction.op1) THEN
  1089. IF backend.forceFPU THEN
  1090. EmitArithmetic3FPU(instruction,InstructionSet.opFMUL)
  1091. ELSE
  1092. EmitArithmetic3XMM(instruction, InstructionSet.opMULSS, InstructionSet.opMULSD)
  1093. END;
  1094. ELSE
  1095. EmitMul(instruction);
  1096. END;
  1097. |IntermediateCode.div:
  1098. IF IsFloat(instruction.op1 )THEN
  1099. IF backend.forceFPU THEN
  1100. EmitArithmetic3FPU(instruction,InstructionSet.opFDIV)
  1101. ELSE
  1102. EmitArithmetic3XMM(instruction, InstructionSet.opDIVSS, InstructionSet.opDIVSD)
  1103. END;
  1104. ELSE
  1105. EmitDivMod(instruction);
  1106. END;
  1107. |IntermediateCode.mod:
  1108. Assert(~IsFloat(instruction.op1),"instruction not supported for float");
  1109. EmitDivMod(instruction);
  1110. |IntermediateCode.sub:
  1111. IF IsFloat(instruction.op1) THEN
  1112. IF backend.forceFPU THEN
  1113. EmitArithmetic3FPU(instruction,InstructionSet.opFSUB)
  1114. ELSE
  1115. EmitArithmetic3XMM(instruction, InstructionSet.opSUBSS, InstructionSet.opSUBSD)
  1116. END;
  1117. ELSE EmitArithmetic3Part(instruction,Low,InstructionSet.opSUB);
  1118. IF IsComplex(instruction.op1) THEN EmitArithmetic3Part(instruction, High, InstructionSet.opSBB) END;
  1119. END;
  1120. |IntermediateCode.add:
  1121. IF IsFloat(instruction.op1) THEN
  1122. IF backend.forceFPU THEN
  1123. EmitArithmetic3FPU(instruction,InstructionSet.opFADD)
  1124. ELSE
  1125. EmitArithmetic3XMM(instruction, InstructionSet.opADDSS, InstructionSet.opADDSD)
  1126. END;
  1127. ELSE EmitArithmetic3Part(instruction,Low,InstructionSet.opADD);
  1128. IF IsComplex(instruction.op1) THEN EmitArithmetic3Part(instruction, High, InstructionSet.opADC) END;
  1129. END;
  1130. |IntermediateCode.and:
  1131. Assert(~IsFloat(instruction.op1),"operation not defined on float");
  1132. EmitArithmetic3(instruction,InstructionSet.opAND);
  1133. |IntermediateCode.or:
  1134. Assert(~IsFloat(instruction.op1),"operation not defined on float");
  1135. EmitArithmetic3(instruction,InstructionSet.opOR);
  1136. |IntermediateCode.xor:
  1137. Assert(~IsFloat(instruction.op1),"operation not defined on float");
  1138. EmitArithmetic3(instruction,InstructionSet.opXOR);
  1139. |IntermediateCode.shl: EmitShift(instruction);
  1140. |IntermediateCode.shr: EmitShift(instruction);
  1141. |IntermediateCode.rol: EmitShift(instruction);
  1142. |IntermediateCode.ror: EmitShift(instruction);
  1143. |IntermediateCode.cas: EmitCas(instruction);
  1144. |IntermediateCode.copy: EmitCopy(instruction);
  1145. |IntermediateCode.fill: EmitFill(instruction,FALSE);
  1146. |IntermediateCode.asm: EmitAsm(instruction);
  1147. END;
  1148. ReserveOperandRegisters(instruction.op3,FALSE); ReserveOperandRegisters(instruction.op2,FALSE); ReserveOperandRegisters(instruction.op1,FALSE);
  1149. END Generate;
  1150. PROCEDURE PostGenerate*(CONST instruction: IntermediateCode.Instruction);
  1151. VAR ticket: Ticket;
  1152. BEGIN
  1153. TryUnmap(instruction.op3); TryUnmap(instruction.op2); TryUnmap(instruction.op1);
  1154. ticket := tickets.live;
  1155. WHILE (ticket # NIL) & (ticket.lastuse = inPC) DO
  1156. UnmapTicket(ticket);
  1157. ticket := tickets.live
  1158. END;
  1159. END PostGenerate;
  1160. (* enter procedure: generate PAF and clear stack *)
  1161. PROCEDURE EmitEnter(CONST instruction: IntermediateCode.Instruction);
  1162. VAR op1,imm,target: Assembler.Operand; cc,size,numberMachineWords,destPC,firstPC,secondPC,x: LONGINT; body: SyntaxTree.Body; name: Basic.SegmentedName;
  1163. parametersSize: SIZE;
  1164. CONST initialize=TRUE; FirstOffset = 5; SecondOffset = 11;
  1165. BEGIN
  1166. stackSize := SHORT(instruction.op2.intValue);
  1167. size := stackSize;
  1168. INC(traceStackSize, stackSize);
  1169. IF initialize THEN
  1170. (* always including this instruction make trace insertion possible *)
  1171. IF backend.traceable THEN
  1172. emitter.Emit2(InstructionSet.opXOR,opRA,opRA);
  1173. END;
  1174. ASSERT(size MOD opRA.sizeInBytes = 0);
  1175. numberMachineWords := size DIV opRA.sizeInBytes;
  1176. IF numberMachineWords >0 THEN
  1177. IF ~backend.traceable THEN
  1178. emitter.Emit2(InstructionSet.opXOR,opRA,opRA);
  1179. END;
  1180. WHILE numberMachineWords MOD 4 # 0 DO
  1181. emitter.Emit1(InstructionSet.opPUSH, opRA);
  1182. DEC(numberMachineWords);
  1183. END;
  1184. IF numberMachineWords >4 THEN
  1185. Assembler.InitImm(imm, 0, numberMachineWords DIV 4);
  1186. (* do not use EBX because it is not volative in WINAPI, do not use ECX: special register in COOP, do not use RD: register param in SysVABI *)
  1187. IF cpuBits = 64 THEN
  1188. emitter.Emit2(InstructionSet.opMOV, opR10, imm);
  1189. destPC := out.pc;
  1190. emitter.Emit1(InstructionSet.opDEC, opR10);
  1191. ELSE
  1192. emitter.Emit2(InstructionSet.opMOV, opRD, imm);
  1193. destPC := out.pc;
  1194. emitter.Emit1(InstructionSet.opDEC, opRD);
  1195. END;
  1196. emitter.Emit1(InstructionSet.opPUSH, opRA);
  1197. emitter.Emit1(InstructionSet.opPUSH, opRA);
  1198. emitter.Emit1(InstructionSet.opPUSH, opRA);
  1199. emitter.Emit1(InstructionSet.opPUSH, opRA);
  1200. Assembler.InitOffset8(target,destPC);
  1201. emitter.Emit1(InstructionSet.opJNZ, target)
  1202. ELSE
  1203. WHILE numberMachineWords >0 DO
  1204. emitter.Emit1(InstructionSet.opPUSH, opRA);
  1205. DEC(numberMachineWords);
  1206. END;
  1207. END;
  1208. END;
  1209. IF spillStack.MaxSize()>0 THEN (* register spill stack, does not have to be initialized *)
  1210. op1 := Assembler.NewImm32(spillStack.MaxSize()*cpuBits DIV 8);
  1211. emitter.Emit2(InstructionSet.opSUB,opSP,op1);
  1212. END;
  1213. ELSE
  1214. op1 := Assembler.NewImm32(size+ spillStack.MaxSize());
  1215. emitter.Emit2(InstructionSet.opSUB,opSP,op1);
  1216. END;
  1217. cc := SHORT(instruction.op1.intValue);
  1218. IF (cc = SyntaxTree.WinAPICallingConvention) OR (cc = SyntaxTree.CCallingConvention) THEN
  1219. IF cpuBits = 32 THEN
  1220. (* the winapi calling convention presumes that all registers except EAX, EDX and ECX are retained by the callee *)
  1221. emitter.Emit1(InstructionSet.opPUSH,opEBX);
  1222. emitter.Emit1(InstructionSet.opPUSH,opEDI);
  1223. emitter.Emit1(InstructionSet.opPUSH,opESI);
  1224. ELSE ASSERT(cpuBits =64);
  1225. emitter.Emit1(InstructionSet.opPUSH,opRB);
  1226. emitter.Emit1(InstructionSet.opPUSH,opRDI);
  1227. emitter.Emit1(InstructionSet.opPUSH,opRSI);
  1228. emitter.Emit1(InstructionSet.opPUSH,opR12);
  1229. emitter.Emit1(InstructionSet.opPUSH,opR13);
  1230. emitter.Emit1(InstructionSet.opPUSH,opR14);
  1231. emitter.Emit1(InstructionSet.opPUSH,opR15);
  1232. END;
  1233. END;
  1234. spillStackStart := stackSize;
  1235. END EmitEnter;
  1236. PROCEDURE EmitLeave(CONST instruction: IntermediateCode.Instruction);
  1237. VAR cc: LONGINT; offset: Assembler.Operand;
  1238. BEGIN
  1239. cc := SHORT(instruction.op1.intValue);
  1240. IF (cc = SyntaxTree.WinAPICallingConvention) OR (cc = SyntaxTree.CCallingConvention) THEN
  1241. IF cpuBits = 32 THEN
  1242. emitter.Emit1(InstructionSet.opPOP,opESI);
  1243. emitter.Emit1(InstructionSet.opPOP,opEDI);
  1244. emitter.Emit1(InstructionSet.opPOP,opEBX);
  1245. ELSE ASSERT(cpuBits =64);
  1246. emitter.Emit1(InstructionSet.opPOP,opR15);
  1247. emitter.Emit1(InstructionSet.opPOP,opR14);
  1248. emitter.Emit1(InstructionSet.opPOP,opR13);
  1249. emitter.Emit1(InstructionSet.opPOP,opR12);
  1250. emitter.Emit1(InstructionSet.opPOP,opRSI);
  1251. emitter.Emit1(InstructionSet.opPOP,opRDI);
  1252. emitter.Emit1(InstructionSet.opPOP,opRB);
  1253. END;
  1254. END;
  1255. END EmitLeave;
  1256. PROCEDURE EmitExit(CONST instruction: IntermediateCode.Instruction);
  1257. VAR parSize,cc: LONGINT; operand: Assembler.Operand;
  1258. BEGIN
  1259. cc := SHORT(instruction.op2.intValue);
  1260. parSize := SHORT(instruction.op3.intValue);
  1261. IF (parSize = 0) OR (cc = SyntaxTree.WinAPICallingConvention) & (cpuBits = 64) THEN
  1262. emitter.Emit0(InstructionSet.opRET)
  1263. ELSE (* e.g. for WINAPI calling convention *)
  1264. operand := Assembler.NewImm16(parSize);
  1265. emitter.Emit1(InstructionSet.opRET,operand)
  1266. END;
  1267. IF fpStackPointer # 0 THEN Error(instruction.textPosition,"compiler implementation error: fp stack not cleared") END;
  1268. END EmitExit;
  1269. PROCEDURE EmitReturnFPU(CONST instruction: IntermediateCode.Instruction);
  1270. VAR operand: Assembler.Operand;
  1271. BEGIN
  1272. IF IsRegister(instruction.op1) & MappedTo(instruction.op1.register,Low, ST0) THEN
  1273. (* nothing to do: result is already in return register *)
  1274. ELSE
  1275. MakeOperand(instruction.op1, Low, operand,NIL);
  1276. emitter.Emit1(InstructionSet.opFLD,operand);
  1277. (*
  1278. not necessary to clear from top of stack as callee will clear
  1279. INC(fpStackPointer);
  1280. emitter.Emit1(InstructionSet.opFSTP,registerOperands[ST0+1]);
  1281. DEC(fpStackPointer);
  1282. *)
  1283. END;
  1284. END EmitReturnFPU;
  1285. (* return operand
  1286. store operand in return register or on fp stack
  1287. *)
  1288. PROCEDURE EmitReturn(CONST instruction: IntermediateCode.Instruction; part: LONGINT);
  1289. VAR return,operand: Assembler.Operand; register: LONGINT; ticket: Ticket; type: IntermediateCode.Type;
  1290. BEGIN
  1291. register := ResultRegister(instruction.op1.type, part);
  1292. IF IsRegister(instruction.op1) & MappedTo(instruction.op1.register,part, register) THEN
  1293. (* nothing to do: result is already in return register *)
  1294. ELSE
  1295. GetPartType(instruction.op1.type,part, type);
  1296. MakeOperand(instruction.op1, part, operand,NIL);
  1297. Spill(physicalRegisters.Mapped(register));
  1298. ticket := ReservePhysicalRegister(IntermediateCode.GeneralPurposeRegister,type,register,inPC);
  1299. TicketToOperand(ticket, return);
  1300. (* Mov takes care of potential register overlaps *)
  1301. Move(return, operand, type);
  1302. UnmapTicket(ticket);
  1303. END;
  1304. END EmitReturn;
  1305. PROCEDURE EmitMovFloat(CONST vdest,vsrc:IntermediateCode.Operand);
  1306. VAR dest,src, espm: Assembler.Operand; sizeInBytes: SHORTINT; vcopy: IntermediateCode.Operand;
  1307. BEGIN
  1308. sizeInBytes := SHORTINT(vdest.type.sizeInBits DIV 8);
  1309. IF vdest.type.form IN IntermediateCode.Integer THEN
  1310. (* e.g. in SYSTEM.VAL(LONGINT, r) *)
  1311. IF vsrc.mode = IntermediateCode.ModeMemory THEN
  1312. vcopy := vsrc; IntermediateCode.SetType(vcopy,vdest.type);
  1313. EmitMov(vdest, vcopy,Low);
  1314. IF IsComplex(vdest) THEN
  1315. EmitMov(vdest,vcopy,High);
  1316. END;
  1317. ELSE
  1318. IF backend.forceFPU THEN
  1319. MakeOperand(vsrc,Low,src,NIL);
  1320. emitter.Emit1(InstructionSet.opFLD,src);
  1321. INC(fpStackPointer);
  1322. IF vdest.mode = IntermediateCode.ModeMemory THEN
  1323. MakeOperand(vdest,Low,dest,NIL);
  1324. Assembler.SetSize(dest,sizeInBytes);
  1325. emitter.Emit1(InstructionSet.opFSTP,dest);
  1326. DEC(fpStackPointer);
  1327. ELSE
  1328. AllocateStack(sizeInBytes);
  1329. Assembler.InitMem(espm, sizeInBytes,SP,0);
  1330. emitter.Emit1(InstructionSet.opFSTP,espm);
  1331. DEC(fpStackPointer);
  1332. MakeOperand(vdest,Low,dest,NIL);
  1333. EmitPop(vdest,Low);
  1334. IF IsComplex(vdest) THEN
  1335. EmitPop(vdest,High);
  1336. END;
  1337. END;
  1338. ELSE
  1339. MakeOperand(vsrc, Low, src, NIL);
  1340. IF vdest.mode = IntermediateCode.ModeMemory THEN
  1341. MakeOperand(vdest, Low, dest, NIL);
  1342. Move(dest, src, vsrc.type);
  1343. ELSE (* need temporary stack argument *)
  1344. AllocateStack(sizeInBytes);
  1345. Assembler.InitMem(espm, sizeInBytes,SP,0);
  1346. Move(espm, src, vsrc.type);
  1347. MakeOperand(vdest,Low,dest,NIL);
  1348. EmitPop(vdest,Low);
  1349. IF IsComplex(vdest) THEN
  1350. EmitPop(vdest,High);
  1351. END;
  1352. END;
  1353. END;
  1354. END;
  1355. ELSIF vsrc.type.form IN IntermediateCode.Integer THEN
  1356. (* e.g. in SYSTEM.VAL(REAL, i) *)
  1357. IF vdest.mode = IntermediateCode.ModeMemory THEN
  1358. vcopy := vdest; IntermediateCode.SetType(vcopy,vsrc.type);
  1359. EmitMov(vcopy, vsrc,Low);
  1360. IF IsComplex(vsrc) THEN
  1361. EmitMov(vcopy,vsrc,High);
  1362. END;
  1363. ELSE
  1364. IF backend.forceFPU THEN
  1365. IF vsrc.mode = IntermediateCode.ModeMemory THEN
  1366. MakeOperand(vsrc,Low,src,NIL);
  1367. Assembler.SetSize(src,sizeInBytes);
  1368. emitter.Emit1(InstructionSet.opFLD,src);
  1369. ELSE
  1370. IF IsComplex(vsrc) THEN
  1371. EmitPush(vsrc,High);
  1372. END;
  1373. EmitPush(vsrc,Low);
  1374. Assembler.InitMem(espm, sizeInBytes,SP,0);
  1375. emitter.Emit1(InstructionSet.opFLD,espm);
  1376. ASSERT(sizeInBytes >0);
  1377. AllocateStack(-sizeInBytes);
  1378. END;
  1379. INC(fpStackPointer);
  1380. MakeOperand(vdest,Low,dest,NIL);
  1381. emitter.Emit1(InstructionSet.opFSTP,dest);
  1382. DEC(fpStackPointer);
  1383. ELSE
  1384. IF vsrc.mode = IntermediateCode.ModeMemory THEN
  1385. MakeOperand(vsrc,Low,src,NIL);
  1386. Assembler.SetSize(src,sizeInBytes);
  1387. MakeOperand(vdest,Low,dest,NIL);
  1388. Move(dest, src, vdest.type);
  1389. ELSE
  1390. IF IsComplex(vsrc) THEN
  1391. EmitPush(vsrc,High);
  1392. END;
  1393. EmitPush(vsrc,Low);
  1394. Assembler.InitMem(espm, sizeInBytes,SP,0);
  1395. MakeOperand(vdest, Low, dest, NIL);
  1396. Move(dest, espm, vdest.type);
  1397. AllocateStack(-sizeInBytes);
  1398. END;
  1399. END;
  1400. END;
  1401. ELSE
  1402. IF backend.forceFPU THEN
  1403. MakeOperand(vsrc,Low,src,NIL);
  1404. emitter.Emit1(InstructionSet.opFLD,src);
  1405. INC(fpStackPointer);
  1406. MakeOperand(vdest,Low,dest,NIL);
  1407. emitter.Emit1(InstructionSet.opFSTP,dest);
  1408. DEC(fpStackPointer);
  1409. ELSE
  1410. MakeOperand(vsrc, Low, src, NIL);
  1411. MakeOperand(vdest, Low, dest, NIL);
  1412. Move(dest, src, vdest.type)
  1413. END;
  1414. END;
  1415. END EmitMovFloat;
  1416. PROCEDURE EmitMov(CONST vdest,vsrc: IntermediateCode.Operand; part: LONGINT);
  1417. VAR op1,op2: Assembler.Operand; tmp: IntermediateCode.Operand;
  1418. t: CodeGenerators.Ticket;
  1419. type: IntermediateCode.Type;
  1420. offset: LONGINT;
  1421. BEGIN
  1422. IF (vdest.mode = IntermediateCode.ModeRegister) & (vsrc.mode = IntermediateCode.ModeRegister) & (vsrc.type.sizeInBits > 8) & (vsrc.offset # 0)THEN
  1423. (* MOV R1, R2+offset => LEA EAX, [EBX+offset] *)
  1424. tmp := vsrc;
  1425. IntermediateCode.MakeMemory(tmp,vsrc.type);
  1426. MakeOperand(tmp,part,op2,NIL);
  1427. (*
  1428. ReleaseHint(op2.register);
  1429. *)
  1430. MakeOperand(vdest,part,op1,NIL);
  1431. t := virtualRegisters.Mapped(vdest.register,part);
  1432. IF (t # NIL) & (t.spilled) THEN
  1433. UnSpill(t); (* make sure this has not spilled *)
  1434. MakeOperand(vdest,part, op1,NIL);
  1435. END;
  1436. emitter.Emit2(InstructionSet.opLEA,op1,op2);
  1437. ELSE
  1438. MakeOperand(vsrc,part,op2,NIL);
  1439. MakeOperand(vdest,part,op1,NIL);
  1440. GetPartType(vsrc.type, part, type);
  1441. Move(op1,op2, type);
  1442. END;
  1443. END EmitMov;
  1444. PROCEDURE EmitConvertFloat(CONST instruction: IntermediateCode.Instruction);
  1445. VAR destType, srcType, dtype: IntermediateCode.Type; dest,src,espm,imm: Assembler.Operand; sizeInBytes, index: LONGINT;
  1446. temp, temp2, temp3, temp4, zero: Assembler.Operand; ticket: Ticket; vdest, vsrc: IntermediateCode.Operand;
  1447. unsigned: BOOLEAN;
  1448. BEGIN
  1449. vdest := instruction.op1; vsrc := instruction.op2;
  1450. srcType := vsrc.type;
  1451. destType := vdest.type;
  1452. IF destType.form = IntermediateCode.Float THEN
  1453. CASE srcType.form OF
  1454. |IntermediateCode.Float: (* just a move *)
  1455. IF backend.forceFPU THEN
  1456. EmitMovFloat(vdest, vsrc);
  1457. ELSE
  1458. MakeOperand(vsrc,Low,src,NIL);
  1459. MakeOperand(vdest, Low, dest, NIL);
  1460. IF srcType.sizeInBits = 32 THEN
  1461. SpecialMove(InstructionSet.opCVTSS2SD, InstructionSet.opMOVSS, FALSE, dest, src, destType)
  1462. ELSE
  1463. SpecialMove(InstructionSet.opCVTSD2SS, InstructionSet.opMOVSD, FALSE, dest, src, destType)
  1464. END;
  1465. END;
  1466. |IntermediateCode.SignedInteger, IntermediateCode.UnsignedInteger:
  1467. (* put value to stack and then read from stack via Float *)
  1468. unsigned := srcType.form = IntermediateCode.UnsignedInteger;
  1469. IF vsrc.type.sizeInBits < IntermediateCode.Bits32 THEN
  1470. MakeOperand(vsrc,Low,src,NIL);
  1471. ticket := TemporaryTicket(IntermediateCode.GeneralPurposeRegister,IntermediateCode.int32);
  1472. TicketToOperand(ticket,temp);
  1473. IF unsigned THEN
  1474. emitter.Emit2(InstructionSet.opMOVZX,temp,src);
  1475. ELSE
  1476. emitter.Emit2(InstructionSet.opMOVSX,temp,src);
  1477. END;
  1478. IF backend.forceFPU THEN (* via stack *)
  1479. emitter.Emit1(InstructionSet.opPUSH,temp);
  1480. UnmapTicket(ticket);
  1481. sizeInBytes := temp.sizeInBytes;
  1482. ELSE (* via register *)
  1483. espm := temp;
  1484. sizeInBytes := 0
  1485. END;
  1486. ELSIF IsComplex(vsrc) THEN (* via stack *)
  1487. EmitPush(vsrc,High);
  1488. EmitPush(vsrc,Low);
  1489. sizeInBytes := 8
  1490. ELSIF unsigned & (cpuBits=32) & ( vsrc.type.sizeInBits = IntermediateCode.Bits32) THEN (* UNSIGNED32 *)
  1491. sizeInBytes := 8;
  1492. Assembler.InitImm(zero,0,0);
  1493. emitter.Emit1(InstructionSet.opPUSH,zero);
  1494. EmitPush(vsrc,Low);
  1495. ELSIF unsigned & ( vsrc.type.sizeInBits = IntermediateCode.Bits32) THEN (* UNSIGNED32 on 64-bit *)
  1496. MakeRegister(vsrc, Low, src);
  1497. index := src.register;
  1498. index := index MOD 32 + RAX;
  1499. src := registerOperands[index];
  1500. espm := src;
  1501. ELSE
  1502. IF backend.forceFPU THEN (* via stack *)
  1503. EmitPush(vsrc,Low);
  1504. sizeInBytes := SHORTINT(4 (* cpuBits DIV 8*)) (*SHORT(srcType.sizeInBits DIV 8)*);
  1505. ELSE (* via memory or register *)
  1506. sizeInBytes := 0;
  1507. MakeOperand(vsrc,Low,src,NIL);
  1508. IF Assembler.IsImmediateOperand(src) THEN (* use temporary register *)
  1509. ticket := TemporaryTicket(IntermediateCode.GeneralPurposeRegister,IntermediateCode.int32);
  1510. TicketToOperand(ticket,temp);
  1511. IF unsigned THEN
  1512. emitter.Emit2(InstructionSet.opMOVZX,temp,src);
  1513. ELSE
  1514. emitter.Emit2(InstructionSet.opMOVSX,temp,src);
  1515. END;
  1516. espm := temp
  1517. ELSE
  1518. espm := src
  1519. END;
  1520. END
  1521. END;
  1522. IF sizeInBytes > 0 THEN
  1523. Assembler.InitMem(espm, SHORTINT(sizeInBytes),SP,0);
  1524. END;
  1525. IF backend.forceFPU THEN
  1526. emitter.Emit1(InstructionSet.opFILD,espm);
  1527. INC(fpStackPointer);
  1528. ASSERT(sizeInBytes >0);
  1529. Basic.Align(sizeInBytes, 4 (* cpuBits DIV 8*));
  1530. AllocateStack(-sizeInBytes);
  1531. MakeOperand(vdest,Low,dest,NIL);
  1532. emitter.Emit1(InstructionSet.opFSTP,dest);
  1533. DEC(fpStackPointer);
  1534. ELSIF IsComplex(vsrc) OR unsigned & (cpuBits=32) & ( vsrc.type.sizeInBits = IntermediateCode.Bits32) THEN
  1535. emitter.Emit1(InstructionSet.opFILD,espm);
  1536. MakeOperand(vdest,Low,dest,NIL);
  1537. IF Assembler.IsMemoryOperand(dest) THEN
  1538. emitter.Emit1(InstructionSet.opFSTP,dest);
  1539. ELSE (* must be register *)
  1540. emitter.Emit1(InstructionSet.opFSTP,espm);
  1541. emitter.Emit2(InstructionSet.opMOVQ,dest,espm);
  1542. IF destType.sizeInBits = 32 THEN
  1543. emitter.Emit2(InstructionSet.opCVTSD2SS, dest,dest);
  1544. END;
  1545. END;
  1546. AllocateStack(-sizeInBytes);
  1547. ELSE
  1548. MakeOperand(vdest,Low,dest,NIL);
  1549. IF destType.sizeInBits = 32 THEN
  1550. emitter.Emit2(InstructionSet.opCVTSI2SS, dest, espm)
  1551. ELSE
  1552. emitter.Emit2(InstructionSet.opCVTSI2SD, dest, espm)
  1553. END;
  1554. AllocateStack(-sizeInBytes);
  1555. END;
  1556. END;
  1557. ELSE
  1558. ASSERT(destType.form IN IntermediateCode.Integer);
  1559. ASSERT(srcType.form = IntermediateCode.Float);
  1560. Assert(vdest.type.form = IntermediateCode.SignedInteger, "no entier as result for unsigned integer");
  1561. MakeOperand(vsrc,Low,src,NIL);
  1562. IF ~backend.forceFPU THEN
  1563. MakeOperand(vdest,Low,dest,ticket);
  1564. GetTemporaryRegister(srcType, temp);
  1565. GetTemporaryRegister(srcType, temp3);
  1566. IF destType.sizeInBits < 32 THEN
  1567. IntermediateCode.InitType(dtype, destType.form, 32);
  1568. GetTemporaryRegister(dtype, temp4);
  1569. ELSE
  1570. dtype := destType;
  1571. temp4 := dest;
  1572. END;
  1573. GetTemporaryRegister(dtype, temp2);
  1574. IF srcType.sizeInBits = 32 THEN
  1575. (* convert truncated -> negative numbers round up !*)
  1576. emitter.Emit2(InstructionSet.opCVTTSS2SI, temp4, src);
  1577. (* back to temporary mmx register *)
  1578. emitter.Emit2(InstructionSet.opCVTSI2SS, temp, temp4);
  1579. (* subtract *)
  1580. emitter.Emit2(InstructionSet.opMOVSS, temp3, src);
  1581. emitter.Emit2(InstructionSet.opSUBSS, temp3, temp);
  1582. (* back to a GP register in order to determine the sign bit *)
  1583. ELSE
  1584. emitter.Emit2(InstructionSet.opCVTTSD2SI, temp4, src);
  1585. emitter.Emit2(InstructionSet.opCVTSI2SD, temp, temp4);
  1586. emitter.Emit2(InstructionSet.opMOVSD, temp3, src);
  1587. emitter.Emit2(InstructionSet.opSUBSD, temp3, temp);
  1588. emitter.Emit2(InstructionSet.opCVTSD2SS, temp3, temp3);
  1589. END;
  1590. emitter.Emit2(InstructionSet.opMOVD, temp2, temp3);
  1591. Assembler.InitImm(imm, 0 ,srcType.sizeInBits-1);
  1592. emitter.Emit2(InstructionSet.opBT, temp2, imm);
  1593. Assembler.InitImm(imm, 0 ,0);
  1594. emitter.Emit2(InstructionSet.opSBB, temp4, imm);
  1595. IF dtype.sizeInBits # destType.sizeInBits THEN
  1596. index := temp4.register;
  1597. CASE destType.sizeInBits OF (* choose low part accordingly *)
  1598. IntermediateCode.Bits8: index := index MOD 32 + AL;
  1599. |IntermediateCode.Bits16: index := index MOD 32 + AX;
  1600. |IntermediateCode.Bits32: index := index MOD 32 + EAX;
  1601. END;
  1602. temp4 := registerOperands[index];
  1603. emitter.Emit2(InstructionSet.opMOV, dest, temp4);
  1604. END
  1605. ELSE
  1606. emitter.Emit1(InstructionSet.opFLD,src); INC(fpStackPointer);
  1607. MakeOperand(vdest,Low,dest,NIL);
  1608. IF destType.sizeInBits = IntermediateCode.Bits64 THEN AllocateStack(12) ELSE AllocateStack(8) END;
  1609. Assembler.InitMem(espm,IntermediateCode.Bits16 DIV 8,SP,0);
  1610. emitter.Emit1(InstructionSet.opFNSTCW,espm);
  1611. emitter.Emit0(InstructionSet.opFWAIT);
  1612. Assembler.InitMem(espm,IntermediateCode.Bits32 DIV 8,SP,0);
  1613. ticket := TemporaryTicket(IntermediateCode.GeneralPurposeRegister,IntermediateCode.int32);
  1614. TicketToOperand(ticket,temp);
  1615. emitter.Emit2(InstructionSet.opMOV,temp,espm);
  1616. imm := Assembler.NewImm32(0F3FFH);
  1617. emitter.Emit2(InstructionSet.opAND,temp,imm);
  1618. imm := Assembler.NewImm32(0400H);
  1619. emitter.Emit2(InstructionSet.opOR,temp,imm);
  1620. Assembler.InitMem(espm,IntermediateCode.Bits32 DIV 8,SP,4);
  1621. emitter.Emit2(InstructionSet.opMOV,espm,temp);
  1622. Assembler.InitMem(espm,IntermediateCode.Bits16 DIV 8,SP,4);
  1623. emitter.Emit1(InstructionSet.opFLDCW,espm);
  1624. IF destType.sizeInBits = IntermediateCode.Bits64 THEN
  1625. Assembler.InitMem(espm,IntermediateCode.Bits64 DIV 8,SP,4);
  1626. emitter.Emit1(InstructionSet.opFISTP,espm);DEC(fpStackPointer);
  1627. emitter.Emit0(InstructionSet.opFWAIT);
  1628. ELSE
  1629. Assembler.InitMem(espm,IntermediateCode.Bits32 DIV 8,SP,4);
  1630. emitter.Emit1(InstructionSet.opFISTP,espm); DEC(fpStackPointer);
  1631. emitter.Emit0(InstructionSet.opFWAIT);
  1632. END;
  1633. Assembler.InitMem(espm,IntermediateCode.Bits16 DIV 8,SP,0);
  1634. emitter.Emit1(InstructionSet.opFLDCW,espm);
  1635. emitter.Emit1(InstructionSet.opPOP,temp);
  1636. UnmapTicket(ticket);
  1637. emitter.Emit1(InstructionSet.opPOP,dest);
  1638. IF IsComplex(vdest) THEN
  1639. MakeOperand(vdest,High,dest,NIL);
  1640. emitter.Emit1(InstructionSet.opPOP,dest);
  1641. END;
  1642. END;
  1643. END;
  1644. END EmitConvertFloat;
  1645. PROCEDURE EmitConvert(CONST vdest, vsrc: IntermediateCode.Operand; part: LONGINT);
  1646. VAR destType, srcType: IntermediateCode.Type; op1,op2: Assembler.Operand; index: LONGINT; nul: Assembler.Operand;
  1647. ticket: Ticket; vop: IntermediateCode.Operand; ediReserved, esiReserved: BOOLEAN;
  1648. eax, edx: Ticket; symbol: ObjectFile.Identifier; offset: LONGINT;
  1649. BEGIN
  1650. GetPartType(vdest.type,part, destType);
  1651. GetPartType(vsrc.type,part,srcType);
  1652. ASSERT(vdest.type.form IN IntermediateCode.Integer);
  1653. ASSERT(destType.form IN IntermediateCode.Integer);
  1654. IF destType.sizeInBits < srcType.sizeInBits THEN (* SHORT *)
  1655. ASSERT(part # High);
  1656. MakeOperand(vdest,part,op1,NIL);
  1657. IF vsrc.mode = IntermediateCode.ModeImmediate THEN
  1658. vop := vsrc;
  1659. IntermediateCode.SetType(vop,destType);
  1660. MakeOperand(vop,part,op2,NIL);
  1661. ELSE
  1662. MakeOperand(vsrc,part,op2,NIL);
  1663. IF Assembler.IsRegisterOperand(op1) & ((op1.register DIV 32 >0) (* not 8 bit register *) OR (op1.register DIV 16 = 0) & (physicalRegisters.Mapped(op1.register MOD 16 + AH)=free) (* low 8 bit register with free upper part *)) THEN
  1664. (* try EAX <- EDI for dest = AL or AX, src=EDI *)
  1665. index := op1.register;
  1666. CASE srcType.sizeInBits OF
  1667. IntermediateCode.Bits16: index := index MOD 32 + AX;
  1668. |IntermediateCode.Bits32: index := index MOD 32 + EAX;
  1669. |IntermediateCode.Bits64: index := index MOD 32 + RAX;
  1670. END;
  1671. op1 := registerOperands[index];
  1672. ELSE
  1673. (* reserve register with a low part *)
  1674. IF destType.sizeInBits=8 THEN (* make sure that allocated temporary register has a low part with 8 bits, i.e. exclude ESI or EDI *)
  1675. ediReserved := physicalRegisters.Reserved(EDI);
  1676. esiReserved := physicalRegisters.Reserved(ESI);
  1677. physicalRegisters.SetReserved(EDI,TRUE); physicalRegisters.SetReserved(ESI,TRUE);
  1678. ticket := TemporaryTicket(IntermediateCode.GeneralPurposeRegister,srcType); (* register with low part *)
  1679. physicalRegisters.SetReserved(EDI,ediReserved); physicalRegisters.SetReserved(ESI,esiReserved);
  1680. ELSE
  1681. ticket := TemporaryTicket(IntermediateCode.GeneralPurposeRegister,srcType); (* any register with low part *)
  1682. END;
  1683. MakeOperand(vsrc,part,op2,ticket); (* stores op2 in ticket register *)
  1684. index := op2.register;
  1685. CASE destType.sizeInBits OF (* choose low part accordingly *)
  1686. IntermediateCode.Bits8: index := index MOD 32 + AL;
  1687. |IntermediateCode.Bits16: index := index MOD 32 + AX;
  1688. |IntermediateCode.Bits32: index := index MOD 32 + EAX;
  1689. END;
  1690. op2 := registerOperands[index];
  1691. END;
  1692. Move(op1,op2,PhysicalOperandType(op1));
  1693. END;
  1694. ELSIF destType.sizeInBits > srcType.sizeInBits THEN (* (implicit) LONG *)
  1695. IF part = High THEN
  1696. IF destType.form = IntermediateCode.SignedInteger THEN
  1697. Spill(physicalRegisters.Mapped(EAX));
  1698. eax := ReservePhysicalRegister(IntermediateCode.GeneralPurposeRegister,IntermediateCode.int32,EAX,inPC);
  1699. Spill(physicalRegisters.Mapped(EDX));
  1700. edx := ReservePhysicalRegister(IntermediateCode.GeneralPurposeRegister,IntermediateCode.int32,EDX,inPC);
  1701. IF vsrc.type.sizeInBits < 32 THEN
  1702. MakeOperand(vsrc,Low,op2,NIL);
  1703. SpecialMove(InstructionSet.opMOVSX,InstructionSet.opMOV, FALSE, opEAX,op2,PhysicalOperandType(opEAX));
  1704. ELSE
  1705. MakeOperand(vsrc,Low,op2,eax);
  1706. END;
  1707. emitter.Emit0(InstructionSet.opCDQ);
  1708. MakeOperand(vdest,High,op1,NIL);
  1709. emitter.Emit2(InstructionSet.opMOV,op1,opEDX);
  1710. UnmapTicket(eax); UnmapTicket(edx);
  1711. ELSE
  1712. MakeOperand(vdest,part,op1,NIL);
  1713. IF (vdest.mode = IntermediateCode.ModeRegister) THEN
  1714. emitter.Emit2(InstructionSet.opXOR,op1,op1)
  1715. ELSE
  1716. Assembler.InitImm(nul,0,0);
  1717. emitter.Emit2(InstructionSet.opMOV,op1,nul);
  1718. END;
  1719. END;
  1720. ELSE
  1721. ASSERT(part=Low);
  1722. MakeOperand(vdest,part,op1,NIL);
  1723. MakeOperand(vsrc,part,op2,NIL);
  1724. IF srcType.sizeInBits = destType.sizeInBits THEN
  1725. Move(op1,op2,PhysicalOperandType(op1));
  1726. ELSIF srcType.form = IntermediateCode.SignedInteger THEN
  1727. IF srcType.sizeInBits=32 THEN (* 64 bits only *)
  1728. ASSERT(cpuBits=64);
  1729. SpecialMove(InstructionSet.opMOVSXD,InstructionSet.opMOV, FALSE, op1,op2,PhysicalOperandType(op1));
  1730. ELSE
  1731. SpecialMove(InstructionSet.opMOVSX,InstructionSet.opMOV, FALSE, op1,op2,PhysicalOperandType(op1));
  1732. END;
  1733. ELSE
  1734. ASSERT(srcType.form = IntermediateCode.UnsignedInteger);
  1735. IF srcType.sizeInBits=32 THEN (* 64 bits only *)
  1736. ASSERT(cpuBits=64);
  1737. IF Assembler.IsRegisterOperand(op1) THEN
  1738. Move( registerOperands[op1.register MOD 32 + EAX], op2,srcType);
  1739. ELSE
  1740. ASSERT(Assembler.IsMemoryOperand(op1));
  1741. symbol := op1.symbol; offset := op1.offset;
  1742. Assembler.InitMem(op1,Assembler.bits32,op1.register, op1.displacement);
  1743. Assembler.SetSymbol(op1,symbol.name,symbol.fingerprint,offset,op1.displacement);
  1744. Move( op1, op2, srcType);
  1745. Assembler.InitMem(op1,Assembler.bits32,op1.register, op1.displacement+Assembler.bits32);
  1746. Assembler.SetSymbol(op1,symbol.name, symbol.fingerprint,offset,op1.displacement);
  1747. Assembler.InitImm(op2,0,0);
  1748. Move( op1, op2,srcType);
  1749. END;
  1750. ELSE
  1751. SpecialMove(InstructionSet.opMOVZX, InstructionSet.opMOV, FALSE, op1, op2,PhysicalOperandType(op1))
  1752. END;
  1753. END;
  1754. END;
  1755. ELSE (* destType.sizeInBits = srcType.sizeInBits) *)
  1756. EmitMov(vdest,vsrc,part);
  1757. END;
  1758. END EmitConvert;
  1759. PROCEDURE EmitResult(CONST instruction: IntermediateCode.Instruction);
  1760. VAR result, resultHigh, op, opHigh: Assembler.Operand; register, highRegister: LONGINT; lowReserved, highReserved: BOOLEAN; type: IntermediateCode.Type;
  1761. BEGIN
  1762. IF ~IsComplex(instruction.op1) THEN
  1763. register := ResultRegister(instruction.op1.type,Low);
  1764. result := registerOperands[register];
  1765. MakeOperand(instruction.op1,Low,op,NIL);
  1766. GetPartType(instruction.op1.type, Low, type);
  1767. Move(op,result,type);
  1768. ELSE
  1769. register := ResultRegister(instruction.op1.type,Low);
  1770. result := registerOperands[register];
  1771. highRegister := ResultRegister(instruction.op1.type, High);
  1772. resultHigh := registerOperands[highRegister];
  1773. (* make sure that result registers are not used during emission of Low / High *)
  1774. lowReserved := physicalRegisters.Reserved(register);
  1775. physicalRegisters.SetReserved(register, TRUE);
  1776. highReserved := physicalRegisters.Reserved(highRegister);
  1777. physicalRegisters.SetReserved(highRegister,TRUE);
  1778. MakeOperand(instruction.op1,Low,op, NIL);
  1779. IF Assembler.SameOperand(op, resultHigh) THEN
  1780. emitter.Emit2(InstructionSet.opXCHG, result, resultHigh); (* low register already mapped ok *)
  1781. MakeOperand(instruction.op1, High, opHigh, NIL);
  1782. GetPartType(instruction.op1.type, High, type);
  1783. Move(opHigh, result, type);
  1784. ELSE
  1785. GetPartType(instruction.op1.type, Low, type);
  1786. Move(op, result, type);
  1787. MakeOperand(instruction.op1,High, opHigh, NIL);
  1788. GetPartType(instruction.op1.type, High, type);
  1789. Move(opHigh, resultHigh, type);
  1790. END;
  1791. physicalRegisters.SetReserved(register, lowReserved);
  1792. physicalRegisters.SetReserved(highRegister, highReserved);
  1793. END;
  1794. END EmitResult;
  1795. PROCEDURE EmitResultFPU(CONST instruction: IntermediateCode.Instruction);
  1796. VAR op: Assembler.Operand;
  1797. BEGIN
  1798. INC(fpStackPointer); (* callee has left the result on top of stack, don't have to allocate here *)
  1799. MakeOperand(instruction.op1,Low,op,NIL);
  1800. emitter.Emit1(InstructionSet.opFSTP,op);
  1801. DEC(fpStackPointer);
  1802. (*
  1803. UnmapTicket(ticket);
  1804. *)
  1805. END EmitResultFPU;
  1806. PROCEDURE EmitCall(CONST instruction: IntermediateCode.Instruction);
  1807. VAR fixup: Sections.Section; target, op, parSize: Assembler.Operand;
  1808. code: SyntaxTree.Code; emitterFixup,newFixup: BinaryCode.Fixup; resolved: BinaryCode.Section; pc: LONGINT;
  1809. BEGIN
  1810. IF fpStackPointer # 0 THEN Error(instruction.textPosition,"compiler implementation error: fp stack not cleared before call") END;
  1811. IF instruction.op1.mode = IntermediateCode.ModeImmediate THEN
  1812. fixup := module.allSections.FindByName(instruction.op1.symbol.name);
  1813. IF (fixup # NIL) & (fixup.type = Sections.InlineCodeSection) THEN
  1814. pc := out.pc;
  1815. (* resolved must be available at this point ! *)
  1816. resolved := fixup(IntermediateCode.Section).resolved;
  1817. IF resolved # NIL THEN
  1818. emitter.code.CopyBits(resolved.os.bits,0,resolved.os.bits.GetSize());
  1819. emitterFixup := resolved.fixupList.firstFixup;
  1820. WHILE (emitterFixup # NIL) DO
  1821. newFixup := BinaryCode.NewFixup(emitterFixup.mode,emitterFixup.offset+pc,emitterFixup.symbol,emitterFixup.symbolOffset,emitterFixup.displacement,emitterFixup.scale,emitterFixup.pattern);
  1822. out.fixupList.AddFixup(newFixup);
  1823. emitterFixup := emitterFixup.nextFixup;
  1824. END;
  1825. END;
  1826. ELSIF cpuBits = 64 THEN
  1827. MakeOperand(instruction.op1,Low,op,NIL);
  1828. emitter.Emit1(InstructionSet.opCALL,op);
  1829. Assembler.InitOffset32(parSize,instruction.op2.intValue);
  1830. IF parSize.val # 0 THEN emitter.Emit2(InstructionSet.opADD,opSP,parSize) END;
  1831. ELSE
  1832. Assembler.InitOffset32(target,instruction.op1.intValue);
  1833. Assembler.SetSymbol(target,instruction.op1.symbol.name,instruction.op1.symbol.fingerprint,instruction.op1.offset,0);
  1834. emitter.Emit1(InstructionSet.opCALL,target);
  1835. Assembler.InitOffset32(parSize,instruction.op2.intValue);
  1836. IF parSize.val # 0 THEN emitter.Emit2(InstructionSet.opADD,opSP,parSize) END;
  1837. END;
  1838. ELSE
  1839. MakeOperand(instruction.op1,Low,op,NIL);
  1840. emitter.Emit1(InstructionSet.opCALL,op);
  1841. Assembler.InitOffset32(parSize,instruction.op2.intValue);
  1842. IF parSize.val # 0 THEN emitter.Emit2(InstructionSet.opADD,opSP,parSize) END;
  1843. END;
  1844. END EmitCall;
  1845. (*
  1846. register allocation
  1847. instruction dest, src1, src2
  1848. preconditions
  1849. dest is memory operand or dest is register with offset = 0
  1850. src1 and src2 may be immediates, registers with or without offset and memory operands
  1851. 1.) translation into two-operand code
  1852. a) dest = src1 (no assumption on src2, src2=src1 is permitted )
  1853. i) dest and src2 are both memory operands or src2 is a register with offset # 0
  1854. alloc temp register
  1855. mov temp, src2
  1856. instruction2 dest, temp
  1857. ii) dest or src2 is not a memory operand
  1858. instruction2 dest, src2
  1859. b) dest = src2
  1860. => src2 is not a register with offset # 0
  1861. alloc temp register
  1862. mov dest, src1
  1863. mov temp, src2
  1864. instruction2 dest, temp
  1865. c) dest # src2
  1866. mov dest, src1
  1867. i) dest and src2 are both memory operands or src2 is a register with offset # 0
  1868. allocate temp register
  1869. mov temp, src2
  1870. instruction2 dest, temp
  1871. ii)
  1872. instruction2 dest, src2
  1873. 1'.) translation into one operand code
  1874. instruction dest, src1
  1875. a) dest = src1
  1876. => src1 is not a register with offset # 0
  1877. instruction1 dest
  1878. b) dest # src1
  1879. mov dest, src1
  1880. instruction1 dest
  1881. 2.) register allocation
  1882. precondition: src1 and src2 are already allocated
  1883. a) dest is already allocated
  1884. go on according to 1.
  1885. b) dest needs to be allocated
  1886. check if register is free
  1887. i) yes: allocate free register and go on with 1.
  1888. ii) no: spill last register in livelist, map register and go on with 1.
  1889. *)
  1890. PROCEDURE PrepareOp3(CONST instruction: IntermediateCode.Instruction;part: LONGINT; VAR left, right: Assembler.Operand; VAR ticket: Ticket);
  1891. VAR vop1,vop2, vop3: IntermediateCode.Operand; op1,op2,op3,temp: Assembler.Operand; type: IntermediateCode.Type;
  1892. t: Ticket;
  1893. BEGIN
  1894. ticket := NIL;
  1895. GetPartType(instruction.op1.type,part,type);
  1896. vop1 := instruction.op1; vop2 := instruction.op2; vop3 := instruction.op3;
  1897. IF IntermediateCode.OperandEquals(vop1,vop3) & (IntermediateCode.Commute23 IN IntermediateCode.instructionFormat[instruction.opcode].flags) THEN
  1898. vop3 := instruction.op2; vop2 := instruction.op3;
  1899. END;
  1900. MakeOperand(vop3,part, op3,NIL);
  1901. IF (vop1.mode = IntermediateCode.ModeRegister) & (~IsMemoryOperand(vop1,part)) & (vop1.register # vop3.register) THEN
  1902. IF (vop2.mode = IntermediateCode.ModeRegister) & (vop2.register = vop1.register) & (vop2.offset = 0) THEN
  1903. (* same register *)
  1904. MakeOperand(vop1,part, op1,NIL);
  1905. ELSE
  1906. MakeOperand(vop2,part, op2,NIL);
  1907. (*
  1908. ReleaseHint(op2.register);
  1909. *)
  1910. MakeOperand(vop1,part, op1,NIL);
  1911. Move(op1, op2, type);
  1912. t := virtualRegisters.Mapped(vop1.register,part);
  1913. IF (t # NIL) & (t.spilled) THEN
  1914. UnSpill(t); (* make sure this has not spilled *)
  1915. MakeOperand(vop1,part, op1,NIL);
  1916. END;
  1917. END;
  1918. left := op1; right := op3;
  1919. ELSIF IntermediateCode.OperandEquals(vop1,vop2) & (~IsMemoryOperand(vop1,part) OR ~IsMemoryOperand(vop3,part)) THEN
  1920. MakeOperand(vop1,part, op1,NIL);
  1921. left := op1; right := op3;
  1922. ELSE
  1923. MakeOperand(vop1,part, op1,NIL);
  1924. MakeOperand(vop2,part, op2,NIL);
  1925. (*ReleaseHint(op2.register);*)
  1926. ticket := TemporaryTicket(IntermediateCode.GeneralPurposeRegister,type);
  1927. TicketToOperand(ticket,temp);
  1928. Move(temp, op2, type);
  1929. left := temp; right := op3;
  1930. END;
  1931. END PrepareOp3;
  1932. PROCEDURE PrepareOp2(CONST instruction: IntermediateCode.Instruction; part: LONGINT; VAR left: Assembler.Operand;VAR ticket: Ticket);
  1933. VAR op2: Assembler.Operand; imm: Assembler.Operand; sizeInBits: INTEGER; type: IntermediateCode.Type;
  1934. BEGIN
  1935. ticket := NIL;
  1936. GetPartType(instruction.op1.type,part,type);
  1937. IF (instruction.op1.mode = IntermediateCode.ModeRegister) THEN
  1938. MakeOperand(instruction.op1,part,left,NIL);
  1939. MakeOperand(instruction.op2,part,op2,NIL);
  1940. IF (instruction.op2.mode = IntermediateCode.ModeRegister) & (instruction.op2.register = instruction.op1.register) & (instruction.op2.offset = 0) THEN
  1941. ELSE
  1942. Move(left, op2, type);
  1943. IF (instruction.op2.offset # 0) & ~IsMemoryOperand(instruction.op2,part) THEN
  1944. GetPartType(instruction.op2.type,part,type);
  1945. sizeInBits := type.sizeInBits;
  1946. Assembler.InitImm(imm,0,instruction.op2.offset);
  1947. emitter.Emit2(InstructionSet.opADD,left,imm);
  1948. END;
  1949. END;
  1950. ELSIF IntermediateCode.OperandEquals(instruction.op1,instruction.op2) & ((instruction.op1.mode # IntermediateCode.ModeMemory) OR (instruction.op3.mode # IntermediateCode.ModeMemory)) THEN
  1951. MakeOperand(instruction.op1,part,left,NIL);
  1952. ELSE
  1953. MakeOperand(instruction.op2,part, op2,NIL);
  1954. ticket := TemporaryTicket(IntermediateCode.GeneralPurposeRegister,type);
  1955. TicketToOperand(ticket,left);
  1956. Move(left, op2, type);
  1957. END;
  1958. END PrepareOp2;
  1959. PROCEDURE FinishOp(CONST vop: IntermediateCode.Operand; part: LONGINT; left: Assembler.Operand; ticket: Ticket);
  1960. VAR op1: Assembler.Operand;
  1961. BEGIN
  1962. IF ticket # NIL THEN
  1963. MakeOperand(vop,part, op1,NIL);
  1964. Move(op1,left,vop.type);
  1965. UnmapTicket(ticket);
  1966. END;
  1967. END FinishOp;
  1968. PROCEDURE EmitArithmetic3Part(CONST instruction: IntermediateCode.Instruction; part: LONGINT; opcode: LONGINT);
  1969. VAR left,right: Assembler.Operand; ticket: Ticket;
  1970. BEGIN
  1971. PrepareOp3(instruction, part, left,right,ticket);
  1972. emitter.Emit2(opcode,left,right);
  1973. FinishOp(instruction.op1,part,left,ticket);
  1974. END EmitArithmetic3Part;
  1975. PROCEDURE EmitArithmetic3(CONST instruction: IntermediateCode.Instruction; opcode: LONGINT);
  1976. BEGIN
  1977. EmitArithmetic3Part(instruction,Low,opcode);
  1978. IF IsComplex(instruction.op1) THEN EmitArithmetic3Part(instruction, High, opcode) END;
  1979. END EmitArithmetic3;
  1980. PROCEDURE EmitArithmetic3XMM(CONST instruction: IntermediateCode.Instruction; op32, op64: LONGINT);
  1981. VAR op: LONGINT;
  1982. BEGIN
  1983. IF instruction.op1.type.sizeInBits = 32 THEN op := op32 ELSE op := op64 END;
  1984. EmitArithmetic3Part(instruction, Low, op);
  1985. END EmitArithmetic3XMM;
  1986. PROCEDURE EmitArithmetic2(CONST instruction: IntermediateCode.Instruction; part: LONGINT; opcode: LONGINT);
  1987. VAR left:Assembler.Operand;ticket: Ticket;
  1988. BEGIN
  1989. PrepareOp2(instruction,part,left,ticket);
  1990. emitter.Emit1(opcode,left);
  1991. FinishOp(instruction.op1,part,left,ticket);
  1992. END EmitArithmetic2;
  1993. PROCEDURE EmitArithmetic2XMM(CONST instruction: IntermediateCode.Instruction; op32, op64: LONGINT);
  1994. VAR op: LONGINT;
  1995. BEGIN
  1996. IF instruction.op1.type.sizeInBits = 32 THEN op := op32 ELSE op := op64 END;
  1997. EmitArithmetic2(instruction, Low, op);
  1998. END EmitArithmetic2XMM;
  1999. PROCEDURE EmitArithmetic3FPU(CONST instruction: IntermediateCode.Instruction; op: LONGINT);
  2000. VAR op1,op2,op3: Assembler.Operand;
  2001. BEGIN
  2002. MakeOperand(instruction.op2,Low,op2,NIL);
  2003. emitter.Emit1(InstructionSet.opFLD,op2);
  2004. INC(fpStackPointer);
  2005. MakeOperand(instruction.op3,Low,op3,NIL);
  2006. IF instruction.op3.mode = IntermediateCode.ModeRegister THEN
  2007. emitter.Emit2(op,opST0,op3);
  2008. ELSE
  2009. emitter.Emit1(op,op3);
  2010. END;
  2011. MakeOperand(instruction.op1,Low,op1,NIL);
  2012. emitter.Emit1(InstructionSet.opFSTP,op1);
  2013. DEC(fpStackPointer);
  2014. END EmitArithmetic3FPU;
  2015. PROCEDURE EmitArithmetic2FPU(CONST instruction: IntermediateCode.Instruction; opcode: LONGINT);
  2016. VAR op1,op2: Assembler.Operand;
  2017. BEGIN
  2018. MakeOperand(instruction.op2,Low,op2,NIL);
  2019. emitter.Emit1(InstructionSet.opFLD,op2);
  2020. INC(fpStackPointer);
  2021. emitter.Emit0(opcode);
  2022. MakeOperand(instruction.op1,Low,op1,NIL);
  2023. emitter.Emit1(InstructionSet.opFSTP,op1);
  2024. DEC(fpStackPointer);
  2025. END EmitArithmetic2FPU;
  2026. PROCEDURE EmitMul(CONST instruction: IntermediateCode.Instruction);
  2027. VAR op1,op2,op3,temp: Assembler.Operand; ra,rd: Ticket;
  2028. value: HUGEINT; exp: LONGINT; iop3: IntermediateCode.Operand;
  2029. inst: IntermediateCode.Instruction;
  2030. BEGIN
  2031. IF IntermediateCode.IsConstantInteger(instruction.op3,value) & IntermediateBackend.PowerOf2(value,exp) THEN
  2032. IntermediateCode.InitImmediate(iop3, IntermediateCode.uint32, exp);
  2033. IntermediateCode.InitInstruction(inst, Basic.invalidPosition, IntermediateCode.shl, instruction.op1, instruction.op2, iop3);
  2034. EmitShift(inst);
  2035. RETURN;
  2036. END;
  2037. ASSERT(~IsComplex(instruction.op1));
  2038. ASSERT(instruction.op1.type.form IN IntermediateCode.Integer);
  2039. IF (instruction.op1.type.sizeInBits = IntermediateCode.Bits8) THEN
  2040. Spill(physicalRegisters.Mapped(AL));
  2041. Spill(physicalRegisters.Mapped(AH));
  2042. ra := ReservePhysicalRegister(IntermediateCode.GeneralPurposeRegister,IntermediateCode.int8,AL,inPC);
  2043. rd := ReservePhysicalRegister(IntermediateCode.GeneralPurposeRegister,IntermediateCode.int8,AH,inPC);
  2044. MakeOperand(instruction.op1,Low,op1,NIL);
  2045. MakeOperand(instruction.op2,Low,op2,ra);
  2046. IF instruction.op3.mode = IntermediateCode.ModeImmediate THEN
  2047. MakeOperand(instruction.op3,Low,op3,rd);
  2048. ELSE
  2049. MakeOperand(instruction.op3,Low,op3,NIL);
  2050. END;
  2051. emitter.Emit1(InstructionSet.opIMUL,op3);
  2052. emitter.Emit2(InstructionSet.opMOV,op1,opAL);
  2053. UnmapTicket(ra);
  2054. UnmapTicket(rd);
  2055. ELSE
  2056. MakeOperand(instruction.op1,Low,op1,NIL);
  2057. MakeOperand(instruction.op2,Low,op2,NIL);
  2058. MakeOperand(instruction.op3,Low,op3,NIL);
  2059. IF ~Assembler.IsRegisterOperand(op1) THEN
  2060. temp := op1;
  2061. ra := TemporaryTicket(instruction.op1.registerClass,instruction.op1.type);
  2062. TicketToOperand(ra,op1);
  2063. END;
  2064. IF Assembler.SameOperand(op1,op3) THEN temp := op2; op2 := op3; op3 := temp END;
  2065. IF Assembler.IsRegisterOperand(op2) OR Assembler.IsMemoryOperand(op2) THEN
  2066. IF Assembler.IsImmediateOperand(op3) THEN
  2067. emitter.Emit3(InstructionSet.opIMUL,op1,op2,op3);
  2068. ELSIF Assembler.IsRegisterOperand(op2) & (op2.register = op1.register) THEN
  2069. IF Assembler.IsRegisterOperand(op3) OR Assembler.IsMemoryOperand(op3) THEN
  2070. emitter.Emit2(InstructionSet.opIMUL,op1,op3);
  2071. ELSE
  2072. rd := TemporaryTicket(instruction.op1.registerClass,instruction.op1.type);
  2073. TicketToOperand(rd,temp);
  2074. Move(temp,op3,instruction.op1.type);
  2075. emitter.Emit2(InstructionSet.opIMUL,op1,temp);
  2076. UnmapTicket(rd);
  2077. END;
  2078. ELSE
  2079. Move(op1,op3,PhysicalOperandType(op1));
  2080. emitter.Emit2(InstructionSet.opIMUL,op1,op2);
  2081. END
  2082. ELSIF Assembler.IsRegisterOperand(op3) OR Assembler.IsMemoryOperand(op3) THEN
  2083. IF Assembler.IsImmediateOperand(op2) THEN
  2084. emitter.Emit3(InstructionSet.opIMUL,op1,op3,op2);
  2085. ELSIF Assembler.IsRegisterOperand(op3) & (op2.register = op1.register) THEN
  2086. IF Assembler.IsRegisterOperand(op2) OR Assembler.IsMemoryOperand(op2) THEN
  2087. emitter.Emit2(InstructionSet.opIMUL,op1,op2);
  2088. ELSE
  2089. rd := TemporaryTicket(instruction.op1.registerClass,instruction.op1.type);
  2090. TicketToOperand(rd,temp);
  2091. Move(temp,op2,instruction.op1.type);
  2092. emitter.Emit2(InstructionSet.opIMUL,op1,temp);
  2093. UnmapTicket(rd);
  2094. END;
  2095. ELSE
  2096. Move(op1,op2,PhysicalOperandType(op1));
  2097. emitter.Emit2(InstructionSet.opIMUL,op1,op3);
  2098. END;
  2099. END;
  2100. IF ra # NIL THEN
  2101. Move(temp,op1,PhysicalOperandType(op1));
  2102. UnmapTicket(ra);
  2103. END;
  2104. END;
  2105. END EmitMul;
  2106. PROCEDURE EmitDivMod(CONST instruction: IntermediateCode.Instruction);
  2107. VAR
  2108. dividend,quotient,remainder,imm,target,memop: Assembler.Operand;
  2109. op1,op2,op3: Assembler.Operand; ra,rd: Ticket;
  2110. size: LONGINT;
  2111. value: HUGEINT; exp: LONGINT; iop3: IntermediateCode.Operand;
  2112. inst: IntermediateCode.Instruction;
  2113. BEGIN
  2114. IF IntermediateCode.IsConstantInteger(instruction.op3,value) & IntermediateBackend.PowerOf2(value,exp) THEN
  2115. IF instruction.opcode = IntermediateCode.div THEN
  2116. IntermediateCode.InitImmediate(iop3, IntermediateCode.uint32, exp);
  2117. IntermediateCode.InitInstruction(inst, Basic.invalidPosition, IntermediateCode.shr, instruction.op1, instruction.op2, iop3);
  2118. EmitShift(inst);
  2119. RETURN;
  2120. ELSE
  2121. IntermediateCode.InitImmediate(iop3, instruction.op3.type, value-1);
  2122. IntermediateCode.InitInstruction(inst, Basic.invalidPosition, IntermediateCode.and, instruction.op1, instruction.op2, iop3);
  2123. EmitArithmetic3(inst,InstructionSet.opAND);
  2124. RETURN;
  2125. END;
  2126. END;
  2127. (*
  2128. In general it must obviously hold that
  2129. a = (a div b) * b + a mod b and
  2130. for all integers a,b#0, and c.
  2131. For positive numbers a and b this holds if
  2132. a div b = max{integer i: i*b <= b} = Entier(a/b)
  2133. and
  2134. a mod b = a-(a div b)*b = min{c >=0: c = a-i*b, integer i}
  2135. Example
  2136. 11 div 3 = 3 (3*3 = 9)
  2137. 11 mod 3 = 2 (=11-9)
  2138. for negative a there are two definitions for mod possible:
  2139. (i) mathematical definition with
  2140. a mod b >= 0:
  2141. a mod b = min{ c >=0: c = a-i*b, integer i} >= 0
  2142. this corresponds with rounding down
  2143. a div b = Entier(a/b) <= a/b
  2144. (ii) symmetric definition with
  2145. (-a) mod' b = -(a mod' b) and
  2146. (-a) div' b = -(a div' b)
  2147. corresponding with rounding to zero
  2148. a div' b = RoundToZero(a/b)
  2149. Examples
  2150. (i) -11 div 3 = -4 (3*(-4) = -12)
  2151. -11 mod 3 = 1 (=-11-(-12))
  2152. (ii) -11 div' 3 = -(11 div 3) = -3 (3*(-3)= -9)
  2153. -11 mod' 3 = -2 (=-11-(-9))
  2154. The behaviour for negative b can, in the symmetrical case, be deduced as
  2155. (ii) symmetric definition
  2156. a div' (-b) = (-a) div' b = -(a div' b)
  2157. a mod' (-b) = a- a div' (-b) * (-b) = a mod' b
  2158. In the mathematical case it is not so easy. It turns out that the definitions
  2159. a DIV b = Entier(a/b) = max{integer i: i*b <= b}
  2160. and
  2161. a MOD b = min { c >=0 : c = a-i*b, integer i} >= 0
  2162. are not compliant with
  2163. a = (a DIV b) * b + a MOD b
  2164. if b <= 0.
  2165. Proof: assume that b<0, then
  2166. a - Entier(a/b) * b >= 0
  2167. <=_> a >= Entier(a/b) * b
  2168. <=> Entier(a/b) >= a/b (contradiction to definition of Entier).
  2169. OBERON ADOPTS THE MATHEMATICAL DEFINITION !
  2170. For integers a and b (b>0) it holds that
  2171. a DIV b = Entier(a/b) <= a/b
  2172. a MOD b = min{ c >=0: c = b-i*a, integer i} = a - a DIV b * b
  2173. The behaviour for b < 0 is explicitely undefined.
  2174. *)
  2175. (*
  2176. AX / regMem8 = AL (remainder AH)
  2177. DX:AX / regmem16 = AX (remainder DX)
  2178. EDX:EAX / regmem32 = EAX (remainder EDX)
  2179. RDX:EAX / regmem64 = RAX (remainder RDX)
  2180. 1.) EAX <- source1
  2181. 2.) CDQ
  2182. 3.) IDIV source2
  2183. 3.) SHL EDX
  2184. 4.) SBB EAX,1
  2185. result is in EAX
  2186. *)
  2187. MakeOperand(instruction.op2,Low,op2,NIL);
  2188. CASE instruction.op1.type.sizeInBits OF
  2189. IntermediateCode.Bits8:
  2190. Spill(physicalRegisters.Mapped(AL)); ra := ReservePhysicalRegister(IntermediateCode.GeneralPurposeRegister,IntermediateCode.int8,AL,inPC);
  2191. emitter.Emit2(InstructionSet.opMOV,opAL,op2);
  2192. dividend := opAX;
  2193. quotient := opAL;
  2194. remainder := opAH;
  2195. emitter.Emit0(InstructionSet.opCBW);
  2196. | IntermediateCode.Bits16:
  2197. Spill(physicalRegisters.Mapped(AX)); ra := ReservePhysicalRegister(IntermediateCode.GeneralPurposeRegister,IntermediateCode.int16,AX,inPC);
  2198. emitter.Emit2(InstructionSet.opMOV,opAX,op2);
  2199. Spill(physicalRegisters.Mapped(DX)); rd := ReservePhysicalRegister(IntermediateCode.GeneralPurposeRegister,IntermediateCode.int16,DX,inPC);
  2200. dividend := opAX;
  2201. quotient := dividend;
  2202. remainder := opDX;
  2203. emitter.Emit0(InstructionSet.opCWD);
  2204. | IntermediateCode.Bits32:
  2205. Spill(physicalRegisters.Mapped(EAX)); ra := ReservePhysicalRegister(IntermediateCode.GeneralPurposeRegister,IntermediateCode.int32,EAX,inPC);
  2206. emitter.Emit2(InstructionSet.opMOV,opEAX,op2);
  2207. Spill(physicalRegisters.Mapped(EDX)); rd := ReservePhysicalRegister(IntermediateCode.GeneralPurposeRegister,IntermediateCode.int32,EDX,inPC);
  2208. dividend := opEAX;
  2209. quotient := dividend;
  2210. remainder := opEDX;
  2211. emitter.Emit0(InstructionSet.opCDQ);
  2212. | IntermediateCode.Bits64:
  2213. Spill(physicalRegisters.Mapped(RAX)); ra := ReservePhysicalRegister(IntermediateCode.GeneralPurposeRegister,IntermediateCode.int64,RAX,inPC);
  2214. emitter.Emit2(InstructionSet.opMOV,opRA,op2);
  2215. Spill(physicalRegisters.Mapped(RDX)); rd := ReservePhysicalRegister(IntermediateCode.GeneralPurposeRegister,IntermediateCode.int64,RDX,inPC);
  2216. dividend := opRA;
  2217. quotient := dividend;
  2218. remainder := registerOperands[RDX];
  2219. emitter.Emit0(InstructionSet.opCQO);
  2220. END;
  2221. (* registers might have been changed, so we make the operands now *)
  2222. MakeOperand(instruction.op1,Low,op1,NIL);
  2223. MakeOperand(instruction.op2,Low,op2,NIL);
  2224. MakeOperand(instruction.op3,Low,op3,NIL);
  2225. IF instruction.op3.mode = IntermediateCode.ModeImmediate THEN
  2226. size := instruction.op3.type.sizeInBits DIV 8;
  2227. Basic.Align(size, 4 (* cpuBits DIV 8 *) );
  2228. AllocateStack(size);
  2229. Assembler.InitMem(memop,SHORT(instruction.op3.type.sizeInBits DIV 8),SP,0);
  2230. emitter.Emit2(InstructionSet.opMOV,memop,op3);
  2231. op3 := memop;
  2232. END;
  2233. emitter.Emit1(InstructionSet.opIDIV,op3);
  2234. IF instruction.opcode = IntermediateCode.mod THEN
  2235. imm := Assembler.NewImm8 (0);
  2236. emitter.Emit2(InstructionSet.opCMP, remainder, imm);
  2237. Assembler.InitImm8(target,0);
  2238. emitter.Emit1(InstructionSet.opJGE, target);
  2239. emitter.Emit2( InstructionSet.opADD, remainder, op3);
  2240. emitter.code.PutByteAt(target.pc,(emitter.code.pc -target.pc )-1);
  2241. emitter.Emit2(InstructionSet.opMOV, op1, remainder);
  2242. ELSE
  2243. imm := Assembler.NewImm8 (1);
  2244. emitter.Emit2(InstructionSet.opSHL, remainder, imm);
  2245. imm := Assembler.NewImm8 (0);
  2246. emitter.Emit2(InstructionSet.opSBB, quotient, imm);
  2247. emitter.Emit2(InstructionSet.opMOV, op1, quotient);
  2248. END;
  2249. IF instruction.op3.mode = IntermediateCode.ModeImmediate THEN
  2250. size := instruction.op3.type.sizeInBits DIV 8;
  2251. Basic.Align(size, 4 (* cpuBits DIV 8*) );
  2252. AllocateStack(-size);
  2253. END;
  2254. END EmitDivMod;
  2255. PROCEDURE EmitShift(CONST instruction: IntermediateCode.Instruction);
  2256. VAR
  2257. shift: Assembler.Operand;
  2258. op: LONGINT;
  2259. op1,op2,op3,dest,temporary,op1High,op2High: Assembler.Operand;
  2260. index: SHORTINT; temp: Assembler.Operand;
  2261. left: BOOLEAN;
  2262. ecx,ticket: Ticket;
  2263. BEGIN
  2264. Assert(instruction.op1.type.form IN IntermediateCode.Integer,"must be integer operand");
  2265. IF instruction.op1.type.form = IntermediateCode.UnsignedInteger THEN
  2266. IF instruction.opcode = IntermediateCode.shr THEN op := InstructionSet.opSHR; left := FALSE;
  2267. ELSIF instruction.opcode = IntermediateCode.shl THEN op := InstructionSet.opSHL; left := TRUE;
  2268. ELSIF instruction.opcode = IntermediateCode.ror THEN op := InstructionSet.opROR; left := FALSE;
  2269. ELSIF instruction.opcode = IntermediateCode.rol THEN op := InstructionSet.opROL; left := TRUE;
  2270. END;
  2271. ELSE
  2272. IF instruction.opcode = IntermediateCode.shr THEN op := InstructionSet.opSAR; left := FALSE;
  2273. ELSIF instruction.opcode = IntermediateCode.shl THEN op := InstructionSet.opSAL; left := TRUE;
  2274. ELSIF instruction.opcode = IntermediateCode.ror THEN op := InstructionSet.opROR; left := FALSE;
  2275. ELSIF instruction.opcode = IntermediateCode.rol THEN op := InstructionSet.opROL; left := TRUE;
  2276. END;
  2277. END;
  2278. IF instruction.op3.mode # IntermediateCode.ModeImmediate THEN
  2279. IF backend.cooperative THEN ap.spillable := TRUE END;
  2280. Spill(physicalRegisters.Mapped(ECX));
  2281. ecx := ReservePhysicalRegister(IntermediateCode.GeneralPurposeRegister,IntermediateCode.int32,ECX,inPC);
  2282. END;
  2283. (*GetTemporaryRegister(instruction.op2.type,dest);*)
  2284. MakeOperand(instruction.op1,Low,op1,NIL);
  2285. IF ~Assembler.IsRegisterOperand(op1) THEN GetTemporaryRegister(instruction.op2.type,dest) ELSE dest := op1 END;
  2286. MakeOperand(instruction.op2,Low,op2,NIL);
  2287. MakeOperand(instruction.op3,Low,op3,NIL);
  2288. IF instruction.op3.mode = IntermediateCode.ModeImmediate THEN
  2289. Assembler.InitImm8(shift,instruction.op3.intValue);
  2290. ELSE
  2291. CASE instruction.op3.type.sizeInBits OF
  2292. IntermediateCode.Bits8: index := CL;
  2293. |IntermediateCode.Bits16: index := CX;
  2294. |IntermediateCode.Bits32: index := ECX;
  2295. |IntermediateCode.Bits64: index := RCX;
  2296. END;
  2297. (*
  2298. IF (physicalRegisters.toVirtual[index] # free) & ((physicalRegisters.toVirtual[index] # instruction.op1.register) OR (instruction.op1.mode # IntermediateCode.ModeRegister)) THEN
  2299. Spill();
  2300. (*
  2301. emitter.Emit1(InstructionSet.opPUSH,opECX);
  2302. ecxPushed := TRUE;
  2303. *)
  2304. END;
  2305. *)
  2306. ticket := virtualRegisters.Mapped(instruction.op3.register,Low);
  2307. IF (instruction.op3.mode # IntermediateCode.ModeRegister) OR (ticket = NIL) OR (ticket.spilled) OR (ticket.register # index) THEN
  2308. emitter.Emit2(InstructionSet.opMOV,registerOperands[index],op3);
  2309. END;
  2310. shift := opCL;
  2311. END;
  2312. IF ~IsComplex(instruction.op1) THEN
  2313. Move(dest,op2,PhysicalOperandType(dest));
  2314. emitter.Emit2 (op, dest,shift);
  2315. Move(op1,dest,PhysicalOperandType(op1));
  2316. ELSIF left THEN
  2317. MakeOperand(instruction.op1,High,op1High,NIL);
  2318. MakeOperand(instruction.op2,High,op2High,NIL);
  2319. IF ~IntermediateCode.OperandEquals(instruction.op1,instruction.op2) THEN
  2320. Move(op1,op2,PhysicalOperandType(op1));
  2321. Move(op1High,op2High,PhysicalOperandType(op1High))
  2322. END;
  2323. IF (instruction.opcode=IntermediateCode.rol) THEN
  2324. (* |high| <- |low| <- |temp=high| *)
  2325. ticket := TemporaryTicket(IntermediateCode.GeneralPurposeRegister,IntermediateCode.int32);
  2326. TicketToOperand(ticket,temp);
  2327. emitter.Emit2( InstructionSet.opMOV, temp, op1High);
  2328. emitter.Emit3( InstructionSet.opSHLD,op1High, op1, shift);
  2329. emitter.Emit3( InstructionSet.opSHLD, op1, temp, shift);
  2330. UnmapTicket(ticket);
  2331. ELSE
  2332. (* |high| <- |low| *)
  2333. emitter.Emit3( InstructionSet.opSHLD, op1,op1High,shift);
  2334. emitter.Emit2( op, op1,shift);
  2335. END;
  2336. ELSE
  2337. IF ~IntermediateCode.OperandEquals(instruction.op1,instruction.op2) THEN
  2338. Move(op1,op2,PhysicalOperandType(op1))
  2339. END;
  2340. IF instruction.opcode=IntermediateCode.ror THEN
  2341. (* |temp=low| -> |high| -> |low| *)
  2342. ticket := TemporaryTicket(IntermediateCode.GeneralPurposeRegister,IntermediateCode.int32);
  2343. TicketToOperand(ticket,temp);
  2344. emitter.Emit2( InstructionSet.opMOV, temporary, op1);
  2345. emitter.Emit3( InstructionSet.opSHRD,op1, op1High, shift);
  2346. emitter.Emit3( InstructionSet.opSHRD, op1High, temporary, shift);
  2347. UnmapTicket(ticket);
  2348. ELSE
  2349. (* |high| -> |low| *)
  2350. emitter.Emit3( InstructionSet.opSHRD, op1,op1High,shift);
  2351. emitter.Emit2( op, op1High, shift);
  2352. END;
  2353. END;
  2354. IF backend.cooperative & (instruction.op3.mode # IntermediateCode.ModeImmediate) THEN
  2355. UnmapTicket(ecx);
  2356. UnSpill(ap);
  2357. ap.spillable := FALSE;
  2358. END;
  2359. END EmitShift;
  2360. PROCEDURE EmitCas(CONST instruction: IntermediateCode.Instruction);
  2361. VAR ra: Ticket; op1,op2,op3,mem: Assembler.Operand; register: LONGINT;
  2362. BEGIN
  2363. CASE instruction.op2.type.sizeInBits OF
  2364. | IntermediateCode.Bits8: register := AL;
  2365. | IntermediateCode.Bits16: register := AX;
  2366. | IntermediateCode.Bits32: register := EAX;
  2367. | IntermediateCode.Bits64: register := RAX;
  2368. END;
  2369. Spill(physicalRegisters.Mapped(register));
  2370. ra := ReservePhysicalRegister(IntermediateCode.GeneralPurposeRegister,instruction.op2.type,register,inPC);
  2371. IF IntermediateCode.OperandEquals (instruction.op2,instruction.op3) THEN
  2372. MakeOperand(instruction.op1,Low,op1,ra);
  2373. Assembler.InitMem(mem,SHORT(instruction.op1.type.sizeInBits DIV 8),op1.register,0);
  2374. emitter.Emit2(InstructionSet.opMOV,op1,mem);
  2375. ELSE
  2376. MakeOperand(instruction.op2,Low,op2,ra);
  2377. MakeRegister(instruction.op1,Low,op1);
  2378. Assembler.InitMem(mem,SHORT(instruction.op2.type.sizeInBits DIV 8),op1.register,0);
  2379. MakeRegister(instruction.op3,Low,op3);
  2380. emitter.EmitPrefix (InstructionSet.prfLOCK);
  2381. emitter.Emit2(InstructionSet.opCMPXCHG,mem,op3);
  2382. END;
  2383. END EmitCas;
  2384. PROCEDURE EmitCopy(CONST instruction: IntermediateCode.Instruction);
  2385. VAR op1,op2,op3: Assembler.Operand; rs, rd, rc, t: Ticket; temp,imm: Assembler.Operand; source, dest: IntermediateCode.Operand; size: HUGEINT;
  2386. BEGIN
  2387. IF IntermediateCode.IsConstantInteger(instruction.op3, size) & (size = 4) THEN
  2388. Spill(physicalRegisters.Mapped(RS));
  2389. Spill(physicalRegisters.Mapped(RD));
  2390. rs := ReservePhysicalRegister(IntermediateCode.GeneralPurposeRegister,instruction.op1.type,RS,inPC);
  2391. rd := ReservePhysicalRegister(IntermediateCode.GeneralPurposeRegister,instruction.op1.type,RD,inPC);
  2392. MakeOperand(instruction.op1,Low,op1,rd);
  2393. MakeOperand(instruction.op2,Low,op2,rs);
  2394. emitter.Emit0(InstructionSet.opMOVSD);
  2395. UnmapTicket(rs);
  2396. UnmapTicket(rd);
  2397. ELSE
  2398. Spill(physicalRegisters.Mapped(RS));
  2399. Spill(physicalRegisters.Mapped(RD));
  2400. IF backend.cooperative THEN ap.spillable := TRUE END;
  2401. Spill(physicalRegisters.Mapped(RC));
  2402. rs := ReservePhysicalRegister(IntermediateCode.GeneralPurposeRegister,instruction.op1.type,RS,inPC);
  2403. rd := ReservePhysicalRegister(IntermediateCode.GeneralPurposeRegister,instruction.op1.type,RD,inPC);
  2404. rc := ReservePhysicalRegister(IntermediateCode.GeneralPurposeRegister,instruction.op1.type,RC,inPC);
  2405. MakeOperand(instruction.op1,Low,op1,rd);
  2406. MakeOperand(instruction.op2,Low,op2,rs);
  2407. IF (instruction.op1.mode = IntermediateCode.ModeRegister) & (instruction.op1.register = IntermediateCode.SP) & IntermediateCode.IsConstantInteger(instruction.op3, size) & (size >= 4096) THEN
  2408. (* special case on stack: copy downwards for possible stack allocation *)
  2409. IF size MOD 4 # 0 THEN
  2410. imm := Assembler.NewImm32(size-1);
  2411. emitter.Emit2(InstructionSet.opADD, opRDI, imm);
  2412. emitter.Emit2(InstructionSet.opADD, opRSI, imm);
  2413. imm := Assembler.NewImm32(size MOD 4);
  2414. emitter.Emit2(InstructionSet.opMOV, opRC, imm);
  2415. emitter.Emit0(InstructionSet.opSTD); (* copy down *)
  2416. emitter.EmitPrefix (InstructionSet.prfREP);
  2417. emitter.Emit0(InstructionSet.opMOVSB);
  2418. imm := Assembler.NewImm32(size DIV 4);
  2419. emitter.Emit2(InstructionSet.opMOV, opRC, imm);
  2420. emitter.EmitPrefix (InstructionSet.prfREP);
  2421. emitter.Emit0(InstructionSet.opMOVSD);
  2422. ELSE
  2423. imm := Assembler.NewImm32(size-4);
  2424. emitter.Emit2(InstructionSet.opADD, opRDI, imm);
  2425. emitter.Emit2(InstructionSet.opADD, opRSI, imm);
  2426. imm := Assembler.NewImm32(size DIV 4);
  2427. emitter.Emit2(InstructionSet.opMOV, opRC, imm);
  2428. emitter.Emit0(InstructionSet.opSTD); (* copy down *)
  2429. emitter.EmitPrefix (InstructionSet.prfREP);
  2430. emitter.Emit0(InstructionSet.opMOVSD);
  2431. END
  2432. ELSIF IntermediateCode.IsConstantInteger(instruction.op3, size) THEN
  2433. imm := Assembler.NewImm32(size DIV 4);
  2434. emitter.Emit2(InstructionSet.opMOV, opRC, imm);
  2435. emitter.Emit0(InstructionSet.opCLD); (* copy upwards *)
  2436. emitter.EmitPrefix (InstructionSet.prfREP);
  2437. emitter.Emit0(InstructionSet.opMOVSD);
  2438. IF size MOD 4 # 0 THEN
  2439. imm := Assembler.NewImm32(size MOD 4);
  2440. emitter.Emit2(InstructionSet.opMOV, opRC, imm);
  2441. emitter.EmitPrefix (InstructionSet.prfREP);
  2442. emitter.Emit0(InstructionSet.opMOVSB);
  2443. END;
  2444. (* this does not work in the kernel -- for whatever reasons *)
  2445. ELSIF (instruction.op1.mode = IntermediateCode.ModeRegister) & (instruction.op1.register = IntermediateCode.SP) THEN
  2446. MakeOperand(instruction.op3,Low,op3,rc);
  2447. t := TemporaryTicket(IntermediateCode.GeneralPurposeRegister, instruction.op1.type);
  2448. TicketToOperand(t, temp);
  2449. emitter.Emit2(InstructionSet.opADD, opRSI, opRC);
  2450. emitter.Emit2(InstructionSet.opADD, opRDI, opRC);
  2451. imm := Assembler.NewImm8(1);
  2452. emitter.Emit2(InstructionSet.opSUB, opRSI, imm);
  2453. emitter.Emit2(InstructionSet.opSUB, opRDI, imm);
  2454. emitter.Emit2(InstructionSet.opMOV, temp, opRC);
  2455. imm := Assembler.NewImm8(3);
  2456. emitter.Emit2(InstructionSet.opAND, opRC, imm);
  2457. emitter.Emit0(InstructionSet.opSTD); (* copy downwards *)
  2458. emitter.EmitPrefix (InstructionSet.prfREP);
  2459. emitter.Emit0(InstructionSet.opMOVSB);
  2460. imm := Assembler.NewImm8(2);
  2461. emitter.Emit2(InstructionSet.opMOV, opRC, temp);
  2462. emitter.Emit2(InstructionSet.opSHR, opRC, imm);
  2463. imm := Assembler.NewImm8(3);
  2464. emitter.Emit2(InstructionSet.opSUB, opRSI, imm);
  2465. emitter.Emit2(InstructionSet.opSUB, opRDI, imm);
  2466. emitter.EmitPrefix (InstructionSet.prfREP);
  2467. emitter.Emit0(InstructionSet.opMOVSD);
  2468. emitter.Emit0(InstructionSet.opCLD);
  2469. ELSE
  2470. MakeOperand(instruction.op3,Low,op3,rc);
  2471. t := TemporaryTicket(IntermediateCode.GeneralPurposeRegister, instruction.op1.type);
  2472. TicketToOperand(t, temp);
  2473. emitter.Emit2(InstructionSet.opMOV, temp, opRC);
  2474. imm := Assembler.NewImm8(3);
  2475. emitter.Emit2(InstructionSet.opAND, temp, imm);
  2476. imm := Assembler.NewImm8(2);
  2477. emitter.Emit2(InstructionSet.opSHR, opRC, imm);
  2478. emitter.Emit0(InstructionSet.opCLD); (* copy upwards *)
  2479. emitter.EmitPrefix (InstructionSet.prfREP);
  2480. emitter.Emit0(InstructionSet.opMOVSD);
  2481. emitter.Emit2(InstructionSet.opMOV, opRC, temp);
  2482. emitter.EmitPrefix (InstructionSet.prfREP);
  2483. emitter.Emit0(InstructionSet.opMOVSB);
  2484. END;
  2485. UnmapTicket(rs);
  2486. UnmapTicket(rd);
  2487. UnmapTicket(rc);
  2488. IF backend.cooperative THEN
  2489. UnSpill(ap);
  2490. ap.spillable := FALSE;
  2491. END;
  2492. END;
  2493. END EmitCopy;
  2494. PROCEDURE EmitFill(CONST instruction: IntermediateCode.Instruction; down: BOOLEAN);
  2495. VAR reg,sizeInBits,i: LONGINT;val, value, size, dest: Assembler.Operand;
  2496. op: LONGINT;
  2497. rd, rc: Ticket;
  2498. BEGIN
  2499. IF FALSE & (instruction.op2.mode = IntermediateCode.ModeImmediate) & (instruction.op2.symbol.name = "") & (instruction.op2.intValue < 5) THEN
  2500. sizeInBits := instruction.op3.type.sizeInBits;
  2501. IF sizeInBits = IntermediateCode.Bits8 THEN value := opAL;
  2502. ELSIF sizeInBits = IntermediateCode.Bits16 THEN value := opAX;
  2503. ELSIF sizeInBits = IntermediateCode.Bits32 THEN value := opEAX;
  2504. ELSE HALT(200)
  2505. END;
  2506. MakeOperand(instruction.op1,Low,dest,NIL);
  2507. IF instruction.op1.mode = IntermediateCode.ModeRegister THEN reg := dest.register
  2508. ELSE emitter.Emit2(InstructionSet.opMOV,opEDX,dest); reg := EDX;
  2509. END;
  2510. IF (instruction.op3.mode = IntermediateCode.ModeImmediate) & (instruction.op3.type.form IN IntermediateCode.Integer) & (instruction.op3.intValue = 0) THEN
  2511. emitter.Emit2(InstructionSet.opXOR,opEAX,opEAX);
  2512. ELSE
  2513. MakeOperand(instruction.op3,Low,value,NIL);
  2514. END;
  2515. FOR i := 0 TO SHORT(instruction.op2.intValue)-1 DO
  2516. IF down THEN
  2517. Assembler.InitMem(dest,SHORT(SHORT(sizeInBits DIV 8)),reg,-i*sizeInBits DIV 8);
  2518. ELSE
  2519. Assembler.InitMem(dest,SHORT(SHORT(sizeInBits DIV 8 )),reg,i*sizeInBits DIV 8);
  2520. END;
  2521. emitter.Emit2(InstructionSet.opMOV,dest,value);
  2522. END;
  2523. ELSE
  2524. Spill(physicalRegisters.Mapped(RD));
  2525. IF backend.cooperative THEN ap.spillable := TRUE END;
  2526. Spill(physicalRegisters.Mapped(RC));
  2527. rd := ReservePhysicalRegister(IntermediateCode.GeneralPurposeRegister,instruction.op1.type,RD,inPC);
  2528. rc := ReservePhysicalRegister(IntermediateCode.GeneralPurposeRegister,instruction.op1.type,RC,inPC);
  2529. MakeOperand(instruction.op1,Low,dest,rd);
  2530. MakeOperand(instruction.op2,Low,size,rc);
  2531. MakeOperand(instruction.op3,Low,value,NIL);
  2532. (*
  2533. emitter.Emit2(InstructionSet.opMOV,opRDI, op1[Low]);
  2534. emitter.Emit2(InstructionSet.opMOV,opRC, op3[Low]);
  2535. *)
  2536. CASE instruction.op3.type.sizeInBits OF
  2537. IntermediateCode.Bits8: val := opAL; op := InstructionSet.opSTOSB;
  2538. |IntermediateCode.Bits16: val := opAX; op := InstructionSet.opSTOSW;
  2539. |IntermediateCode.Bits32: val := opEAX; op := InstructionSet.opSTOSD;
  2540. ELSE Halt("only supported for upto 32 bit integers ");
  2541. END;
  2542. IF (instruction.op3.mode = IntermediateCode.ModeImmediate) & (instruction.op3.type.form IN IntermediateCode.Integer) & (instruction.op3.intValue = 0) THEN
  2543. emitter.Emit2(InstructionSet.opXOR,opEAX,opEAX);
  2544. ELSE
  2545. emitter.Emit2(InstructionSet.opMOV,val,value);
  2546. END;
  2547. IF down THEN
  2548. emitter.Emit0(InstructionSet.opSTD); (* fill downwards *)
  2549. ELSE
  2550. emitter.Emit0(InstructionSet.opCLD); (* fill upwards *)
  2551. END;
  2552. emitter.EmitPrefix (InstructionSet.prfREP);
  2553. emitter.Emit0(op);
  2554. IF down THEN (* needed as calls to windows crash otherwise *)
  2555. emitter.Emit0(InstructionSet.opCLD);
  2556. END;
  2557. UnmapTicket(rc);
  2558. IF backend.cooperative THEN
  2559. UnSpill(ap);
  2560. ap.spillable := FALSE;
  2561. END;
  2562. END;
  2563. END EmitFill;
  2564. PROCEDURE EmitBr (CONST instruction: IntermediateCode.Instruction);
  2565. VAR dest,destPC,offset: LONGINT; target: Assembler.Operand;hit,fail: LONGINT; reverse: BOOLEAN;
  2566. (* jump operands *) left,right,temp: Assembler.Operand;
  2567. failOp: Assembler.Operand; failPC: LONGINT;
  2568. PROCEDURE JmpDest(brop: LONGINT);
  2569. BEGIN
  2570. IF instruction.op1.mode = IntermediateCode.ModeImmediate THEN
  2571. IF instruction.op1.symbol.name = in.name THEN
  2572. dest := (instruction.op1.symbolOffset); (* this is the offset in the in-data section (intermediate code), it is not byte- *)
  2573. destPC := (in.instructions[dest].pc );
  2574. offset := destPC - (out.pc );
  2575. IF dest > inPC THEN (* forward jump *)
  2576. Assembler.InitOffset32(target,0);
  2577. Assembler.SetSymbol(target,instruction.op1.symbol.name,instruction.op1.symbol.fingerprint,instruction.op1.symbolOffset,instruction.op1.offset);
  2578. emitter.Emit1(brop,target);
  2579. ELSIF ABS(offset) <= 126 THEN
  2580. Assembler.InitOffset8(target,destPC);
  2581. emitter.Emit1(brop,target);
  2582. ELSE
  2583. Assembler.InitOffset32(target,destPC);
  2584. emitter.Emit1(brop,target);
  2585. END;
  2586. ELSIF cpuBits = 64 THEN
  2587. MakeOperand(instruction.op1,Low,target,NIL);
  2588. emitter.Emit1(brop,target);
  2589. ELSE
  2590. Assembler.InitOffset32(target,instruction.op1.intValue);
  2591. Assembler.SetSymbol(target,instruction.op1.symbol.name,instruction.op1.symbol.fingerprint,instruction.op1.symbolOffset,instruction.op1.offset);
  2592. emitter.Emit1(brop,target);
  2593. END;
  2594. ELSE
  2595. MakeOperand(instruction.op1,Low,target,NIL);
  2596. emitter.Emit1(brop,target);
  2597. END;
  2598. END JmpDest;
  2599. PROCEDURE CmpFloat;
  2600. BEGIN
  2601. IF backend.forceFPU THEN
  2602. MakeOperand(instruction.op2,Low,left,NIL);
  2603. emitter.Emit1(InstructionSet.opFLD,left); INC(fpStackPointer);
  2604. MakeOperand(instruction.op3,Low,right,NIL);
  2605. emitter.Emit1(InstructionSet.opFCOMP,right); DEC(fpStackPointer);
  2606. emitter.Emit1(InstructionSet.opFNSTSW,opAX);
  2607. emitter.Emit0(InstructionSet.opSAHF);
  2608. ELSE
  2609. MakeRegister(instruction.op2,Low,left);
  2610. MakeOperand(instruction.op3,Low,right,NIL);
  2611. IF instruction.op2.type.sizeInBits = 32 THEN
  2612. emitter.Emit2(InstructionSet.opCOMISS, left, right);
  2613. ELSE
  2614. emitter.Emit2(InstructionSet.opCOMISD, left, right);
  2615. END
  2616. END;
  2617. END CmpFloat;
  2618. PROCEDURE Cmp(part: LONGINT; VAR reverse: BOOLEAN);
  2619. VAR type: IntermediateCode.Type; left,right: Assembler.Operand;
  2620. BEGIN
  2621. IF (instruction.op2.mode = IntermediateCode.ModeImmediate) & (instruction.op3.mode = IntermediateCode.ModeImmediate) THEN
  2622. reverse := FALSE;
  2623. GetPartType(instruction.op2.type,part,type);
  2624. GetTemporaryRegister(type,temp);
  2625. MakeOperand(instruction.op2,part,left,NIL);
  2626. MakeOperand(instruction.op3,part,right,NIL);
  2627. Move(temp,left, type);
  2628. left := temp;
  2629. ELSIF instruction.op2.mode = IntermediateCode.ModeImmediate THEN
  2630. reverse := TRUE;
  2631. MakeOperand(instruction.op2,part,right,NIL);
  2632. MakeOperand(instruction.op3,part,left,NIL);
  2633. ELSIF IsMemoryOperand(instruction.op2,part) & IsMemoryOperand(instruction.op3,part) THEN
  2634. reverse := FALSE;
  2635. GetPartType(instruction.op2.type,part,type);
  2636. GetTemporaryRegister(type,temp);
  2637. MakeOperand(instruction.op2,part,left,NIL);
  2638. MakeOperand(instruction.op3,part,right,NIL);
  2639. Move(temp,right,type);
  2640. right := temp;
  2641. ELSE
  2642. reverse := FALSE;
  2643. MakeOperand(instruction.op2,part,left,NIL);
  2644. MakeOperand(instruction.op3,part,right,NIL);
  2645. END;
  2646. emitter.Emit2(InstructionSet.opCMP,left,right);
  2647. END Cmp;
  2648. BEGIN
  2649. IF (instruction.op1.symbol.name = in.name) & (instruction.op1.symbolOffset = inPC +1) THEN (* jump to next instruction can be ignored *)
  2650. IF dump # NIL THEN dump.String("jump to next instruction ignored"); dump.Ln END;
  2651. RETURN
  2652. END;
  2653. failPC := 0;
  2654. IF instruction.opcode = IntermediateCode.br THEN
  2655. hit := InstructionSet.opJMP
  2656. ELSIF instruction.op2.type.form = IntermediateCode.Float THEN
  2657. CmpFloat;
  2658. CASE instruction.opcode OF
  2659. IntermediateCode.breq: hit := InstructionSet.opJE;
  2660. |IntermediateCode.brne:hit := InstructionSet.opJNE;
  2661. |IntermediateCode.brge: hit := InstructionSet.opJAE
  2662. |IntermediateCode.brlt: hit := InstructionSet.opJB
  2663. END;
  2664. ELSE
  2665. IF ~IsComplex(instruction.op2) THEN
  2666. Cmp(Low,reverse);
  2667. CASE instruction.opcode OF
  2668. IntermediateCode.breq: hit := InstructionSet.opJE;
  2669. |IntermediateCode.brne: hit := InstructionSet.opJNE;
  2670. |IntermediateCode.brge:
  2671. IF instruction.op2.type.form = IntermediateCode.SignedInteger THEN
  2672. IF reverse THEN hit := InstructionSet.opJLE ELSE hit := InstructionSet.opJGE END;
  2673. ELSIF instruction.op2.type.form = IntermediateCode.UnsignedInteger THEN
  2674. IF reverse THEN hit := InstructionSet.opJBE ELSE hit := InstructionSet.opJAE END;
  2675. END;
  2676. |IntermediateCode.brlt:
  2677. IF instruction.op2.type.form = IntermediateCode.SignedInteger THEN
  2678. IF reverse THEN hit := InstructionSet.opJG ELSE hit := InstructionSet.opJL END;
  2679. ELSIF instruction.op2.type.form = IntermediateCode.UnsignedInteger THEN
  2680. IF reverse THEN hit := InstructionSet.opJA ELSE hit := InstructionSet.opJB END;
  2681. END;
  2682. END;
  2683. ELSE
  2684. Cmp(High,reverse);
  2685. CASE instruction.opcode OF
  2686. IntermediateCode.breq: hit := 0; fail := InstructionSet.opJNE;
  2687. |IntermediateCode.brne: hit := InstructionSet.opJNE; fail := 0;
  2688. |IntermediateCode.brge:
  2689. IF instruction.op2.type.form = IntermediateCode.SignedInteger THEN
  2690. IF reverse THEN hit := InstructionSet.opJL; fail := InstructionSet.opJG ELSE hit := InstructionSet.opJG; fail := InstructionSet.opJL END;
  2691. ELSIF instruction.op2.type.form = IntermediateCode.UnsignedInteger THEN
  2692. IF reverse THEN hit := InstructionSet.opJB; fail := InstructionSet.opJA ELSE hit := InstructionSet.opJA; fail := InstructionSet.opJB END;
  2693. END;
  2694. |IntermediateCode.brlt:
  2695. IF instruction.op2.type.form = IntermediateCode.SignedInteger THEN
  2696. IF reverse THEN hit := InstructionSet.opJG; fail := InstructionSet.opJL ELSE hit := InstructionSet.opJL; fail := InstructionSet.opJG END;
  2697. ELSIF instruction.op2.type.form = IntermediateCode.UnsignedInteger THEN
  2698. IF reverse THEN hit := InstructionSet.opJA; fail := InstructionSet.opJB ELSE hit := InstructionSet.opJB; fail := InstructionSet.opJA END;
  2699. END;
  2700. END;
  2701. IF hit # 0 THEN JmpDest(hit) END;
  2702. IF fail # 0 THEN
  2703. failPC := out.pc; (* to avoid potential value overflow problem, will be patched anyway *)
  2704. Assembler.InitOffset8(failOp,failPC );
  2705. emitter.Emit1(fail,failOp);
  2706. failPC := failOp.pc;
  2707. END;
  2708. Cmp(Low,reverse);
  2709. CASE instruction.opcode OF
  2710. IntermediateCode.breq: hit := InstructionSet.opJE
  2711. |IntermediateCode.brne: hit := InstructionSet.opJNE
  2712. |IntermediateCode.brge:
  2713. IF reverse THEN hit := InstructionSet.opJBE ELSE hit := InstructionSet.opJAE END;
  2714. |IntermediateCode.brlt:
  2715. IF reverse THEN hit := InstructionSet.opJA ELSE hit := InstructionSet.opJB END;
  2716. END;
  2717. END;
  2718. END;
  2719. JmpDest(hit);
  2720. IF failPC > 0 THEN out.PutByteAt(failPC,(out.pc-failPC)-1); END;
  2721. END EmitBr;
  2722. PROCEDURE EmitPush(CONST vop: IntermediateCode.Operand; part: LONGINT);
  2723. VAR index: LONGINT; type,cpuType: IntermediateCode.Type; op1: Assembler.Operand; ra: Ticket;
  2724. BEGIN
  2725. GetPartType(vop.type,part,type);
  2726. ASSERT(type.form IN IntermediateCode.Integer);
  2727. IF vop.mode = IntermediateCode.ModeImmediate THEN (* may not push 16 bit immediate: strange instruction in 32 / 64 bit mode *)
  2728. GetImmediate(vop,part,op1,TRUE);
  2729. emitter.Emit1(InstructionSet.opPUSH,op1);
  2730. ELSIF (type.sizeInBits = cpuBits) THEN
  2731. MakeOperand(vop,part,op1,NIL);
  2732. emitter.Emit1(InstructionSet.opPUSH,op1);
  2733. ELSE
  2734. ASSERT(type.sizeInBits < cpuBits);
  2735. MakeOperand(vop,part,op1,NIL);
  2736. IF Assembler.IsRegisterOperand(op1) & ~((cpuBits=32) & (type.sizeInBits=8) & (op1.register >= AH)) THEN
  2737. index := op1.register MOD 32 + opRA.register;
  2738. emitter.Emit1(InstructionSet.opPUSH, registerOperands[index]);
  2739. ELSE
  2740. WHILE physicalRegisters.Mapped(opRA.register) # free DO Spill(physicalRegisters.Mapped(opRA.register)) END;
  2741. IntermediateCode.InitType(cpuType,IntermediateCode.SignedInteger,SHORT(cpuBits));
  2742. ra := ReservePhysicalRegister(IntermediateCode.GeneralPurposeRegister,cpuType,opRA.register,inPC);
  2743. CASE type.sizeInBits OF
  2744. 8: index := AL
  2745. |16: index := AX
  2746. |32: index := EAX
  2747. |64: index := RAX
  2748. END;
  2749. emitter.Emit2(InstructionSet.opMOV,registerOperands[index],op1);
  2750. emitter.Emit1(InstructionSet.opPUSH,opRA);
  2751. UnmapTicket(ra);
  2752. END;
  2753. END;
  2754. END EmitPush;
  2755. PROCEDURE EmitPop(CONST vop: IntermediateCode.Operand; part: LONGINT);
  2756. VAR index: LONGINT; type,cpuType: IntermediateCode.Type; op1: Assembler.Operand; ra: Ticket;
  2757. BEGIN
  2758. GetPartType(vop.type,part,type);
  2759. ASSERT(type.form IN IntermediateCode.Integer);
  2760. IF (type.sizeInBits = cpuBits) THEN
  2761. MakeOperand(vop,part,op1,NIL);
  2762. emitter.Emit1(InstructionSet.opPOP,op1);
  2763. ELSE
  2764. ASSERT(type.sizeInBits < cpuBits);
  2765. MakeOperand(vop,part,op1,NIL);
  2766. IF Assembler.IsRegisterOperand(op1) & ~((cpuBits=32) & (type.sizeInBits=8) & (op1.register >= AH)) THEN
  2767. index := op1.register MOD 32 + opRA.register;
  2768. emitter.Emit1(InstructionSet.opPOP, registerOperands[index]);
  2769. ELSE
  2770. WHILE physicalRegisters.Mapped(opRA.register) # free DO Spill(physicalRegisters.Mapped(opRA.register)) END;
  2771. IntermediateCode.InitType(cpuType, IntermediateCode.SignedInteger, SHORT(cpuBits));
  2772. ra := ReservePhysicalRegister(IntermediateCode.GeneralPurposeRegister,cpuType,opRA.register,inPC);
  2773. emitter.Emit1(InstructionSet.opPOP,opRA);
  2774. CASE type.sizeInBits OF
  2775. 8: index := AL
  2776. |16: index := AX
  2777. |32: index := EAX
  2778. |64: index := RAX
  2779. END;
  2780. emitter.Emit2(InstructionSet.opMOV, op1, registerOperands[index]);
  2781. UnmapTicket(ra);
  2782. END;
  2783. END;
  2784. END EmitPop;
  2785. PROCEDURE EmitPushFloat(CONST vop: IntermediateCode.Operand);
  2786. VAR sizeInBytes,length: LONGINT; memop: Assembler.Operand; op: Assembler.Operand;
  2787. BEGIN
  2788. MakeOperand(vop,Low,op,NIL);
  2789. length := vop.type.length;
  2790. IF (vop.mode = IntermediateCode.ModeMemory) & (vop.type.sizeInBits*length =cpuBits) THEN
  2791. emitter.Emit1(InstructionSet.opPUSH,op);
  2792. ELSE
  2793. sizeInBytes := vop.type.sizeInBits DIV 8;
  2794. length := vop.type.length;
  2795. IF sizeInBytes * length * 8 < cpuBits THEN
  2796. AllocateStack(cpuBits DIV 8);
  2797. ELSE
  2798. AllocateStack(sizeInBytes*length);
  2799. END;
  2800. Assembler.InitMem(memop, SHORTINT(sizeInBytes*length),SP,0);
  2801. IF backend.forceFPU THEN
  2802. emitter.Emit1(InstructionSet.opFLD,op); INC(fpStackPointer);
  2803. emitter.Emit1(InstructionSet.opFSTP,memop); DEC(fpStackPointer);
  2804. ELSE
  2805. Move(memop, op, vop.type)
  2806. END
  2807. END;
  2808. END EmitPushFloat;
  2809. PROCEDURE EmitPopFloat(CONST vop: IntermediateCode.Operand);
  2810. VAR sizeInBytes,length: LONGINT; memop: Assembler.Operand; op: Assembler.Operand;
  2811. BEGIN
  2812. sizeInBytes := vop.type.sizeInBits DIV 8;
  2813. length := vop.type.length;
  2814. IF (vop.mode = IntermediateCode.ModeMemory) & (vop.type.sizeInBits*length =cpuBits) THEN
  2815. MakeOperand(vop,Low,op,NIL);
  2816. emitter.Emit1(InstructionSet.opPOP,op);
  2817. ELSE
  2818. Assembler.InitMem(memop, SHORTINT(sizeInBytes*length),SP,0);
  2819. IF backend.forceFPU THEN
  2820. emitter.Emit1(InstructionSet.opFLD,memop);
  2821. INC(fpStackPointer);
  2822. MakeOperand(vop,Low,op,NIL);
  2823. emitter.Emit1(InstructionSet.opFSTP,op);
  2824. DEC(fpStackPointer);
  2825. ASSERT(sizeInBytes > 0);
  2826. ELSE
  2827. MakeOperand(vop,Low,op,NIL);
  2828. Move(op, memop, vop.type)
  2829. END;
  2830. IF sizeInBytes * length * 8 < cpuBits THEN
  2831. AllocateStack(-cpuBits DIV 8);
  2832. ELSE
  2833. AllocateStack(-sizeInBytes*length);
  2834. END;
  2835. END;
  2836. END EmitPopFloat;
  2837. PROCEDURE EmitNeg(CONST instruction: IntermediateCode.Instruction);
  2838. VAR opLow,opHigh: Assembler.Operand; minusOne: Assembler.Operand; ticketLow,ticketHigh: Ticket;
  2839. BEGIN
  2840. IF IsComplex(instruction.op1) THEN
  2841. PrepareOp2(instruction,High,opHigh,ticketHigh);
  2842. PrepareOp2(instruction,Low,opLow,ticketLow);
  2843. emitter.Emit1(InstructionSet.opNOT,opHigh);
  2844. emitter.Emit1(InstructionSet.opNEG,opLow);
  2845. Assembler.InitImm8(minusOne,-1);
  2846. emitter.Emit2(InstructionSet.opSBB,opHigh,minusOne);
  2847. FinishOp(instruction.op1,High,opHigh,ticketHigh);
  2848. FinishOp(instruction.op1,Low,opLow,ticketLow);
  2849. ELSE
  2850. EmitArithmetic2(instruction,Low,InstructionSet.opNEG);
  2851. END;
  2852. END EmitNeg;
  2853. PROCEDURE EmitNegXMM(CONST instruction: IntermediateCode.Instruction);
  2854. VAR temp, op: Assembler.Operand; ticket: Ticket;
  2855. BEGIN
  2856. PrepareOp2(instruction, Low, op, ticket);
  2857. GetTemporaryRegister(instruction.op1.type,temp);
  2858. IF instruction.op1.type.sizeInBits = 32 THEN
  2859. emitter.Emit2(InstructionSet.opXORPS, temp, temp);
  2860. emitter.Emit2(InstructionSet.opSUBPS, temp, op);
  2861. emitter.Emit2(InstructionSet.opMOVAPS, op, temp);
  2862. ELSE
  2863. emitter.Emit2(InstructionSet.opXORPD, temp, temp);
  2864. emitter.Emit2(InstructionSet.opSUBPD, temp, op);
  2865. emitter.Emit2(InstructionSet.opMOVAPS, op, temp);
  2866. END;
  2867. FinishOp(instruction.op1, Low, op, ticket);
  2868. END EmitNegXMM;
  2869. PROCEDURE EmitAbs(CONST instruction: IntermediateCode.Instruction);
  2870. VAR op1,op2: Assembler.Operand; source,imm: Assembler.Operand; eax: Ticket;
  2871. BEGIN
  2872. Assert(~IsComplex(instruction.op1),"complex Abs not supported");
  2873. IF instruction.op1.type.form = IntermediateCode.SignedInteger THEN
  2874. Spill(physicalRegisters.Mapped(EAX));
  2875. eax := ReservePhysicalRegister(IntermediateCode.GeneralPurposeRegister,IntermediateCode.int32,EAX,inPC);
  2876. MakeOperand(instruction.op1,Low,op1,NIL);
  2877. MakeOperand(instruction.op2,Low,op2,NIL);
  2878. CASE instruction.op1.type.sizeInBits OF
  2879. | IntermediateCode.Bits8: imm := Assembler.NewImm8 (7); source := opAL;
  2880. | IntermediateCode.Bits16: imm := Assembler.NewImm8 (15); source := opAX;
  2881. | IntermediateCode.Bits32: imm := Assembler.NewImm8 (31); source := opEAX;
  2882. | IntermediateCode.Bits64: imm := Assembler.NewImm8 (63); source := registerOperands[RAX];
  2883. END;
  2884. emitter.Emit2 (InstructionSet.opMOV, source,op2);
  2885. emitter.Emit2 (InstructionSet.opMOV, op1,source);
  2886. emitter.Emit2 (InstructionSet.opSAR, source, imm);
  2887. emitter.Emit2 (InstructionSet.opXOR, op1, source);
  2888. emitter.Emit2 (InstructionSet.opSUB, op1, source);
  2889. UnmapTicket(eax);
  2890. ELSE Halt("Abs does not make sense on unsigned integer")
  2891. END;
  2892. END EmitAbs;
  2893. PROCEDURE EmitAbsXMM(CONST instruction: IntermediateCode.Instruction);
  2894. VAR temp, op: Assembler.Operand; ticket: Ticket;
  2895. BEGIN
  2896. PrepareOp2(instruction, Low, op, ticket);
  2897. GetTemporaryRegister(instruction.op1.type,temp);
  2898. IF instruction.op1.type.sizeInBits = 32 THEN
  2899. emitter.Emit2(InstructionSet.opXORPS, temp, temp);
  2900. emitter.Emit2(InstructionSet.opSUBPS, temp, op);
  2901. emitter.Emit2(InstructionSet.opMAXPS, op, temp);
  2902. ELSE
  2903. emitter.Emit2(InstructionSet.opXORPD, temp, temp);
  2904. emitter.Emit2(InstructionSet.opSUBPD, temp, op);
  2905. emitter.Emit2(InstructionSet.opMAXPD, op, temp);
  2906. END;
  2907. FinishOp(instruction.op1, Low, op, ticket);
  2908. END EmitAbsXMM;
  2909. PROCEDURE EmitTrap(CONST instruction: IntermediateCode.Instruction);
  2910. VAR operand: Assembler.Operand;
  2911. BEGIN
  2912. IF instruction.op1.intValue < 80H THEN
  2913. operand := Assembler.NewImm8(instruction.op1.intValue);
  2914. ELSE
  2915. operand := Assembler.NewImm32(instruction.op1.intValue);
  2916. END;
  2917. emitter.Emit1(InstructionSet.opPUSH, operand);
  2918. emitter.Emit0(InstructionSet.opINT3);
  2919. END EmitTrap;
  2920. PROCEDURE EmitAsm(CONST instruction: IntermediateCode.Instruction);
  2921. VAR reader: Streams.StringReader; procedure: SyntaxTree.Procedure; scope: SyntaxTree.Scope;
  2922. len: LONGINT; symbol: SyntaxTree.Symbol; assembler: Assembler.Assembly;
  2923. inr, outr: IntermediateCode.Rules;
  2924. string: SyntaxTree.SourceCode;
  2925. i: LONGINT;
  2926. reg, dest: Assembler.Operand;
  2927. map: Assembler.RegisterMap;
  2928. register: LONGINT;
  2929. ticket: Ticket;
  2930. BEGIN
  2931. IF instruction.op2.mode = IntermediateCode.ModeRule THEN inr := instruction.op2.rule ELSE inr := NIL END;
  2932. IF instruction.op3.mode = IntermediateCode.ModeRule THEN outr := instruction.op3.rule ELSE outr := NIL END;
  2933. string := instruction.op1.string;
  2934. NEW(map);
  2935. IF inr # NIL THEN
  2936. FOR i := 0 TO LEN(inr)-1 DO
  2937. MakeRegister(inr[i], 0, reg);
  2938. ASSERT(map.Find(inr[i].string^) < 0);
  2939. map.Add(inr[i].string, reg.register)
  2940. END;
  2941. END;
  2942. IF outr # NIL THEN
  2943. FOR i := 0 TO LEN(outr)-1 DO
  2944. IF (map.Find(outr[i].string^) < 0) THEN
  2945. GetTemporaryRegister(outr[i].type,reg);
  2946. map.Add(outr[i].string, reg.register)
  2947. END;
  2948. END;
  2949. END;
  2950. len := Strings.Length(string^);
  2951. NEW(reader,len);
  2952. reader.Set(string^);
  2953. symbol := in.symbol;
  2954. procedure := symbol(SyntaxTree.Procedure);
  2955. scope := procedure.procedureScope;
  2956. NEW(assembler,diagnostics,emitter);
  2957. assembler.useLineNumbers := Compiler.UseLineNumbers IN backend.flags;
  2958. assembler.Assemble(reader,instruction.textPosition,scope,in,in,module,procedure.access * SyntaxTree.Public # {}, procedure.isInline, map) ;
  2959. error := error OR assembler.error;
  2960. IF outr # NIL THEN
  2961. FOR i := 0 TO LEN(outr)-1 DO
  2962. IF outr[i].mode # IntermediateCode.Undefined THEN
  2963. register := map.Find(outr[i].string^);
  2964. ticket := physicalRegisters.Mapped(register);
  2965. IF ticket.lastuse = inPC THEN UnmapTicket(ticket); physicalRegisters.AllocationHint(register) END; (* try to reuse register here *)
  2966. Assembler.InitRegister(reg, register);
  2967. MakeOperand(outr[i], Low, dest, NIL);
  2968. Move( dest, reg,outr[i].type)
  2969. END;
  2970. END;
  2971. END;
  2972. (*
  2973. IntermediateCode.SetString(instruction.op1, string);
  2974. *)
  2975. END EmitAsm;
  2976. END CodeGeneratorAMD64;
  2977. BackendAMD64= OBJECT (IntermediateBackend.IntermediateBackend)
  2978. VAR
  2979. cg: CodeGeneratorAMD64;
  2980. bits: LONGINT;
  2981. traceable: BOOLEAN;
  2982. forceFPU: BOOLEAN;
  2983. winAPIRegisters: ARRAY 4 OF LONGINT;
  2984. cRegisters: ARRAY 6 OF LONGINT;
  2985. PROCEDURE &InitBackendAMD64;
  2986. BEGIN
  2987. InitIntermediateBackend;
  2988. bits := 32;
  2989. forceFPU := FALSE;
  2990. winAPIRegisters[0] := RCX - RAX;
  2991. winAPIRegisters[1] := RDX - RAX;
  2992. winAPIRegisters[2] := R8 - RAX;
  2993. winAPIRegisters[3] := R9 - RAX;
  2994. cRegisters[0] := RDI - RAX;
  2995. cRegisters[1] := RSI - RAX;
  2996. cRegisters[2] := RDX - RAX;
  2997. cRegisters[3] := RCX - RAX;
  2998. cRegisters[4] := R8 - RAX;
  2999. cRegisters[5] := R9 - RAX;
  3000. SetName("AMD");
  3001. END InitBackendAMD64;
  3002. PROCEDURE Initialize*(diagnostics: Diagnostics.Diagnostics; log: Streams.Writer; flags: SET; checker: SemanticChecker.Checker; system: Global.System);
  3003. BEGIN
  3004. Initialize^(diagnostics,log, flags,checker,system); NEW(cg, runtimeModuleName, diagnostics, SELF);
  3005. END Initialize;
  3006. PROCEDURE GetSystem*(): Global.System;
  3007. VAR system: Global.System;
  3008. PROCEDURE AddRegister(CONST name: Scanner.IdentifierString; val: LONGINT);
  3009. BEGIN
  3010. Global.NewConstant(name,val,system.shortintType,system.systemScope)
  3011. END AddRegister;
  3012. PROCEDURE AddRegisters;
  3013. BEGIN
  3014. (* system constants *)
  3015. AddRegister("EAX",InstructionSet.regEAX); AddRegister("ECX", InstructionSet.regECX);
  3016. AddRegister( "EDX", InstructionSet.regEDX); AddRegister( "EBX", InstructionSet.regEBX);
  3017. AddRegister( "ESP", InstructionSet.regESP); AddRegister( "EBP", InstructionSet.regEBP);
  3018. AddRegister( "ESI", InstructionSet.regESI); AddRegister( "EDI", InstructionSet.regEDI);
  3019. AddRegister( "AX", InstructionSet.regAX); AddRegister( "CX", InstructionSet.regCX);
  3020. AddRegister( "DX", InstructionSet.regDX); AddRegister( "BX", InstructionSet.regBX);
  3021. AddRegister( "AL", InstructionSet.regAL); AddRegister( "CL", InstructionSet.regCL);
  3022. AddRegister( "DL", InstructionSet.regDL); AddRegister( "BL", InstructionSet.regBL);
  3023. AddRegister( "AH", InstructionSet.regAH); AddRegister( "CH", InstructionSet.regCH);
  3024. AddRegister( "DH", InstructionSet.regDH); AddRegister( "BH", InstructionSet.regBH);
  3025. AddRegister( "RAX", InstructionSet.regRAX); AddRegister( "RCX", InstructionSet.regRCX);
  3026. AddRegister( "RDX", InstructionSet.regRDX); AddRegister( "RBX", InstructionSet.regRBX);
  3027. AddRegister( "RSP", InstructionSet.regRSP); AddRegister( "RBP", InstructionSet.regRBP);
  3028. AddRegister( "RSI", InstructionSet.regRSI); AddRegister( "RDI", InstructionSet.regRDI);
  3029. AddRegister( "R8", InstructionSet.regR8); AddRegister( "R9", InstructionSet.regR9);
  3030. AddRegister( "R10", InstructionSet.regR10); AddRegister( "R11", InstructionSet.regR11);
  3031. AddRegister( "R12", InstructionSet.regR12); AddRegister( "R13", InstructionSet.regR13);
  3032. AddRegister( "R14", InstructionSet.regR14); AddRegister( "R15", InstructionSet.regR15);
  3033. AddRegister( "R8D", InstructionSet.regR8D); AddRegister( "R9D", InstructionSet.regR9D);
  3034. AddRegister( "R10D", InstructionSet.regR10D); AddRegister( "R11D", InstructionSet.regR11D);
  3035. AddRegister( "R12D", InstructionSet.regR12D); AddRegister( "R13D", InstructionSet.regR13D);
  3036. AddRegister( "R14D", InstructionSet.regR14D); AddRegister( "R15D", InstructionSet.regR15D);
  3037. AddRegister( "R8W", InstructionSet.regR8W); AddRegister( "R9W", InstructionSet.regR9W);
  3038. AddRegister( "R10W", InstructionSet.regR10W); AddRegister( "R11W", InstructionSet.regR11W);
  3039. AddRegister( "R12W", InstructionSet.regR12W); AddRegister( "R13W", InstructionSet.regR13W);
  3040. AddRegister( "R14W", InstructionSet.regR14W); AddRegister( "R15W", InstructionSet.regR15W);
  3041. AddRegister( "R8B", InstructionSet.regR8B); AddRegister( "R9B", InstructionSet.regR9B);
  3042. AddRegister( "R10B", InstructionSet.regR10B); AddRegister( "R11B", InstructionSet.regR11B);
  3043. AddRegister( "R12B", InstructionSet.regR12B); AddRegister( "R13B", InstructionSet.regR13B);
  3044. AddRegister( "R14B", InstructionSet.regR14B); AddRegister( "R15B", InstructionSet.regR15B);
  3045. END AddRegisters;
  3046. BEGIN
  3047. IF system = NIL THEN
  3048. IF bits=32 THEN
  3049. NEW(system,8,8,32, 8,32,32,32,64,cooperative);
  3050. Global.SetDefaultDeclarations(system,8);
  3051. Global.SetDefaultOperators(system);
  3052. ELSE
  3053. NEW(system,8,8,64,8,64,64,64,128,cooperative);
  3054. Global.SetDefaultDeclarations(system,8);
  3055. Global.SetDefaultOperators(system);
  3056. END;
  3057. system.SetRegisterPassCallback(CanPassInRegister);
  3058. AddRegisters
  3059. END;
  3060. RETURN system
  3061. END GetSystem;
  3062. (* return number of general purpose registery used as parameter register in calling convention *)
  3063. PROCEDURE NumberParameterRegisters*(callingConvention: SyntaxTree.CallingConvention): SIZE;
  3064. BEGIN
  3065. IF bits = 32 THEN
  3066. RETURN 0;
  3067. ELSE
  3068. CASE callingConvention OF
  3069. |SyntaxTree.WinAPICallingConvention: RETURN 4;
  3070. |SyntaxTree.CCallingConvention, SyntaxTree.DarwinCCallingConvention: RETURN 6;
  3071. ELSE
  3072. RETURN 0;
  3073. END;
  3074. END
  3075. END NumberParameterRegisters;
  3076. (* returns the following register (or part thereof)
  3077. 0: regRAX;
  3078. 1: regRCX;
  3079. 2: regRDX;
  3080. 3: regRBX;
  3081. 4: regRSP;
  3082. 5: regRBP;
  3083. 6: regRSI;
  3084. 7: regRDI;
  3085. 8 .. 15: regRx;
  3086. *)
  3087. PROCEDURE HardwareIntegerRegister(index: LONGINT; sizeInBits: LONGINT): LONGINT;
  3088. BEGIN
  3089. index := index MOD 32;
  3090. sizeInBits := sizeInBits DIV 8;
  3091. WHILE sizeInBits > 1 DO (* jump to register section that corresponds to the number of bits *)
  3092. INC(index,32);
  3093. sizeInBits := sizeInBits DIV 2;
  3094. END;
  3095. RETURN index
  3096. END HardwareIntegerRegister;
  3097. PROCEDURE HardwareFloatRegister(index: LONGINT; sizeInBits: LONGINT): LONGINT;
  3098. BEGIN
  3099. ASSERT((sizeInBits = 32) OR (sizeInBits = 64));
  3100. RETURN XMM0 + index;
  3101. END HardwareFloatRegister;
  3102. PROCEDURE ParameterRegister*(callingConvention: SyntaxTree.CallingConvention; type: IntermediateCode.Type; index: LONGINT): LONGINT;
  3103. VAR size: LONGINT;
  3104. BEGIN
  3105. IF type.form IN IntermediateCode.Integer THEN
  3106. CASE callingConvention OF
  3107. |SyntaxTree.WinAPICallingConvention: index := winAPIRegisters[index];
  3108. |SyntaxTree.CCallingConvention, SyntaxTree.DarwinCCallingConvention: index := cRegisters[index]
  3109. END;
  3110. RETURN HardwareIntegerRegister(RAX + index, type.sizeInBits)
  3111. ELSIF type.form = IntermediateCode.Float THEN
  3112. RETURN HardwareFloatRegister(index, type.sizeInBits)
  3113. ELSE
  3114. HALT(100);
  3115. END;
  3116. END ParameterRegister;
  3117. PROCEDURE SupportedInstruction*(CONST instruction: IntermediateCode.Instruction; VAR moduleName, procedureName: ARRAY OF CHAR): BOOLEAN;
  3118. BEGIN
  3119. RETURN cg.Supported(instruction,moduleName,procedureName);
  3120. END SupportedInstruction;
  3121. PROCEDURE GenerateBinary(module: Sections.Module; dump: Streams.Writer);
  3122. VAR
  3123. in: Sections.Section;
  3124. out: BinaryCode.Section;
  3125. name: Basic.SegmentedName;
  3126. procedure: SyntaxTree.Procedure;
  3127. i, j, initialSectionCount: LONGINT;
  3128. (* recompute fixup positions and assign binary sections *)
  3129. PROCEDURE PatchFixups(section: BinaryCode.Section);
  3130. VAR resolved: BinaryCode.Section; fixup: BinaryCode.Fixup; displacement,symbolOffset: LONGINT; in: IntermediateCode.Section;
  3131. symbol: Sections.Section;
  3132. BEGIN
  3133. fixup := section.fixupList.firstFixup;
  3134. WHILE fixup # NIL DO
  3135. symbol := module.allSections.FindByName(fixup.symbol.name);
  3136. IF (symbol # NIL) & (symbol(IntermediateCode.Section).resolved # NIL) THEN
  3137. resolved := symbol(IntermediateCode.Section).resolved(BinaryCode.Section);
  3138. in := symbol(IntermediateCode.Section);
  3139. symbolOffset := fixup.symbolOffset;
  3140. IF symbolOffset = in.pc THEN
  3141. displacement := resolved.pc
  3142. ELSIF (symbolOffset # 0) THEN
  3143. ASSERT(in.pc > symbolOffset);
  3144. displacement := in.instructions[symbolOffset].pc;
  3145. ELSE
  3146. displacement := 0;
  3147. END;
  3148. fixup.SetSymbol(fixup.symbol.name,fixup.symbol.fingerprint,0,fixup.displacement+displacement);
  3149. END;
  3150. fixup := fixup.nextFixup;
  3151. END;
  3152. END PatchFixups;
  3153. BEGIN
  3154. cg.SetModule(module);
  3155. FOR i := 0 TO module.allSections.Length() - 1 DO
  3156. in := module.allSections.GetSection(i);
  3157. IF in.type = Sections.InlineCodeSection THEN
  3158. name := in.name;
  3159. out := ResolvedSection(in(IntermediateCode.Section));
  3160. cg.Section(in(IntermediateCode.Section),out);
  3161. procedure := in.symbol(SyntaxTree.Procedure);
  3162. IF procedure.procedureScope.body.code # NIL THEN
  3163. procedure.procedureScope.body.code.SetBinaryCode(out.os.bits);
  3164. END;
  3165. END
  3166. END;
  3167. initialSectionCount := 0;
  3168. REPEAT
  3169. j := initialSectionCount;
  3170. initialSectionCount := module.allSections.Length() ;
  3171. FOR i := j TO initialSectionCount - 1 DO
  3172. in := module.allSections.GetSection(i);
  3173. IF (in.type # Sections.InlineCodeSection) & (in(IntermediateCode.Section).resolved = NIL) THEN
  3174. name := in.name;
  3175. out := ResolvedSection(in(IntermediateCode.Section));
  3176. cg.Section(in(IntermediateCode.Section),out);
  3177. IF out.os.type = Sections.VarSection THEN
  3178. IF out.pc = 1 THEN out.SetAlignment(FALSE,1)
  3179. ELSIF out.pc = 2 THEN out.SetAlignment(FALSE,2)
  3180. ELSIF (out.pc > 4) & (bits > 32) THEN out.SetAlignment(FALSE,8)
  3181. ELSIF (out.pc > 2) THEN out.SetAlignment(FALSE,4)
  3182. END;
  3183. ELSIF out.os.type = Sections.ConstSection THEN
  3184. out.SetAlignment(FALSE,bits DIV 8);
  3185. END;
  3186. END
  3187. END
  3188. UNTIL initialSectionCount = module.allSections.Length(); (* process remaining sections that have been added during traversal of sections *)
  3189. (*
  3190. FOR i := 0 TO module.allSections.Length() - 1 DO
  3191. in := module.allSections.GetSection(i);
  3192. IF in.kind = Sections.CaseTableKind THEN
  3193. IF in(IntermediateCode.Section).resolved = NIL THEN
  3194. out := ResolvedSection(in(IntermediateCode.Section));
  3195. cg.Section(in(IntermediateCode.Section),out);
  3196. END
  3197. END
  3198. END;
  3199. *)
  3200. FOR i := 0 TO module.allSections.Length() - 1 DO
  3201. in := module.allSections.GetSection(i);
  3202. PatchFixups(in(IntermediateCode.Section).resolved)
  3203. END;
  3204. (*
  3205. FOR i := 0 TO module.allSections.Length() - 1 DO
  3206. in := module.allSections.GetSection(i);
  3207. IF in.kind = Sections.CaseTableKind THEN
  3208. PatchFixups(in(IntermediateCode.Section).resolved)
  3209. END
  3210. END;
  3211. *)
  3212. IF cg.error THEN Error("",Basic.invalidPosition, Diagnostics.Invalid,"") END;
  3213. END GenerateBinary;
  3214. (* genasm *)
  3215. PROCEDURE ProcessIntermediateCodeModule*(intermediateCodeModule: Formats.GeneratedModule): Formats.GeneratedModule;
  3216. VAR
  3217. result: Formats.GeneratedModule;
  3218. BEGIN
  3219. ASSERT(intermediateCodeModule IS Sections.Module);
  3220. result := ProcessIntermediateCodeModule^(intermediateCodeModule);
  3221. IF ~error THEN
  3222. GenerateBinary(result(Sections.Module),dump);
  3223. IF dump # NIL THEN
  3224. dump.Ln; dump.Ln;
  3225. dump.String(";------------------ binary code -------------------"); dump.Ln;
  3226. IF (traceString="") OR (traceString="*") THEN
  3227. result.Dump(dump);
  3228. dump.Update
  3229. ELSE
  3230. Sections.DumpFiltered(dump, result(Sections.Module), traceString);
  3231. dump.Update;
  3232. END
  3233. END;
  3234. END;
  3235. RETURN result
  3236. FINALLY
  3237. IF dump # NIL THEN
  3238. dump.Ln; dump.Ln;
  3239. dump.String("; ------------------ rescued code (code generation trapped) -------------------"); dump.Ln;
  3240. IF (traceString="") OR (traceString="*") THEN
  3241. result.Dump(dump);
  3242. dump.Update
  3243. ELSE
  3244. Sections.DumpFiltered(dump, result(Sections.Module), traceString);
  3245. dump.Update;
  3246. END
  3247. END;
  3248. HALT(100); (* do not continue compiling after trap *)
  3249. RETURN result
  3250. END ProcessIntermediateCodeModule;
  3251. PROCEDURE FindPC*(x: SyntaxTree.Module; CONST sectionName: ARRAY OF CHAR; sectionOffset: LONGINT);
  3252. VAR
  3253. section: Sections.Section; binarySection: BinaryCode.Section; label: BinaryCode.LabelList; module: Formats.GeneratedModule;
  3254. i: LONGINT; pooledName: Basic.SegmentedName;
  3255. BEGIN
  3256. module := ProcessSyntaxTreeModule(x);
  3257. Basic.ToSegmentedName(sectionName, pooledName);
  3258. i := 0;
  3259. REPEAT
  3260. section := module(Sections.Module).allSections.GetSection(i);
  3261. INC(i);
  3262. UNTIL (i = module(Sections.Module).allSections.Length()) OR (section.name = pooledName);
  3263. IF section.name # pooledName THEN
  3264. Basic.Error(diagnostics, module.module.sourceName,Basic.invalidPosition, " could not locate pc");
  3265. ELSE
  3266. binarySection := section(IntermediateCode.Section).resolved;
  3267. IF binarySection # NIL THEN
  3268. label := binarySection.labels;
  3269. WHILE (label # NIL) & (label.offset >= sectionOffset) DO
  3270. label := label.prev;
  3271. END;
  3272. END;
  3273. IF label # NIL THEN
  3274. Basic.Information(diagnostics, module.module.sourceName,label.position, " pc position");
  3275. ELSE
  3276. Basic.Error(diagnostics, module.module.sourceName,Basic.invalidPosition, " could not locate pc");
  3277. END;
  3278. END;
  3279. END FindPC;
  3280. PROCEDURE CanPassInRegister*(type: SyntaxTree.Type): BOOLEAN;
  3281. VAR length: LONGINT; baseType: SyntaxTree.Type; b: BOOLEAN;
  3282. BEGIN
  3283. b := SemanticChecker.IsStaticMathArray(type, length, baseType) & (baseType IS SyntaxTree.FloatType) &
  3284. (baseType.sizeInBits <= 32) & (length = 4);
  3285. b := b OR SemanticChecker.IsStaticMathArray(type, length, baseType) & (baseType IS SyntaxTree.CharacterType) &
  3286. (baseType.sizeInBits = 8) & (length = 4);
  3287. b := b OR SemanticChecker.IsStaticArray(type, baseType, length) & (baseType.resolved IS SyntaxTree.CharacterType) &
  3288. (baseType.resolved.sizeInBits = 8) & (length = 4);
  3289. RETURN b
  3290. END CanPassInRegister;
  3291. PROCEDURE GetDescription*(VAR instructionSet: ARRAY OF CHAR);
  3292. BEGIN instructionSet := "AMD";
  3293. END GetDescription;
  3294. PROCEDURE DefineOptions*(options: Options.Options);
  3295. BEGIN
  3296. options.Add(0X,"bits",Options.Integer);
  3297. options.Add(0X,"traceable", Options.Flag);
  3298. options.Add(0X,"useFPU", Options.Flag);
  3299. DefineOptions^(options);
  3300. END DefineOptions;
  3301. PROCEDURE GetOptions*(options: Options.Options);
  3302. BEGIN
  3303. IF ~options.GetInteger("bits",bits) THEN bits := 32 END;
  3304. traceable := options.GetFlag("traceable");
  3305. forceFPU := options.GetFlag("useFPU");
  3306. GetOptions^(options);
  3307. END GetOptions;
  3308. PROCEDURE DefaultObjectFileFormat*(): Formats.ObjectFileFormat;
  3309. BEGIN RETURN ObjectFileFormat.Get();
  3310. END DefaultObjectFileFormat;
  3311. PROCEDURE DefaultSymbolFileFormat*(): Formats.SymbolFileFormat;
  3312. BEGIN
  3313. RETURN NIL
  3314. END DefaultSymbolFileFormat;
  3315. END BackendAMD64;
  3316. (** the number of regular sections in a section list **)
  3317. PROCEDURE RegularSectionCount(sectionList: Sections.SectionList): LONGINT;
  3318. VAR
  3319. section: Sections.Section;
  3320. i, result: LONGINT;
  3321. BEGIN
  3322. result := 0;
  3323. FOR i := 0 TO sectionList.Length() - 1 DO
  3324. section := sectionList.GetSection(i);
  3325. INC(result)
  3326. END;
  3327. RETURN result
  3328. END RegularSectionCount;
  3329. PROCEDURE Assert(b: BOOLEAN; CONST s: ARRAY OF CHAR);
  3330. BEGIN
  3331. ASSERT(b,100);
  3332. END Assert;
  3333. PROCEDURE Halt(CONST s: ARRAY OF CHAR);
  3334. BEGIN
  3335. HALT(100);
  3336. END Halt;
  3337. PROCEDURE ResolvedSection(in: IntermediateCode.Section): BinaryCode.Section;
  3338. VAR section: BinaryCode.Section;
  3339. BEGIN
  3340. IF in.resolved = NIL THEN
  3341. NEW(section,in.type, 8, in.name,in.comments # NIL,FALSE);
  3342. section.SetAlignment(in.fixed, in.positionOrAlignment);
  3343. in.SetResolved(section);
  3344. ELSE
  3345. section := in.resolved
  3346. END;
  3347. RETURN section
  3348. END ResolvedSection;
  3349. PROCEDURE Init;
  3350. VAR i: LONGINT;
  3351. BEGIN
  3352. FOR i := 0 TO LEN(registerOperands)-1 DO
  3353. Assembler.InitRegister(registerOperands[i],i);
  3354. END;
  3355. opEAX := registerOperands[EAX];
  3356. opEBX := registerOperands[EBX];
  3357. opECX := registerOperands[ECX];
  3358. opEDX := registerOperands[EDX];
  3359. opESI := registerOperands[ESI];
  3360. opEDI := registerOperands[EDI];
  3361. opEBP := registerOperands[EBP];
  3362. opESP := registerOperands[ESP];
  3363. opRSP := registerOperands[RSP];
  3364. opRBP := registerOperands[RBP];
  3365. opAX := registerOperands[AX];
  3366. opBX := registerOperands[BX];
  3367. opCX := registerOperands[CX];
  3368. opDX := registerOperands[DX];
  3369. opSI := registerOperands[SI];
  3370. opDI := registerOperands[DI];
  3371. opAL := registerOperands[AL];
  3372. opBL := registerOperands[BL];
  3373. opCL := registerOperands[CL];
  3374. opDL := registerOperands[DL];
  3375. opAH := registerOperands[AH];
  3376. opBH := registerOperands[BH];
  3377. opCH := registerOperands[CH];
  3378. opDH := registerOperands[DH];
  3379. opST0 := registerOperands[ST0];
  3380. NEW(unusable); NEW(blocked); NEW(split); free := NIL;
  3381. END Init;
  3382. PROCEDURE Get*(): Backend.Backend;
  3383. VAR backend: BackendAMD64;
  3384. BEGIN NEW(backend); RETURN backend
  3385. END Get;
  3386. PROCEDURE Trace*;
  3387. BEGIN
  3388. TRACE(traceStackSize);
  3389. END Trace;
  3390. BEGIN
  3391. traceStackSize := 0;
  3392. Init;
  3393. usePool := Machine.NumberOfProcessors()>1;
  3394. END FoxAMDBackend.
  3395. SystemTools.FreeDownTo FoxAMDBackend ~