BIOS.MemInfo.Mod 7.5 KB

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  1. (* Aos, Copyright 2001, Pieter Muller, ETH Zurich *)
  2. MODULE MemInfo; (** AUTHOR "pjm"; PURPOSE "Memory mapping information"; *)
  3. IMPORT SYSTEM, KernelLog, Machine;
  4. CONST
  5. SoftInt = Machine.SoftInt;
  6. (* standard multipliers *)
  7. K = 1024; M = 100000H; (* 1K, 1M *)
  8. PS = 4096;
  9. RS = 4*M; (* region covered by a page table in bytes *)
  10. PTEs = RS DIV PS; (* number of page table/directory entries *)
  11. VAR
  12. kernelPD: ADDRESS;
  13. msrlow, msrhigh: SET;
  14. PROCEDURE GetCR3(VAR state: Machine.State);
  15. CODE
  16. #IF I386 THEN
  17. MOV EAX, CR3
  18. MOV kernelPD, EAX
  19. #ELSIF AMD64 THEN
  20. MOV RAX, CR3
  21. MOV RBX, kernelPD
  22. MOV [RBX], RAX
  23. #ELSE
  24. unimplemented
  25. #END
  26. END GetCR3;
  27. PROCEDURE -DoSoftInt(eax: LONGINT);
  28. CODE
  29. #IF I386 THEN
  30. POP EAX
  31. INT SoftInt
  32. #ELSIF AMD64 THEN
  33. POP EAX
  34. INT SoftInt
  35. #ELSE
  36. unimplemented
  37. #END
  38. END DoSoftInt;
  39. (* Display mapped ranges. *)
  40. PROCEDURE DisplayMap*;
  41. VAR i, j: LONGINT; pt: LONGINT; virt, phys, virt0, phys0, size: LONGINT;
  42. PROCEDURE Page;
  43. BEGIN
  44. IF (phys = phys0+size) & (virt = virt0+size) THEN
  45. INC(size, PS)
  46. ELSE
  47. IF size # 0 THEN
  48. KernelLog.Hex(virt0, 9); KernelLog.Hex(phys0, 9);
  49. KernelLog.IntSuffix(size, 8, "B"); KernelLog.Ln
  50. END;
  51. virt0 := virt; phys0 := phys; size := PS
  52. END
  53. END Page;
  54. BEGIN
  55. Machine.InstallHandler(GetCR3, SoftInt); (* ignore race *)
  56. DoSoftInt(0);
  57. Machine.RemoveHandler(GetCR3, SoftInt);
  58. KernelLog.Enter; KernelLog.Char(0EX); KernelLog.Ln;
  59. KernelLog.String(" Virtual Physical Size"); KernelLog.Ln;
  60. virt := 0; virt0 := 0; phys0 := 0; size := 0;
  61. FOR i := 0 TO PTEs-1 DO
  62. SYSTEM.GET(kernelPD + SIZEOF(ADDRESS)*i, pt);
  63. IF ODD(pt) THEN (* present *)
  64. pt := pt - pt MOD PS;
  65. FOR j := 0 TO PTEs-1 DO
  66. SYSTEM.GET(pt, phys);
  67. IF ODD(phys) THEN
  68. DEC(phys, phys MOD PS);
  69. Page
  70. END;
  71. INC(pt, 4); INC(virt, 4*K)
  72. END
  73. ELSE
  74. INC(virt, 4*M)
  75. END
  76. END;
  77. virt := -1; Page;
  78. KernelLog.Char(0FX); KernelLog.Exit;
  79. END DisplayMap;
  80. PROCEDURE Write64(s: ARRAY OF CHAR; low, high: SET);
  81. BEGIN
  82. KernelLog.String(s); KernelLog.Char("=");
  83. KernelLog.Hex(SYSTEM.VAL(LONGINT, high), 8);
  84. KernelLog.Hex(SYSTEM.VAL(LONGINT, low), 9)
  85. END Write64;
  86. PROCEDURE Bits(s: ARRAY OF CHAR; x: SET; ofs, n: LONGINT);
  87. BEGIN
  88. KernelLog.String(s); KernelLog.Char("="); KernelLog.Bits(x, ofs, n)
  89. END Bits;
  90. PROCEDURE -RealReadMSR(msr: LONGWORD; VAR low, high: SET);
  91. CODE
  92. #IF I386 THEN
  93. POP EDI
  94. POP ESI
  95. POP ECX
  96. RDMSR
  97. MOV [ESI], EAX
  98. MOV [EDI], EDX
  99. #ELSIF AMD64 THEN
  100. POP RDI
  101. POP RSI
  102. POP ECX
  103. RDMSR
  104. MOV [RSI], EAX
  105. MOV [RDI], EDX
  106. #ELSE
  107. unimplemented
  108. #END
  109. END RealReadMSR;
  110. PROCEDURE IntReadMSR(VAR state: Machine.State);
  111. BEGIN
  112. #IF I386 THEN
  113. RealReadMSR(state.EAX, msrlow, msrhigh);
  114. #ELSIF AMD64 THEN
  115. RealReadMSR(state.RAX, msrlow, msrhigh);
  116. #ELSE
  117. unimplemented
  118. #END
  119. END IntReadMSR;
  120. PROCEDURE ReadMSR(msr: LONGINT; VAR low, high: SET);
  121. BEGIN
  122. Machine.InstallHandler(IntReadMSR, SoftInt); (* ignore race *)
  123. DoSoftInt(msr);
  124. Machine.RemoveHandler(IntReadMSR, SoftInt);
  125. low := msrlow; high := msrhigh
  126. END ReadMSR;
  127. PROCEDURE DisplayMTTR*;
  128. VAR version, i, j, k, vcnt: LONGINT; features, low, high, mask: SET; vendor: Machine.Vendor;
  129. BEGIN
  130. KernelLog.Enter;
  131. (* Machine.CPUID(vendor, version, features);
  132. KernelLog.String("CPU: "); KernelLog.Int(ASH(version, -8) MOD 16, 1);
  133. KernelLog.Char("."); KernelLog.Int(ASH(version, -4) MOD 16, 1);
  134. KernelLog.Char("."); KernelLog.Int(version MOD 16, 1);
  135. Bits(", features", features, 0, 32);
  136. KernelLog.String(", vendor "); KernelLog.String(vendor);
  137. KernelLog.Ln; *)
  138. features := Machine.features;
  139. IF 5 IN features THEN (* MSR supported *)
  140. IF 12 IN features THEN (* MTTR supported *)
  141. ReadMSR(0FEH, low, high);
  142. vcnt := SYSTEM.VAL(LONGINT, low) MOD 256;
  143. KernelLog.String("VCNT="); KernelLog.Int(vcnt, 1);
  144. Bits(", FIX", low, 8, 1); Bits(", WC", low, 10, 1);
  145. KernelLog.Ln;
  146. IF 8 IN low THEN
  147. ReadMSR(2FFH, low, high); Write64("DefType", low, high); KernelLog.Ln;
  148. ReadMSR(250H, low, high); Write64("Fix64k", low, high); KernelLog.Ln;
  149. ReadMSR(258H, low, high); Write64("Fix16k", low, high); KernelLog.Ln;
  150. ReadMSR(259H, low, high); Write64("Fix16k", low, high); KernelLog.Ln;
  151. ReadMSR(268H, low, high); Write64("Fix4k", low, high); KernelLog.Ln;
  152. ReadMSR(269H, low, high); Write64("Fix4k", low, high); KernelLog.Ln;
  153. ReadMSR(26AH, low, high); Write64("Fix4k", low, high); KernelLog.Ln;
  154. ReadMSR(26BH, low, high); Write64("Fix4k", low, high); KernelLog.Ln;
  155. ReadMSR(26CH, low, high); Write64("Fix4k", low, high); KernelLog.Ln;
  156. ReadMSR(26DH, low, high); Write64("Fix4k", low, high); KernelLog.Ln;
  157. ReadMSR(26EH, low, high); Write64("Fix4k", low, high); KernelLog.Ln;
  158. ReadMSR(26FH, low, high); Write64("Fix4k", low, high); KernelLog.Ln;
  159. FOR i := 0 TO vcnt-1 DO
  160. KernelLog.Int(i, 1);
  161. ReadMSR(200H+2*i, low, high); Write64(" base", low, high);
  162. ReadMSR(200H+2*i+1, low, high); Write64(", mask", low, high);
  163. IF 11 IN low THEN (* valid *)
  164. mask := LSH(low, -12);
  165. FOR j := 0 TO 3 DO
  166. IF j IN high THEN INCL(mask, 20+j) END
  167. END;
  168. j := 0; WHILE (j # 32) & ~(j IN mask) DO INC(j) END;
  169. k := 31; WHILE (k # -1) & ~(k IN mask) DO DEC(k) END;
  170. IF (k = 23) & (k >= j) & (mask = {j..k}) THEN
  171. KernelLog.String(", "); KernelLog.IntSuffix(SYSTEM.VAL(LONGINT, {j})*4*1024, 1, "B")
  172. ELSE
  173. KernelLog.String(" discon="); KernelLog.Hex(SYSTEM.VAL(LONGINT, mask), 8)
  174. END
  175. END;
  176. KernelLog.Ln
  177. END
  178. ELSE
  179. KernelLog.String("Fixed range registers not supported"); KernelLog.Ln
  180. END
  181. ELSE
  182. KernelLog.String("MTTR not supported"); KernelLog.Ln
  183. END
  184. ELSE
  185. KernelLog.String("MSR not supported"); KernelLog.Ln
  186. END;
  187. KernelLog.Exit;
  188. END DisplayMTTR;
  189. (*
  190. PROCEDURE IntSetCache(VAR state: Machine.State);
  191. VAR res: WORD;
  192. BEGIN
  193. Machine.SetLocalCacheProperties(0FA800000H, 800000H, Machine.WC, res);
  194. KernelLog.Enter; KernelLog.String("SetCache "); KernelLog.Int(res, 1); KernelLog.Exit
  195. END IntSetCache;
  196. PROCEDURE Test*;
  197. BEGIN
  198. Machine.InstallHandler(IntSetCache, SoftInt); (* ignore race *)
  199. DoSoftInt(0);
  200. Machine.RemoveHandler(IntSetCache, SoftInt)
  201. END Test;
  202. PROCEDURE -SetMTTRphysBase(n: LONGINT; high, low: LONGINT);
  203. CODE {SYSTEM.Pentium, SYSTEM.Privileged}
  204. POP EAX
  205. POP EDX
  206. POP ECX
  207. SHL ECX, 1
  208. ADD ECX, 200H ; MTTRphysBase0
  209. WRMSR
  210. END SetMTTRphysBase;
  211. PROCEDURE -SetMTTRphysMask(n: LONGINT; high, low: LONGINT);
  212. CODE {SYSTEM.Pentium, SYSTEM.Privileged}
  213. POP EAX
  214. POP EDX
  215. POP ECX
  216. SHL ECX, 1
  217. ADD ECX, 201H ; MTTRphysMask0
  218. WRMSR
  219. END SetMTTRphysMask;
  220. (*
  221. 1 000000000H 4GB WB
  222. 0 0F0000000H 128MB UC
  223. 4 0F8000000H 64MB UC
  224. - 0FC000000H 32MB WB (implicit)
  225. 3 0FE000000H 32MB UC
  226. 2 100000000H 256MB WB
  227. WB 0MB-2048MB 2048MB
  228. WB 2048MB-3072MB 1024MB
  229. WB 3072MB-3584MB 512MB
  230. WB 3584MB-3840MB 256MB
  231. WC 4032MB-4064MB 32MB
  232. WB 4096MB-4352MB 256MB
  233. *)
  234. PROCEDURE IntSetCache2(VAR state: Machine.State);
  235. BEGIN
  236. SetMTTRphysBase(3, 0, 0FE000000H);
  237. SetMTTRphysMask(3, 0FH, 0FE000800H);
  238. SetMTTRphysBase(4, 0, 0F8000000H);
  239. SetMTTRphysMask(4, 0FH, 0FC000800H);
  240. SetMTTRphysBase(0, 0, 0F0000000H);
  241. SetMTTRphysMask(0, 0FH, 0F8000800H)
  242. END IntSetCache2;
  243. PROCEDURE Test2*;
  244. BEGIN
  245. Machine.InstallHandler(IntSetCache2, SoftInt); (* ignore race *)
  246. DoSoftInt(0);
  247. Machine.RemoveHandler(IntSetCache2, SoftInt)
  248. END Test2;
  249. PROCEDURE Test3*;
  250. VAR res: LONGINT;
  251. BEGIN
  252. Processors.GlobalSetCacheProperties(0FA800000H, 800000H, Machine.WC, res);
  253. KernelLog.Enter; KernelLog.String("SetCache "); KernelLog.Int(res, 1); KernelLog.Exit
  254. END Test3;
  255. *)
  256. END MemInfo.
  257. System.Free MemInfo ~
  258. MemInfo.DisplayMap
  259. MemInfo.DisplayMTTR
  260. MemInfo.Test
  261. MemInfo.Test2
  262. MemInfo.Test3
  263. DisplayTests.Mod
  264. PCITools.Scan