A2OS/source/FoxAMD64InstructionSet.Mod

MODULE FoxAMD64InstructionSet; (**  AUTHOR "fof & fn"; PURPOSE "Oberon Compiler:AMD 64 Instruction Set";  **)
(* (c) fof ETH Zürich, 2008 *)

(** This module has been written with inspiration from
	-module CCIx86A.Mod : Component Compiler, Intel x86 Backend Assembler, 2005-2007, by Luc Bläser and
	-module AsmAMD64.Mod: AMD64 instruction set repository, 2006,  by Florian Negele
	The instruction set reference generator  is built by parsing the file InstructionSetAMD64.txt  also written by Florian Negele
	Parser for parsing the file is contained in FoxProgTools.Mod
**)

(** referenced literature
	[AMD:3] AMD64 Architecture Programmer's Manual Volume 3:General-Purpose and System Instructions

			Revision 3.14 September 2007
	[AMD:4] AMD64 Architecture Programmer's Manual Volume 4: 128-Bit Media Instructions
			Revision 3.14 September 2007
	[AMD:5] AMD64 Architecture Programmer's Manual Volume 5: 64-Bit Media and x87 Floating-Point Instructions
			Revision 3.14 September 2007
	[AMD:SSE5] AMD64 Technology 128-Bit SSE5 Instruction Set
			Revision 3.01 August 2007

	[INTEL:2A] Intel 64 and IA-32 Architectures Software Developer's Manual Volume 2A: Instruction Set Reference, A-M
			September 2008
	[INTEL:2B] Intel 64 and IA-32 Architectures Software Developer's Manual Volume 2B: Instruction Set Reference, N-Z
			September 2008
**)

IMPORT KernelLog (* debugging *);

CONST
	maxCPUs* = 30;
	maxNumberOperands*=5; (* maximal two source and one destination operand *)

	(* numbers generated by the instruction set parser *)
	maxNumberMnemonics = 1012;
	maxNumberInstructions = 3380;
	maxMnemonicNameLength =20;
	maxCodeLength* =12;
	none* = -1;

	bitsDefault*=0;
	bits8*=1;
	bits16*=2;
	bits32*=4;
	bits64*=8;
	bits128*=16;

	(** cpu options **)
	cpu8086* = 0;
	cpu186* = 1;
	cpu286* = 2;
	cpu386* = 3;
	cpu486* = 4;
	cpuPentium* = 5;
	cpuP6* = 6;
	cpuKatmai* = 7;
	cpuWillamette* = 8;
	cpuPrescott* = 9;
	cpuAMD64* = 10;
	(* unused options
	cpuSW = 11;
	cpuSB = 11;
	cpuSMM = 11;
	cpuAR1 = 11;
	cpuAR2 = 11;
	cpuND = 11;
	*)

	(** options selectable with CODE {SYSTEM.....} **)
	cpuPrivileged* = 20;
	cpuProtected* = 21;
	cpuSSE* = 22;
	cpuSSE2* = 23;
	cpuSSE3* = 24;
	cpu3DNow* = 25;
	cpuMMX* = 26;
	cpuFPU* = 27;

	cpuOptions* = {cpuPrivileged .. cpuFPU};

	(** instruction options **)
	optO16* = 0;	(* default 16bit operand size *)
	optO32* = 1;	(* default 32bit operand size *)
	optO64* = 2;	(* default 64bit operand size *)
	optD64* = 3;	(* default 64bit operand size in 64bit mode *)
	optNot64* = 4;		(* instruction invalid in 64bit mode *)
	optA16* = 5;	(* default 16bit address size *)
	optA32* = 6;	(* default 32bit address size *)

	optPOP* = 7;		(* an operand size override prefix must preceed the instruction *)
	optPLOCK* = 8;		(* a lock prefix must preceed the instruction *)
	optPREP* = 9;		(* a repeat prefix must preceed the instruction *)
	optPREPN* = 10;	(* a repeat prefix must preceed the instruction *)

	(*
		FoxProgTools.Enum -l=1 -e
		(** operand types, numbers assigned to the types do not have a special meaning **)
		(* register classes first *)
		reg8 reg16 reg32 reg64 CRn DRn segReg mmx xmm ymm sti
		(* other classes *)
		mem imm ioffset pntr1616 pntr1632
		(* special registers *)
		AL  AX  CL  CR8   CS   DS  DX  EAX  ECX  ES  FS  GS  RAX  SS rAX st0
		(* immediates and memory locations *)
		imm16  imm32  imm64  imm8
		uimm16  uimm32  uimm8
		simm16  simm32  simm8
		mem256
		mem128  mem16  mem32  mem64  mem8
		moffset16  moffset32  moffset64  moffset8
		rel16off  rel32off  rel8off
		(* ambivalent operand types *)
		reg3264
		regmem16  regmem32  regmem64  regmem8 reg32mem16
		mmxmem32  mmxmem64
		xmmmem256 xmmmem128  xmmmem32  xmmmem64
		xmmmem8
		xmmmem16
		ymmmem128
		ymmmem256
		(* miscellaneous *)
		one three
		vm32x
		vm32y
		vm64x
		vm64y
		m2z;
		~
	*)
	(** operand types, numbers assigned to the types do not have a special meaning **)
	(* register classes first *)
	reg8*= 0;
	reg16*= 1;
	reg32*= 2;
	reg64*= 3;
	CRn*= 4;
	DRn*= 5;
	segReg*= 6;
	mmx*= 7;
	xmm*= 8;
	ymm*= 9;
	sti*= 10;
	(* other classes *)
	mem*= 11;
	imm*= 12;
	ioffset*= 13;
	pntr1616*= 14;
	pntr1632*= 15;
	(* special registers *)
	AL*= 16;
	AX*= 17;
	CL*= 18;
	CR8*= 19;
	CS*= 20;
	DS*= 21;
	DX*= 22;
	EAX*= 23;
	ECX*= 24;
	ES*= 25;
	FS*= 26;
	GS*= 27;
	RAX*= 28;
	SS*= 29;
	rAX*= 30;
	st0*= 31;
	(* immediates and memory locations *)
	imm16*= 32;
	imm32*= 33;
	imm64*= 34;
	imm8*= 35;
	uimm16*= 36;
	uimm32*= 37;
	uimm8*= 38;
	simm16*= 39;
	simm32*= 40;
	simm8*= 41;
	mem256*= 42;
	mem128*= 43;
	mem16*= 44;
	mem32*= 45;
	mem64*= 46;
	mem8*= 47;
	moffset16*= 48;
	moffset32*= 49;
	moffset64*= 50;
	moffset8*= 51;
	rel16off*= 52;
	rel32off*= 53;
	rel8off*= 54;
	(* ambivalent operand types *)
	reg3264*= 55;
	regmem16*= 56;
	regmem32*= 57;
	regmem64*= 58;
	regmem8*= 59;
	reg32mem16*= 60;
	mmxmem32*= 61;
	mmxmem64*= 62;
	xmmmem256*= 63;
	xmmmem128*= 64;
	xmmmem32*= 65;
	xmmmem64*= 66;
	xmmmem8*= 67;
	xmmmem16*= 68;
	ymmmem128*= 69;
	ymmmem256*= 70;
	(* miscellaneous *)
	one*= 71;
	three*= 72;
	vm32x*= 73;
	vm32y*= 74;
	vm64x*= 75;
	vm64y*= 76;
	m2z*= 77;

	(** prefixes **)
	prfOP* = 066H;
	prfADR* = 067H;
	prfCS* = 02EH;		(* ignored in 64bit mode *)
	prfDS* = 03EH;		(* ignored in 64bit mode *)
	prfES* = 026H;		(* ignored in 64bit mode *)
	prfFS* = 064H;
	prfGS* = 065H;
	prfSS* = 036H;		(* ignored in 64bit mode *)
	prfLOCK* = 0F0H;
	prfREP* = 0F3H;
	prfREPE* = 0F3H;
	prfREPZ* = 0F3H;
	prfREPNE* = 0F2H;
	prfREPNZ* = 0F2H;

	(* registers
		FoxProgTools.Enum -e -l=8 -s=0
		(** 8 bit general purpose registers **)
		regAL regCL regDL regBL  regAH regCH regDH regBH
		regSPL regBPL regSIL regDIL
		~
		FoxProgTools.Enum -e -l=16 -s=16
		regR8B regR9B regR10B regR11B regR12B regR13B regR14B regR15B
		~
		FoxProgTools.Enum -l=8 -e -s=32
		(** 16 bit general purpose registers **)
		regAX regCX regDX regBX regSP regBP regSI regDI
		regR8W regR9W regR10W regR11W regR12W regR13W regR14W regR15W
		~
		FoxProgTools.Enum -l=8 -e -s=64
		(** 32 bit general purpose registers **)
		regEAX regECX regEDX regEBX regESP regEBP regESI regEDI
		regR8D regR9D regR10D regR11D regR12D regR13D regR14D regR15D
		~
		FoxProgTools.Enum -l=8 -e -s=96
		(** 64 bit general purpose registers **)
		regRAX regRCX regRDX regRBX regRSP regRBP regRSI  regRDI
		regR8 regR9 regR10 regR11 regR12 regR13 regR14 regR15 regRIP
		~
		FoxProgTools.Enum -l=8 -e -s=128
		regES regCS regSS regDS regFS regGS
		regCR0 regCR1 regCR2 regCR3 regCR4 regCR5 regCR6 regCR7
		regCR8 regCR9 regCR10 regCR11 regCR12 regCR13 regCR14 regCR15
		regDR0 regDR1 regDR2 regDR3 regDR4 regDR5 regDR6 regDR7
		regDR8 regDR9 regDR10 regDR11 regDR12 regDR13 regDR14 regDR15
		regST0 regST1 regST2 regST3 regST4 regST5 regST6 regST7
		regXMM0 regXMM1 regXMM2 regXMM3 regXMM4 regXMM5 regXMM6 regXMM7
		regXMM8 regXMM9 regXMM10 regXMM11 regXMM12 regXMM13 regXMM14 regXMM15
		regMMX0 regMMX1 regMMX2 regMMX3 regMMX4 regMMX5 regMMX6 regMMX7
		regYMM0 regYMM1 regYMM2 regYMM3 regYMM4 regYMM5 regYMM6 regYMM7
		regYMM8 regYMM9 regYMM10 regYMM11 regYMM12 regYMM13 regYMM14 regYMM15

		numberRegisters
		~
	*)

		(*
			regNumber = S*32 + N

		N\S		0		1		2		3
		0			AL		AX		EAX	RAX
		1			CL		CX		ECX	RCX
		2			DL		DX		EDX	RDX
		3			BL		BX		EBX	RBX
		4			SPL		SP		ESP		RSP
		5			BPL		BP		EBP	RBP
		6			SIL		SI		ESI		RSI
		7			DIL		DI		EDI		RDI
		8			R8B	R8W	R8D	R8
		9			R9B	R9W	R9D	R9
		10			R10B	R10W	R10D	R10
		11			R11B	R11W	R11D	R11
		12			R12B	R12W	R12D	R12
		13			R13B	R13W	R13D	R13
		14			R14B	R14W	R14D	R14
		15			R15B	R15W	R15D	R15
		16			AH
		17			CH
		18			BH
		19			DH

		*)

	(** register indices, the order is arbitrary and has no meaning for instruction encoding,
	it nevertheless should not be changed as the numbers are important on in the code generator !  **)
	(** 8 bit general purpose registers : index DIV 32 = 0**)
	regAL*= 0; regCL*= 1; regDL*= 2; regBL*= 3; regSPL*= 4; regBPL*= 5; regSIL*= 6; regDIL*= 7;
	regAH*= 16; regCH*= 17; regDH*= 18; regBH*= 19;
	regR8B*= 8; regR9B*= 9; regR10B*= 10; regR11B*= 11; regR12B*= 12; regR13B*= 13; regR14B*= 14; regR15B*= 15;
	(** 16 bit general purpose registers : index DIV 32 = 1**)
	regAX*= 32; regCX*= 33; regDX*= 34; regBX*= 35; regSP*= 36; regBP*= 37; regSI*= 38; regDI*= 39;
	regR8W*= 40; regR9W*= 41; regR10W*= 42; regR11W*= 43; regR12W*= 44; regR13W*= 45; regR14W*= 46; regR15W*= 47;
	(** 32 bit general purpose registers: index DIV 32 = 2 **)
	regEAX*= 64; regECX*= 65; regEDX*= 66; regEBX*= 67; regESP*= 68; regEBP*= 69; regESI*= 70; regEDI*= 71;
	regR8D*= 72; regR9D*= 73; regR10D*= 74; regR11D*= 75; regR12D*= 76; regR13D*= 77; regR14D*= 78; regR15D*= 79;
	(** 64 bit general purpose registers : index DIV 32 = 3 (except for regRIP) **)
	regRAX*= 96; regRCX*= 97; regRDX*= 98; regRBX*= 99; regRSP*= 100; regRBP*= 101; regRSI*= 102; regRDI*= 103;
	regR8*= 104; regR9*= 105; regR10*= 106; regR11*= 107; regR12*= 108; regR13*= 109; regR14*= 110; regR15*= 111;
	regRIP*= 112;
	(** other registers **)
	regES*= 128; regCS*= 129; regSS*= 130; regDS*= 131; regFS*= 132; regGS*= 133; regCR0*= 134; regCR1*= 135;
	regCR2*= 136; regCR3*= 137; regCR4*= 138; regCR5*= 139; regCR6*= 140; regCR7*= 141; regCR8*= 142; regCR9*= 143;
	regCR10*= 144; regCR11*= 145; regCR12*= 146; regCR13*= 147; regCR14*= 148; regCR15*= 149; regDR0*= 150; regDR1*= 151;
	regDR2*= 152; regDR3*= 153; regDR4*= 154; regDR5*= 155; regDR6*= 156; regDR7*= 157; regDR8*= 158; regDR9*= 159;
	regDR10*= 160; regDR11*= 161; regDR12*= 162; regDR13*= 163; regDR14*= 164; regDR15*= 165; regST0*= 166; regST1*= 167;
	regST2*= 168; regST3*= 169; regST4*= 170; regST5*= 171; regST6*= 172; regST7*= 173; regXMM0*= 174; regXMM1*= 175;
	regXMM2*= 176; regXMM3*= 177; regXMM4*= 178; regXMM5*= 179; regXMM6*= 180; regXMM7*= 181; regXMM8*= 182; regXMM9*= 183;
	regXMM10*= 184; regXMM11*= 185; regXMM12*= 186; regXMM13*= 187; regXMM14*= 188; regXMM15*= 189; regMMX0*= 190; regMMX1*= 191;
	regMMX2*= 192; regMMX3*= 193; regMMX4*= 194; regMMX5*= 195; regMMX6*= 196; regMMX7*= 197; regYMM0*= 198; regYMM1*= 199;
	regYMM2*= 200; regYMM3*= 201; regYMM4*= 202; regYMM5*= 203; regYMM6*= 204; regYMM7*= 205; regYMM8*= 206; regYMM9*= 207;
	regYMM10*= 208; regYMM11*= 209; regYMM12*= 210; regYMM13*= 211; regYMM14*= 212; regYMM15*= 213;
	numberRegisters*= 214;

VAR
	opAAA*,
	opAAD*,
	opAAM*,
	opAAS*,
	opADC*,
	opADD*,
	opADDPD*,
	opADDPS*,
	opADDSD*,
	opADDSS*,
	opADDSUBPD*,
	opADDSUBPS*,
	opAND*,
	opANDNPD*,
	opANDNPS*,
	opANDPD*,
	opANDPS*,
	opARPL*,
	opBOUND*,
	opBSF*,
	opBSR*,
	opBSWAP*,
	opBT*,
	opBTC*,
	opBTR*,
	opBTS*,
	opCALL*,
	opCALLFAR*,
	opCBW*,
	opCDQ*,
	opCDQE*,
	opCLC*,
	opCLD*,
	opCLFLUSH*,
	opCLGI*,
	opCLI*,
	opCLTS*,
	opCMC*,
	opCMOVA*,
	opCMOVAE*,
	opCMOVB*,
	opCMOVBE*,
	opCMOVC*,
	opCMOVE*,
	opCMOVG*,
	opCMOVGE*,
	opCMOVL*,
	opCMOVLE*,
	opCMOVNA*,
	opCMOVNAE*,
	opCMOVNB*,
	opCMOVNBE*,
	opCMOVNC*,
	opCMOVNE*,
	opCMOVNG*,
	opCMOVNGE*,
	opCMOVNL*,
	opCMOVNLE*,
	opCMOVNO*,
	opCMOVNP*,
	opCMOVNS*,
	opCMOVNZ*,
	opCMOVO*,
	opCMOVP*,
	opCMOVPE*,
	opCMOVPO*,
	opCMOVS*,
	opCMOVZ*,
	opCMP*,
	opCMPPD*,
	opCMPPS*,
	opCMPS*,
	opCMPSB*,
	opCMPSD*,
	opCMPSQ*,
	opCMPSS*,
	opCMPSW*,
	opCMPXCHG*,
	opCMPXCHG16B*,
	opCMPXCHG8B*,
	opCOMISD*,
	opCOMISS*,
	opCPUID*,
	opCQO*,
	opCVTDQ2PD*,
	opCVTDQ2PS*,
	opCVTPD2DQ*,
	opCVTPD2PI*,
	opCVTPD2PS*,
	opCVTPI2PD*,
	opCVTPI2PS*,
	opCVTPS2DQ*,
	opCVTPS2PD*,
	opCVTPS2PI*,
	opCVTSD2SI*,
	opCVTSD2SS*,
	opCVTSI2SD*,
	opCVTSI2SS*,
	opCVTSS2SD*,
	opCVTSS2SI*,
	opCVTTPD2DQ*,
	opCVTTPD2PI*,
	opCVTTPS2DQ*,
	opCVTTPS2PI*,
	opCVTTSD2SI*,
	opCVTTSS2SI*,
	opCWD*,
	opCWDE*,
	opDAA*,
	opDAS*,
	opDEC*,
	opDIV*,
	opDIVPD*,
	opDIVPS*,
	opDIVSD*,
	opDIVSS*,
	opEMMS*,
	opENTER*,
	opF2XM1*,
	opFABS*,
	opFADD*,
	opFADDP*,
	opFBLD*,
	opFBSTP*,
	opFCHS*,
	opFCLEX*,
	opFCMOVB*,
	opFCMOVBE*,
	opFCMOVE*,
	opFCMOVNB*,
	opFCMOVNBE*,
	opFCMOVNE*,
	opFCMOVNU*,
	opFCMOVU*,
	opFCOM*,
	opFCOMI*,
	opFCOMIP*,
	opFCOMP*,
	opFCOMPP*,
	opFCOS*,
	opFDECSTP*,
	opFDIV*,
	opFDIVP*,
	opFDIVR*,
	opFDIVRP*,
	opFEMMS*,
	opFFREE*,
	opFIADD*,
	opFICOM*,
	opFICOMP*,
	opFIDIV*,
	opFIDIVR*,
	opFILD*,
	opFIMUL*,
	opFINCSTP*,
	opFINIT*,
	opFIST*,
	opFISTP*,
	opFISTTP*,
	opFISUB*,
	opFISUBR*,
	opFLD*,
	opFLD1*,
	opFLDCW*,
	opFLDENV*,
	opFLDL2E*,
	opFLDL2T*,
	opFLDLG2*,
	opFLDLN2*,
	opFLDPI*,
	opFLDZ*,
	opFMUL*,
	opFMULP*,
	opFNCLEX*,
	opFNINIT*,
	opFNOP*,
	opFNSAVE*,
	opFNSTCW*,
	opFNSTENV*,
	opFNSTSW*,
	opFPATAN*,
	opFPREM*,
	opFPREM1*,
	opFPTAN*,
	opFRNDINT*,
	opFRSTOR*,
	opFSAVE*,
	opFSCALE*,
	opFSIN*,
	opFSINCOS*,
	opFSQRT*,
	opFST*,
	opFSTCW*,
	opFSTENV*,
	opFSTP*,
	opFSTSW*,
	opFSUB*,
	opFSUBP*,
	opFSUBR*,
	opFSUBRP*,
	opFTST*,
	opFUCOM*,
	opFUCOMI*,
	opFUCOMIP*,
	opFUCOMP*,
	opFUCOMPP*,
	opFWAIT*,
	opFXAM*,
	opFXCH*,
	opFXRSTOR*,
	opFXSAVE*,
	opFXTRACT*,
	opFYL2X*,
	opFYL2XP1*,
	opHADDPD*,
	opHADDPS*,
	opHLT*,
	opHSUBPD*,
	opHSUBPS*,
	opIDIV*,
	opIMUL*,
	opIN*,
	opINC*,
	opINS*,
	opINSB*,
	opINSD*,
	opINSW*,
	opINT*,
	opINT3*,
	opINTO*,
	opINVD*,
	opINVLPG*,
	opINVLPGA*,
	opIRET*,
	opIRETD*,
	opIRETQ*,
	opJA*,
	opJAE*,
	opJB*,
	opJBE*,
	opJC*,
	opJCXZ*,
	opJE*,
	opJECXZ*,
	opJG*,
	opJGE*,
	opJL*,
	opJLE*,
	opJMP*,
	opJMPFAR*,
	opJNA*,
	opJNAE*,
	opJNB*,
	opJNBE*,
	opJNC*,
	opJNE*,
	opJNG*,
	opJNGE*,
	opJNL*,
	opJNLE*,
	opJNO*,
	opJNP*,
	opJNS*,
	opJNZ*,
	opJO*,
	opJP*,
	opJPE*,
	opJPO*,
	opJRCXZ*,
	opJS*,
	opJZ*,
	opLAHF*,
	opLAR*,
	opLDDQU*,
	opLDMXCSR*,
	opLDS*,
	opLEA*,
	opLEAVE*,
	opLES*,
	opLFENCE*,
	opLFS*,
	opLGDT*,
	opLGS*,
	opLIDT*,
	opLLDT*,
	opLMSW*,
	opLODS*,
	opLODSB*,
	opLODSD*,
	opLODSQ*,
	opLODSW*,
	opLOOP*,
	opLOOPE*,
	opLOOPNE*,
	opLOOPNZ*,
	opLOOPZ*,
	opLSL*,
	opLSS*,
	opLTR*,
	opMASKMOVDQU*,
	opMASKMOVQ*,
	opMAXPD*,
	opMAXPS*,
	opMAXSD*,
	opMAXSS*,
	opMFENCE*,
	opMINPD*,
	opMINPS*,
	opMINSD*,
	opMINSS*,
	opMOV*,
	opMOVAPD*,
	opMOVAPS*,
	opMOVD*,
	opMOVDDUP*,
	opMOVDQ2Q*,
	opMOVDQA*,
	opMOVDQU*,
	opMOVHLPS*,
	opMOVHPD*,
	opMOVHPS*,
	opMOVLHPS*,
	opMOVLPD*,
	opMOVLPS*,
	opMOVMSKPD*,
	opMOVMSKPS*,
	opMOVNTDQ*,
	opMOVNTI*,
	opMOVNTPD*,
	opMOVNTPS*,
	opMOVNTQ*,
	opMOVQ*,
	opMOVQ2DQ*,
	opMOVS*,
	opMOVSB*,
	opMOVSD*,
	opMOVSHDUP*,
	opMOVSLDUP*,
	opMOVSQ*,
	opMOVSS*,
	opMOVSW*,
	opMOVSX*,
	opMOVSXD*,
	opMOVUPD*,
	opMOVUPS*,
	opMOVZX*,
	opMUL*,
	opMULPD*,
	opMULPS*,
	opMULSD*,
	opMULSS*,
	opNEG*,
	opNOP*,
	opNOT*,
	opOR*,
	opORPD*,
	opORPS*,
	opOUT*,
	opOUTS*,
	opOUTSB*,
	opOUTSD*,
	opOUTSW*,
	opPACKSSDW*,
	opPACKSSWB*,
	opPACKUSWB*,
	opPADDB*,
	opPADDD*,
	opPADDQ*,
	opPADDSB*,
	opPADDSW*,
	opPADDUSB*,
	opPADDUSW*,
	opPADDW*,
	opPAND*,
	opPANDN*,
	opPAUSE*,
	opPAVGB*,
	opPAVGUSB*,
	opPAVGW*,
	opPCMPEQB*,
	opPCMPEQD*,
	opPCMPEQW*,
	opPCMPGTB*,
	opPCMPGTD*,
	opPCMPGTW*,
	opPEXTRW*,
	opPF2ID*,
	opPF2IW*,
	opPFACC*,
	opPFADD*,
	opPFCMPEQ*,
	opPFCMPGE*,
	opPFCMPGT*,
	opPFMAX*,
	opPFMIN*,
	opPFMUL*,
	opPFNACC*,
	opPFPNACC*,
	opPFRCP*,
	opPFRCPIT1*,
	opPFRCPIT2*,
	opPFRSQIT1*,
	opPFRSQRT*,
	opPFSUB*,
	opPFSUBR*,
	opPI2FD*,
	opPI2FW*,
	opPINSRW*,
	opPMADDWD*,
	opPMAXSW*,
	opPMAXUB*,
	opPMINSW*,
	opPMINUB*,
	opPMOVMSKB*,
	opPMULHRW*,
	opPMULHUW*,
	opPMULHW*,
	opPMULLW*,
	opPMULUDQ*,
	opPOP*,
	opPOPA*,
	opPOPAD*,
	opPOPAW*,
	opPOPF*,
	opPOPFD*,
	opPOPFQ*,
	opPOR*,
	opPREFETCH*,
	opPREFETCHNTA*,
	opPREFETCHT0*,
	opPREFETCHT1*,
	opPREFETCHT2*,
	opPREFETCHW*,
	opPSADBW*,
	opPSHUFD*,
	opPSHUFHW*,
	opPSHUFLW*,
	opPSHUFW*,
	opPSLLD*,
	opPSLLDQ*,
	opPSLLQ*,
	opPSLLW*,
	opPSRAD*,
	opPSRAW*,
	opPSRLD*,
	opPSRLDQ*,
	opPSRLQ*,
	opPSRLW*,
	opPSUBB*,
	opPSUBD*,
	opPSUBQ*,
	opPSUBSB*,
	opPSUBSW*,
	opPSUBUSB*,
	opPSUBUSW*,
	opPSUBW*,
	opPSWAPD*,
	opPUNPCKHBW*,
	opPUNPCKHDQ*,
	opPUNPCKHQDQ*,
	opPUNPCKHWD*,
	opPUNPCKLBW*,
	opPUNPCKLDQ*,
	opPUNPCKLQDQ*,
	opPUNPCKLWD*,
	opPUSH*,
	opPUSHA*,
	opPUSHAD*,
	opPUSHF*,
	opPUSHFD*,
	opPUSHFQ*,
	opPXOR*,
	opRCL*,
	opRCPPS*,
	opRCPSS*,
	opRCR*,
	opRDMSR*,
	opRDPMC*,
	opRDTSC*,
	opRDTSCP*,
	opRET*,
	opRETF*,
	opROL*,
	opROR*,
	opRSM*,
	opRSQRTPS*,
	opRSQRTSS*,
	opSAHF*,
	opSAL*,
	opSAR*,
	opSBB*,
	opSCAS*,
	opSCASB*,
	opSCASD*,
	opSCASQ*,
	opSCASW*,
	opSETA*,
	opSETAE*,
	opSETB*,
	opSETBE*,
	opSETC*,
	opSETE*,
	opSETG*,
	opSETGE*,
	opSETL*,
	opSETLE*,
	opSETNA*,
	opSETNAE*,
	opSETNB*,
	opSETNBE*,
	opSETNC*,
	opSETNE*,
	opSETNG*,
	opSETNGE*,
	opSETNL*,
	opSETNLE*,
	opSETNO*,
	opSETNP*,
	opSETNS*,
	opSETNZ*,
	opSETO*,
	opSETP*,
	opSETPE*,
	opSETPO*,
	opSETS*,
	opSETZ*,
	opSFENCE*,
	opSGDT*,
	opSHL*,
	opSHLD*,
	opSHR*,
	opSHRD*,
	opSHUFPD*,
	opSHUFPS*,
	opSIDT*,
	opSKINIT*,
	opSLDT*,
	opSMSW*,
	opSQRTPD*,
	opSQRTPS*,
	opSQRTSD*,
	opSQRTSS*,
	opSTC*,
	opSTD*,
	opSTGI*,
	opSTI*,
	opSTMXCSR*,
	opSTOS*,
	opSTOSB*,
	opSTOSD*,
	opSTOSQ*,
	opSTOSW*,
	opSTR*,
	opSUB*,
	opSUBPD*,
	opSUBPS*,
	opSUBSD*,
	opSUBSS*,
	opSWAPGS*,
	opSYSCALL*,
	opSYSENTER*,
	opSYSEXIT*,
	opSYSRET*,
	opTEST*,
	opUCOMISD*,
	opUCOMISS*,
	opUD2*,
	opUNPCKHPD*,
	opUNPCKHPS*,
	opUNPCKLPD*,
	opUNPCKLPS*,
	opVERR*,
	opVERW*,
	opVMLOAD*,
	opVMMCALL*,
	opVMRUN*,
	opVMSAVE*,
	opWBINVD*,
	opWRMSR*,
	opXADD*,
	opXCHG*,
	opXLAT*,
	opXLATB*,
	opXOR*,
	opXORPD*,
	opXORPS*: LONGINT;
(* AVX 2 Media instructions *)
	opVAESKEYGENASSIST*,
	opVPMADCSWD*,
	opVADDPD*,
	opVADDPS*,
	opVADDSD*,
	opVADDSS*,
	opVADDSUBPD*,
	opVADDSUBPS*,
	opVAESDEC*,
	opVAESDECLAST*,
	opVAESENC*,
	opVAESENCLAST*,
	opVAESIMC*,
	opVANDNPD*,
	opVANDNPS*,
	opVANDPD*,
	opVANDPS*,
	opVBLENDPD*,
	opVBLENDPS*,
	opVBLENDVPD*,
	opVBLENDVPS*,
	opVBROADCASTF128*,
	opVBROADCASTI128*,
	opVBROADCASTSD*,
	opVBROADCASTSS*,
	opVCMPPD*,
	opVCMPPS*,
	opVCMPSD*,
	opVCMPSS*,
	opVCOMISD*,
	opVCOMISS*,
	opVCVTDQ2PD*,
	opVCVTDQ2PS*,
	opVCVTPD2DQ*,
	opVCVTPD2PS*,
	opVCVTPH2PS*,
	opVCVTPS2DQ*,
	opVCVTPS2PD*,
	opVCVTPS2PH*,
	opVCVTSD2SI*,
	opVCVTSD2SS*,
	opVCVTSI2SD*,
	opVCVTSI2SS*,
	opVCVTSS2SD*,
	opVCVTSS2SI*,
	opVCVTTPD2DQ*,
	opVCVTTPS2DQ*,
	opVCVTTSD2SI*,
	opVCVTTSS2SI*,
	opVDIVPD*,
	opVDIVPS*,
	opVDIVSD*,
	opVDIVSS*,
	opVDPPD*,
	opVDPPS*,
	opVEXTRACTF128*,
	opVEXTRACTI128*,
	opVEXTRACTPS*,
	opVFMADD132PD*,
	opVFMADD132PS*,
	opVFMADD132SD*,
	opVFMADD132SS*,
	opVFMADD213PD*,
	opVFMADD213PS*,
	opVFMADD213SD*,
	opVFMADD213SS*,
	opVFMADD231PD*,
	opVFMADD231PS*,
	opVFMADD231SD*,
	opVFMADD231SS*,
	opVFMADDPD*,
	opVFMADDPS*,
	opVFMADDSD*,
	opVFMADDSS*,
	opVFMADDSUB132PD*,
	opVFMADDSUB132PS*,
	opVFMADDSUB213PD*,
	opVFMADDSUB213PS*,
	opVFMADDSUB231PD*,
	opVFMADDSUB231PS*,
	opVFMADDSUBPD*,
	opVFMADDSUBPS*,
	opVFMSUB132PD*,
	opVFMSUB132PS*,
	opVFMSUB132SD*,
	opVFMSUB132SS*,
	opVFMSUB213PD*,
	opVFMSUB213PS*,
	opVFMSUB213SD*,
	opVFMSUB213SS*,
	opVFMSUB231PD*,
	opVFMSUB231PS*,
	opVFMSUB231SD*,
	opVFMSUB231SS*,
	opVFMSUBADD132PD*,
	opVFMSUBADD132PS*,
	opVFMSUBADD213PD*,
	opVFMSUBADD213PS*,
	opVFMSUBADD231PD*,
	opVFMSUBADD231PS*,
	opVFMSUBADDPD*,
	opVFMSUBADDPS*,
	opVFMSUBPD*,
	opVFMSUBPS*,
	opVFMSUBSD*,
	opVFMSUBSS*,
	opVFNMADD132PD*,
	opVFNMADD132PS*,
	opVFNMADD132SD*,
	opVFNMADD132SS*,
	opVFNMADD213PD*,
	opVFNMADD213PS*,
	opVFNMADD213SD*,
	opVFNMADD213SS*,
	opVFNMADD231PD*,
	opVFNMADD231PS*,
	opVFNMADD231SD*,
	opVFNMADD231SS*,
	opVFNMADDPD*,
	opVFNMADDPS*,
	opVFNMADDSD*,
	opVFNMADDSS*,
	opVFNMSUB132PD*,
	opVFNMSUB132PS*,
	opVFNMSUB132SD*,
	opVFNMSUB132SS*,
	opVFNMSUB213PD*,
	opVFNMSUB213PS*,
	opVFNMSUB213SD*,
	opVFNMSUB213SS*,
	opVFNMSUB231PD*,
	opVFNMSUB231PS*,
	opVFNMSUB231SD*,
	opVFNMSUB231SS*,
	opVFNMSUBPD*,
	opVFNMSUBPS*,
	opVFNMSUBSD*,
	opVFNMSUBSS*,
	opVFRCZPD*,
	opVFRCZPS*,
	opVFRCZSD*,
	opVFRCZSS*,
	opVGATHERDPD*,
	opVGATHERDPS*,
	opVGATHERQPD*,
	opVGATHERQPS*,
	opVHADDPD*,
	opVHADDPS*,
	opVHSUBPD*,
	opVHSUBPS*,
	opVINSERTF128*,
	opVINSERTI128*,
	opVINSERTPS*,
	opVLDDQU*,
	opVLDMXCSR*,
	opVMASKMOVDQU*,
	opVMASKMOVPD*,
	opVMASKMOVPS*,
	opVMAXPD*,
	opVMAXPS*,
	opVMAXSD*,
	opVMAXSS*,
	opVMINPD*,
	opVMINPS*,
	opVMINSD*,
	opVMINSS*,
	opVMOVAPD*,
	opVMOVAPS*,
	opVMOVD*,
	opVMOVDDUP*,
	opVMOVDQA*,
	opVMOVDQU*,
	opVMOVHLPS*,
	opVMOVHPD*,
	opVMOVHPS*,
	opVMOVLHPS*,
	opVMOVLPD*,
	opVMOVLPS*,
	opVPMOVMSKB*,
	opVMOVMSKPD*,
	opVMOVMSKPS*,
	opVMOVNTDQ*,
	opVMOVNTDQA*,
	opVMOVNTPD*,
	opVMOVNTPS*,
	opVMOVQ*,
	opVMOVSD*,
	opVMOVSHDUP*,
	opVMOVSLDUP*,
	opVMOVSS*,
	opVMOVUPD*,
	opVMOVUPS*,
	opVMPSADBW*,
	opVMULPD*,
	opVMULPS*,
	opVMULSD*,
	opVMULSS*,
	opVORPD*,
	opVORPS*,
	opVPABSB*,
	opVPABSD*,
	opVPABSW*,
	opVPACKSSDW*,
	opVPACKSSWB*,
	opVPACKUSDW*,
	opVPACKUSWB*,
	opVPADDB*,
	opVPADDD*,
	opVPADDQ*,
	opVPADDSB*,
	opVPADDSW*,
	opVPADDUSB*,
	opVPADDUSW*,
	opVPADDW*,
	opVPALIGNR*,
	opVPAND*,
	opVPANDN*,
	opVPAVGB*,
	opVPAVGW*,
	opVPBLENDD*,
	opVPBLENDVB*,
	opVPBLENDW*,
	opVPBROADCASTB*,
	opVPBROADCASTD*,
	opVPBROADCASTQ*,
	opVPBROADCASTW*,
	opVPCLMULQDQ*,
	opVPCMOV*,
	opVPCMPEQB*,
	opVPCMPEQD*,
	opVPCMPEQQ*,
	opVPCMPEQW*,
	opVPCMPESTRI*,
	opVPCMPESTRM*,
	opVPCMPGTB*,
	opVPCMPGTD*,
	opVPCMPGTQ*,
	opVPCMPGTW*,
	opVPCMPISTRI*,
	opVPCMPISTRM*,
	opVPCOMB*,
	opVPCOMD*,
	opVPCOMQ*,
	opVPCOMUB*,
	opVPCOMUD*,
	opVPCOMUQ*,
	opVPCOMUW*,
	opVPCOMW*,
	opVPERM2F128*,
	opVPERM2I128*,
	opVPERMD*,
	opVPERMIL2PD*,
	opVPERMIL2PS*,
	opVPERMILPD*,
	opVPERMILPS*,
	opVPERMPD*,
	opVPERMPS*,
	opVPERMQ*,
	opVPEXTRB*,
	opVPEXTRD*,
	opVPEXTRQ*,
	opVPEXTRW*,
	opVPGATHERDD*,
	opVPGATHERDQ*,
	opVPGATHERQD*,
	opVPGATHERQQ*,
	opVPHADDBD*,
	opVPHADDBQ*,
	opVPHADDBW*,
	opVPHADDD*,
	opVPHADDDQ*,
	opVPHADDSW*,
	opVPHADDUBD*,
	opVPHADDUBQ*,
	opVPHADDUBW*,
	opVPHADDUDQ*,
	opVPHADDUWD*,
	opVPHADDUWQ*,
	opVPHADDW*,
	opVPHADDWD*,
	opVPHADDWQ*,
	opVPHMINPOSUW*,
	opVPHSUBBW*,
	opVPHSUBD*,
	opVPHSUBDQ*,
	opVPHSUBSW*,
	opVPHSUBW*,
	opVPHSUBWD*,
	opVPINSRB*,
	opVPINSRD*,
	opVPINSRQ*,
	opVPINSRW*,
	opVPMACSDD*,
	opVPMACSDQH*,
	opVPMACSDQL*,
	opVPMACSSDD*,
	opVPMACSSDQH*,
	opVPMACSSDQL*,
	opVPMACSSWD*,
	opVPMACSSWW*,
	opVPMACSWD*,
	opVPMACSWW*,
	opVPMADCSSWD*,
	opVPMADDUBSW*,
	opVPMADDWD*,
	opVPMASKMOVD*,
	opVPMASKMOVQ*,
	opVPMAXSB*,
	opVPMAXSD*,
	opVPMAXSW*,
	opVPMAXUB*,
	opVPMAXUD*,
	opVPMAXUW*,
	opVPMINSB*,
	opVPMINSD*,
	opVPMINSW*,
	opVPMINUB*,
	opVPMINUD*,
	opVPMINUW*,
	opVPMOVSXBD*,
	opVPMOVSXBQ*,
	opVPMOVSXBW*,
	opVPMOVSXDQ*,
	opVPMOVSXWD*,
	opVPMOVSXWQ*,
	opVPMOVZXBD*,
	opVPMOVZXBQ*,
	opVPMOVZXBW*,
	opVPMOVZXDQ*,
	opVPMOVZXWD*,
	opVPMOVZXWQ*,
	opVPMULDQ*,
	opVPMULHRSW*,
	opVPMULHUW*,
	opVPMULHW*,
	opVPMULLD*,
	opVPMULLW*,
	opVPMULUDQ*,
	opVPOR*,
	opVPPERM*,
	opVPROTB*,
	opVPROTD*,
	opVPROTQ*,
	opVPROTW*,
	opVPSADBW*,
	opVPSHAB*,
	opVPSHAD*,
	opVPSHAQ*,
	opVPSHAW*,
	opVPSHLB*,
	opVPSHLD*,
	opVPSHLQ*,
	opVPSHLW*,
	opVPSHUFB*,
	opVPSHUFD*,
	opVPSHUFHW*,
	opVPSHUFLW*,
	opVPSIGNB*,
	opVPSIGND*,
	opVPSIGNW*,
	opVPSLLD*,
	opVPSLLDQ*,
	opVPSLLQ*,
	opVPSLLVD*,
	opVPSLLVQ*,
	opVPSLLW*,
	opVPSRAD*,
	opVPSRAVD*,
	opVPSRAW*,
	opVPSRLD*,
	opVPSRLDQ*,
	opVPSRLQ*,
	opVPSRLVD*,
	opVPSRLVQ*,
	opVPSRLW*,
	opVPSUBB*,
	opVPSUBD*,
	opVPSUBQ*,
	opVPSUBSB*,
	opVPSUBSW*,
	opVPSUBUSB*,
	opVPSUBUSW*,
	opVPSUBW*,
	opVPTEST*,
	opVPUNPCKHBW*,
	opVPUNPCKHDQ*,
	opVPUNPCKHQDQ*,
	opVPUNPCKHWD*,
	opVPUNPCKLBW*,
	opVPUNPCKLDQ*,
	opVPUNPCKLQDQ*,
	opVPUNPCKLWD*,
	opVPXOR*,
	opVRCPPS*,
	opVRCPSS*,
	opVROUNDPD*,
	opVROUNDPS*,
	opVROUNDSD*,
	opVROUNDSS*,
	opVRSQRTPS*,
	opVRSQRTSS*,
	opVSHUFPD*,
	opVSHUFPS*,
	opVSQRTPD*,
	opVSQRTPS*,
	opVSQRTSD*,
	opVSQRTSS*,
	opVSTMXCSR*,
	opVSUBPD*,
	opVSUBPS*,
	opVSUBSD*,
	opVSUBSS*,
	opVTESTPD*,
	opVTESTPS*,
	opVUCOMISD*,
	opVUCOMISS*,
	opVUNPCKHPD*,
	opVUNPCKHPS*,
	opVUNPCKLPD*,
	opVUNPCKLPS*,
	opVXORPD*,
	opVXORPS*,
	opVZEROALL*,
	opVZEROUPPER*

	: LONGINT

	(*
		FoxProgTools.Enum -l=8 -e
			opCode
			modRMExtension
			modRMBoth
			cb cw cd cp
			ib iw id iq
			rb rw rd rq
			mem64Operand mem128Operand
			fpStackOperand
			directMemoryOffset
		~
	*)
CONST
	(* opcode flags, cf [AMD:3], pp. 39-40 *)
	opCode*= 0; modRMExtension*= 1; modRMBoth*= 2; cb*= 3; cw*= 4; cd*= 5; cp*= 6; ib*= 7;
	iw*= 8; id*= 9; iq*= 10; rb*= 11; rw*= 12; rd*= 13; rq*= 14; mem64Operand*= 15;
	mem128Operand*= 16; fpStackOperand*= 17; directMemoryOffset*= 18;
	Src1Prefix* = 19; Src2Prefix* = 20; CountPrefix*= 21; DestPrefix*=22; RXB*=23;

TYPE
	Name = ARRAY 20 OF CHAR;
	OperandType* = SHORTINT;
	CPUOptions*= SET;
	Code*=CHAR; (* should be unsigned -- for emitter *)

	Instruction* = RECORD
		code-: ARRAY maxCodeLength OF Code; (* for the encoding cd. InitInstructions.Encode *)

		operands-: ARRAY maxNumberOperands OF OperandType;

		bitwidthOptions-: SET;
		cpuOptions-: SET;
	END;

	Mnemonic* = RECORD
		name-: ARRAY maxMnemonicNameLength OF CHAR;
		firstInstruction-, lastInstruction-: LONGINT;
	END;

	CPUType* = RECORD
		name-: Name;
		cpuOptions-: SET;
	END;

	Register*  = RECORD
		name-: Name; (* name for debug output and for an assembler *)
		type-: OperandType; (* can be one of reg8, reg16, reg32, reg64, CRn, DRn, segReg, mmx, xmm, sti
								the particular value of reg8 ... sti does not have a meaning *)
		index-: SHORTINT; (* this index has a meaning for instruction encoding, it is the register index used in the instruction *)
		sizeInBytes-: SHORTINT; (* size in bytes *)
	END;

VAR
	(* repository *)
	mnemonics-: ARRAY maxNumberMnemonics OF Mnemonic;
	numberMnemonics: LONGINT;

	instructions-: ARRAY maxNumberInstructions OF Instruction;
	numberInstructions: LONGINT;

	registers-: ARRAY numberRegisters OF Register;
	registersByClass-: ARRAY sti+1 OF ARRAY 17 OF LONGINT;

	cpus-: ARRAY maxCPUs OF CPUType;
	cpuCount: LONGINT;

	(* perform a binary search for the index of the specified mnemonic *)
	PROCEDURE FindMnemonic* (CONST mnem: ARRAY OF CHAR): LONGINT;
	VAR l, r, m: LONGINT;
	BEGIN
		l := 0;
		r := numberMnemonics;
		WHILE l # r DO
			m := (l + r) DIV 2;
			IF mnem < mnemonics[m].name THEN r := m;
			ELSIF mnem > mnemonics[m].name THEN l := m + 1;
			ELSE RETURN m;
			END
		END;
		RETURN none;
	END FindMnemonic;

	(* search for the register name and return it's index *)
	PROCEDURE FindRegister* (CONST reg: ARRAY OF CHAR): LONGINT;
	VAR i: LONGINT;
	BEGIN
		FOR i := 0 TO numberRegisters - 1 DO
			IF registers[i].name = reg THEN RETURN i END;
		END;
		RETURN none;
	END FindRegister;

	PROCEDURE RegisterType*(regNumber: LONGINT): OperandType;
	BEGIN IF regNumber = none THEN RETURN none ELSE RETURN registers[regNumber].type END
	END RegisterType;

	PROCEDURE RegisterIndex*(regNumber: LONGINT): SHORTINT;
	BEGIN IF regNumber = none THEN RETURN none ELSE RETURN registers[regNumber].index END
	END RegisterIndex;

	(* search for the CPU name and return it's index *)
	PROCEDURE FindCPU* (CONST cpu: ARRAY OF CHAR): LONGINT;
	VAR i: LONGINT;
	BEGIN
		FOR i := 0 TO cpuCount - 1 DO
			IF cpus[i].name = cpu THEN RETURN i END;
		END;
		RETURN none;
	END FindCPU;

				PROCEDURE StringToOperand(CONST name: ARRAY OF CHAR): SHORTINT;
				BEGIN
					IF name = "" THEN RETURN none
					ELSIF name = "1" THEN RETURN one;
					ELSIF name = "3" THEN RETURN three;
					ELSIF name = "reg8" THEN RETURN reg8;
					ELSIF name = "reg16" THEN RETURN reg16;
					ELSIF name = "reg32" THEN RETURN reg32;
					ELSIF name = "reg64" THEN RETURN reg64;
					ELSIF name = "reg" THEN RETURN reg3264;
					ELSIF name = "CRn" THEN RETURN CRn
					ELSIF name = "DRn" THEN RETURN DRn
					ELSIF name = "segReg" THEN RETURN segReg
					ELSIF name = "mmx" THEN RETURN mmx
					ELSIF name = "xmm" THEN RETURN xmm
					ELSIF name = "mem" THEN RETURN mem
					ELSIF name = "imm" THEN RETURN imm
					ELSIF name = "ioffset" THEN RETURN ioffset
					ELSIF name = "pntr1616" THEN RETURN pntr1616
					ELSIF name = "pntr1632" THEN RETURN pntr1632
					ELSIF name = "AL" THEN RETURN AL;
					ELSIF name = "AX" THEN RETURN AX;
					ELSIF name = "CL" THEN RETURN CL;
					ELSIF name = "CR8" THEN RETURN CR8;
					ELSIF name = "CS" THEN RETURN CS;
					ELSIF name = "DS" THEN RETURN DS;
					ELSIF name = "DX" THEN RETURN DX;
					ELSIF name = "EAX" THEN RETURN EAX;
					ELSIF name = "ECX" THEN RETURN ECX;
					ELSIF name = "ES" THEN RETURN ES;
					ELSIF name = "FS" THEN RETURN FS;
					ELSIF name = "GS" THEN RETURN GS;
					ELSIF name = "RAX" THEN RETURN RAX;
					ELSIF name = "SS" THEN RETURN SS;
					ELSIF name = "rAX" THEN RETURN rAX;
					ELSIF name = "ST(0)" THEN RETURN st0;
					ELSIF name = "ST(i)" THEN RETURN sti;
					ELSIF name = "imm16" THEN RETURN imm16
					ELSIF name = "imm32" THEN RETURN imm32;
					ELSIF name = "imm64" THEN RETURN imm64
					ELSIF name = "imm8" THEN RETURN imm8
					ELSIF name = "uimm16" THEN RETURN uimm16
					ELSIF name = "uimm32" THEN RETURN uimm32
					ELSIF name = "uimm8" THEN RETURN uimm8
					ELSIF name = "simm16" THEN RETURN simm16
					ELSIF name = "simm32" THEN RETURN simm32
					ELSIF name = "simm8" THEN RETURN simm8
					ELSIF name = "mem256" THEN RETURN mem256
					ELSIF name = "mem128" THEN RETURN mem128
					ELSIF name = "mem16" THEN RETURN mem16
					ELSIF name = "mem32" THEN RETURN mem32
					ELSIF name = "mem64" THEN RETURN mem64
					ELSIF name = "mem8" THEN RETURN mem8
					ELSIF name = "moffset16" THEN RETURN moffset16
					ELSIF name = "moffset32" THEN RETURN moffset32
					ELSIF name = "moffset64" THEN RETURN moffset64
					ELSIF name = "moffset8" THEN RETURN moffset8
					ELSIF name = "rel16off" THEN RETURN rel16off
					ELSIF name = "rel32off" THEN RETURN rel32off
					ELSIF name = "rel8off" THEN RETURN rel8off
					ELSIF name = "reg/mem8" THEN RETURN regmem8;
					ELSIF name = "reg/mem16" THEN RETURN regmem16;
					ELSIF name = "reg/mem32" THEN RETURN regmem32;
					ELSIF name = "reg32/mem32" THEN RETURN regmem32;
					ELSIF name = "reg32/mem16" THEN RETURN reg32mem16;
					ELSIF name = "reg/mem64" THEN RETURN regmem64;
					ELSIF name = "reg64/mem64" THEN RETURN regmem64;
					ELSIF name = "mem14/28env" THEN RETURN mem;
					ELSIF name = "mem16&mem16" THEN RETURN mem;
					ELSIF name = "mem32&mem32" THEN RETURN mem;
					ELSIF name = "mem16:16" THEN RETURN mem;
					ELSIF name = "mem16:32" THEN RETURN mem;
					ELSIF name = "mem16:64" THEN RETURN mem;
					ELSIF name = "mem512env" THEN RETURN mem;
					ELSIF name = "mem80dec" THEN RETURN mem;
					ELSIF name = "mem80real" THEN RETURN mem;
					ELSIF name = "mem94/108env" THEN RETURN mem;
					ELSIF name = "mem2env" THEN RETURN mem16;
					ELSIF name = "xmm0" THEN RETURN xmm;
					ELSIF name = "xmm1" THEN RETURN xmm;
					ELSIF name = "xmm2" THEN RETURN xmm;
					ELSIF name = "xmm3" THEN RETURN xmm;
					ELSIF name = "xmm4" THEN RETURN xmm;
					ELSIF name = "xmm/mem32" THEN RETURN xmmmem32;
					ELSIF name = "xmm/mem64" THEN RETURN xmmmem64;
					ELSIF name = "xmm/mem128" THEN RETURN xmmmem128;
					ELSIF name = "xmm1/mem32" THEN RETURN xmmmem32;
					ELSIF name = "xmm1/mem64" THEN RETURN xmmmem64;
					ELSIF name = "xmm1/mem128" THEN RETURN xmmmem128;
					ELSIF name = "xmm2/mem8" THEN RETURN xmmmem8;
					ELSIF name = "xmm2/mem16" THEN RETURN xmmmem16;
					ELSIF name = "xmm2/mem32" THEN RETURN xmmmem32;
					ELSIF name = "xmm2/mem64" THEN RETURN xmmmem64;
					ELSIF name = "xmm2/mem128" THEN RETURN xmmmem128;
					ELSIF name = "xmm2/mem256" THEN RETURN xmmmem256;
					ELSIF name = "xmm2/m64" THEN RETURN xmmmem64;
					ELSIF name = "xmm2/m128" THEN RETURN xmmmem128;
					ELSIF name = "xmm3/mem32" THEN RETURN xmmmem32;
					ELSIF name = "xmm3/mem64" THEN RETURN xmmmem64;
					ELSIF name = "xmm3/mem128" THEN RETURN xmmmem128;
					ELSIF name = "xmm4/mem32" THEN RETURN xmmmem32;
					ELSIF name = "xmm4/mem64" THEN RETURN xmmmem64;
					ELSIF name = "xmm4/mem128" THEN RETURN xmmmem128;
					ELSIF name = "mmx/mem64" THEN RETURN mmxmem64;
					ELSIF name = "mmx1" THEN RETURN mmx;
					ELSIF name = "mmx2" THEN RETURN mmx;
					ELSIF name = "mmx1/mem64" THEN RETURN mmxmem64;
					ELSIF name = "mmx2/mem32" THEN RETURN mmxmem32;
					ELSIF name = "mmx2/mem64" THEN RETURN mmxmem64;
					ELSIF name = "pntr16:16" THEN RETURN pntr1616;
					ELSIF name = "pntr16:32" THEN RETURN pntr1632;
					ELSIF name = "mem16int" THEN RETURN mem16;
					ELSIF name = "mem32int" THEN RETURN mem32;
					ELSIF name = "mem32real" THEN RETURN mem32;
					ELSIF name = "mem64int" THEN RETURN mem64;
					ELSIF name = "mem64real" THEN RETURN mem64;
					ELSIF name = "ymm" THEN RETURN ymm;
					ELSIF name = "ymm0" THEN RETURN ymm;
					ELSIF name = "ymm1" THEN RETURN ymm;
					ELSIF name = "ymm2" THEN RETURN ymm;
					ELSIF name = "ymm3" THEN RETURN ymm;
					ELSIF name = "ymm4" THEN RETURN ymm;
					ELSIF name = "ymm1/mem256" THEN RETURN ymmmem256;
					ELSIF name = "ymm1/m256" THEN RETURN ymmmem256;
					ELSIF name = "ymm2/mem256" THEN RETURN ymmmem256;
					ELSIF name = "ymm2/m256" THEN RETURN ymmmem256;
					ELSIF name = "ymm3/mem256" THEN RETURN ymmmem256;
					ELSIF name = "ymm1/mem128" THEN RETURN ymmmem128;
					ELSIF name = "ymm1/m128" THEN RETURN ymmmem128;
					ELSIF name = "ymm2/mem128" THEN RETURN ymmmem128;
					ELSIF name = "ymm2/m128" THEN RETURN ymmmem128;
					ELSIF name = "ymm3/mem128" THEN RETURN ymmmem128;
					ELSIF name = "ymm4/mem256" THEN RETURN ymmmem256;
					ELSIF name = "vm32x" THEN RETURN vm32x
					ELSIF name = "vm32y" THEN RETURN vm32y
					ELSIF name = "vm64x" THEN RETURN vm64x
					ELSIF name = "vm64y" THEN RETURN vm64y
					ELSIF name = "m2z" THEN RETURN m2z
					ELSE HALT(200)
					END;
				END StringToOperand;

			PROCEDURE ParseOperand(CONST op: ARRAY OF CHAR; VAR at: LONGINT): SHORTINT;
			VAR name: ARRAY 32 OF CHAR; i: LONGINT;
			BEGIN
				i := 0;
				WHILE(op[at] # 0X) & (op[at] # ",") DO
					name[i] := op[at];
					INC(i); INC(at);
				END;
				name[i] := 0X;
				IF op[at] = "," THEN INC(at) END;
				RETURN StringToOperand(name);
			END ParseOperand;

	(** setup instruction and mnemonic tables **)
	PROCEDURE InitInstructions;
	VAR

		PROCEDURE AddMnemonic(VAR op: LONGINT; CONST name: ARRAY OF CHAR);
		BEGIN
			op := numberMnemonics;
			COPY (name, mnemonics[op].name);
			mnemonics[op].firstInstruction := -1;
			INC(numberMnemonics);
		END AddMnemonic;

		PROCEDURE HexOrd (ch: CHAR): INTEGER;
		BEGIN
			IF ("0" <= ch) & (ch <= "9") THEN RETURN ORD (ch) - ORD ("0")
			ELSIF ("A" <= ch) & (ch <= "F") THEN RETURN ORD (CAP (ch)) - ORD ("A") + 10
			ELSE HALT(100);
			END
		END HexOrd;

		PROCEDURE Encode(CONST charcode: ARRAY OF CHAR; VAR code: ARRAY OF Code);
		(* simple encoding:
			code =
			{
			opCode number
			|modRMBoth
			|modRMExtension number
			|cb|cw|cd|cp
			|ib|iw|id|iq
			|m6|m1
			|+i|+o
			|rb|rw|rd|rq
			}
			none
			{
			none
			}

			all symbols 8 bit wide, numbers also 8 bits wide
		*)
		VAR i,k,length: SHORTINT; ch1,ch2: CHAR;
		BEGIN
			i := 0; k := 0;
			WHILE(charcode[2*i] # 0X) DO
				ch1 := charcode[2*i];
				ch2 := charcode[2*i+1];
				CASE ch1 OF
					'0'..'9','A'..'F':
						CASE ch2 OF '0'..'9','A'..'F':
							code[k] := CHR(opCode);INC(k);
							code[k] := CHR(HexOrd(ch1)*10H+HexOrd(ch2)); INC(k);
						ELSE HALT(100)
						END;
					|'/':
						CASE ch2 OF
							'r': code[k] := CHR(modRMBoth); INC(k);
							|'0'..'7': code[k] := CHR(modRMExtension); INC(k); code[k] := CHR(HexOrd(ch2)); INC(k);
						ELSE HALT(100)
						END;
					|'c':
						CASE ch2 OF
							'b': code[k] := CHR(cb); INC(k);
							|'w': code[k] := CHR(cw); INC(k);
							|'d': code[k] := CHR(cd); INC(k);
							|'p': code[k] := CHR(cp); INC(k);
						ELSE HALT(100)
						END;
					|'i':
						CASE ch2 OF
							'b': code[k] := CHR(ib); INC(k);
							|'w': code[k] := CHR(iw); INC(k);
							|'d': code[k] := CHR(id); INC(k);
							|'q': code[k] := CHR(iq); INC(k);
						ELSE HALT(100)
						END;
					|'m':
						CASE ch2 OF
							'6': code[k] := CHR(mem64Operand); INC(k);
							|'1': code[k] := CHR(mem128Operand); INC(k);
						ELSE HALT(100)
						END;
					|'+':
						CASE ch2 OF
							'i': code[k] := CHR(fpStackOperand); INC(k);
							|'o': code[k] := CHR(directMemoryOffset); INC(k);
						ELSE HALT(100)
						END;
					|'r':
						CASE ch2 OF
							'b': code[k] := CHR(rb); INC(k);
							|'w': code[k] := CHR(rw); INC(k);
							|'d': code[k] := CHR(rd); INC(k);
							|'q': code[k] := CHR(rq); INC(k);
						ELSE HALT(100)
						END;
					ELSE HALT(100)
					END;
				INC(i);
			END;
			length := k;
			WHILE(k < LEN(code)) DO
				code[k] := CHR(none);
				INC(k);
			END;
		END Encode;

		PROCEDURE EncodeV(CONST charcode: ARRAY OF CHAR; VAR code: ARRAY OF Code);
		(* simple encoding:
			code =
			{
			opCode number
			|modRMBoth
			|modRMExtension number
			|cb|cw|cd|cp
			|ib|iw|id|iq
			|m6|m1
			|+i|+o
			|rb|rw|rd|rq
			}
			none
			{
			none
			}

			all symbols 8 bit wide, numbers also 8 bits wide
		*)

			PROCEDURE GetCode(CONST charcode: ARRAY OF CHAR; VAR at: LONGINT; VAR cd: ARRAY OF CHAR): BOOLEAN;
			VAR i: LONGINT;
			BEGIN
				WHILE(charcode[at] = " ") DO INC(at) END;
				IF charcode[at] = 0X THEN RETURN FALSE END;
				i := 0;
				WHILE (charcode[at] # " ") & (charcode[at] # 0X) DO
					cd[i] := charcode[at];
					INC(i); INC(at);
				END;
				cd[i] := 0X;
				RETURN TRUE;
			END GetCode;

		VAR i,k,length: SHORTINT; ch1,ch2: CHAR; cdc: ARRAY 32 OF CHAR; at,mul,val: LONGINT;
		BEGIN
			i := 0; k := 0; at := 0;
			WHILE(GetCode(charcode,at,cdc)) DO
				ch1 := cdc[0];
				ch2 := cdc[1];
				IF (ch2 = ".") & ((ch1="0") OR (ch1="1") OR (ch1="X")) THEN
					mul := 80H;
					val := 0;
					i := 0;
					code[k] := CHR(opCode);
					WHILE (cdc[i] # 0X) DO
						IF (cdc[i] ="0") OR (cdc[i]="X") THEN
							mul := mul DIV 2;
						ELSIF cdc[i] = "1" THEN
							INC(val, mul);
							mul := mul DIV 2;
						ELSIF cdc[i] = "." (* next *) THEN
						ELSIF cdc[i] = "c" THEN
							INC(i); ASSERT(cdc[i] ="o");
							INC(i); ASSERT(cdc[i] ="u");
							INC(i); ASSERT(cdc[i] ="n");
							INC(i); ASSERT(cdc[i] ="t");
							code[k] := CHR(CountPrefix);
							mul := mul DIV 10H;
						ELSIF cdc[i] = "d" THEN
							INC(i); ASSERT(cdc[i] ="e");
							INC(i); ASSERT(cdc[i] ="s");
							INC(i); ASSERT(cdc[i] ="t");
							code[k] := CHR(DestPrefix);
							mul := mul DIV 10H;
						ELSIF cdc[i] = "s" THEN
							INC(i); ASSERT(cdc[i] ="r");
							INC(i); ASSERT(cdc[i] ="c");
							code[k] := CHR(Src1Prefix);
							ASSERT(mul = 64);
							IF (cdc[i+1] = "1") THEN
								INC(i);
							ELSIF (cdc[i+1] = "2") THEN
								code[k] := CHR(Src2Prefix);
								INC(i);
							END;
							mul := mul DIV 10H;
						ELSE HALT(100);
						END;
						INC(i);
					END;
					INC(k);
					code[k] := CHR(val); INC(k);
				ELSIF (ch1="R") THEN
					code[k] := CHR(RXB); INC(k);
					IF (cdc = "RXB.00001") OR  (cdc ="RXB.01") THEN
						code[k] := CHR(1);
					ELSIF (cdc ="RXB.00011") OR (cdc = "RXB.03") THEN
						code[k] := CHR(3);
					ELSIF (cdc ="RXB.00010") OR (cdc = "RXB.2") OR (cdc = "RXB.02") THEN
						code[k] := CHR(2);
					ELSIF (cdc ="RXB.01000") OR (cdc ="RXB.08") THEN
						code[k] := CHR(8);
					ELSIF cdc ="RXB.09" THEN
						code[k] := CHR(9);
					ELSE HALT(100)
					END;
					INC(k);
				ELSE
				CASE ch1 OF
					'0'..'9','A'..'F':
						CASE ch2 OF '0'..'9','A'..'F':
							code[k] := CHR(opCode);INC(k);
							code[k] := CHR(HexOrd(ch1)*10H+HexOrd(ch2)); INC(k);
						ELSE HALT(100)
						END;
					|'/':
						CASE ch2 OF
							'r': code[k] := CHR(modRMBoth); INC(k);
							|'0'..'7': code[k] := CHR(modRMExtension); INC(k); code[k] := CHR(HexOrd(ch2)); INC(k);
						ELSE
							IF cdc = "/imm8" THEN
								(*todo*)
							ELSIF cdc = "/is4" THEN
								(*todo*)
							ELSIF cdc = "/ib" THEN
								code[k] := CHR(ib); INC(k);
							ELSE
								HALT(100)
							END;
						END;
					|'c':
						CASE ch2 OF
							'b': code[k] := CHR(cb); INC(k);
							|'w': code[k] := CHR(cw); INC(k);
							|'d': code[k] := CHR(cd); INC(k);
							|'p': code[k] := CHR(cp); INC(k);
						ELSE HALT(100)
						END;
					|'i':
						CASE ch2 OF
							'b': code[k] := CHR(ib); INC(k);
							|'w': code[k] := CHR(iw); INC(k);
							|'d': code[k] := CHR(id); INC(k);
							|'q': code[k] := CHR(iq); INC(k);
						ELSE
							IF cdc = "is4" THEN
								(*todo*)
							ELSIF cdc = "is5" THEN
								(*todo*)
							ELSE
							HALT(100)
							END;
						END;
					|'m':
						CASE ch2 OF
							'6': code[k] := CHR(mem64Operand); INC(k);
							|'1': code[k] := CHR(mem128Operand); INC(k);
						ELSE HALT(100)
						END;
					|'+':
						CASE ch2 OF
							'i': code[k] := CHR(fpStackOperand); INC(k);
							|'o': code[k] := CHR(directMemoryOffset); INC(k);
						ELSE HALT(100)
						END;
					|'r':
						CASE ch2 OF
							'b': code[k] := CHR(rb); INC(k);
							|'w': code[k] := CHR(rw); INC(k);
							|'d': code[k] := CHR(rd); INC(k);
							|'q': code[k] := CHR(rq); INC(k);
						ELSE HALT(100)
						END;
					ELSE HALT(100)
					END;
				INC(i);
			END;
			END;
			length := k;
			WHILE(k < LEN(code)) DO
				code[k] := CHR(none);
				INC(k);
			END;
		END EncodeV;

		PROCEDURE AddInstructionV(mnemonic: LONGINT; CONST operands, code: ARRAY OF CHAR);
		VAR i, at: LONGINT; name: ARRAY 32 OF CHAR;
		BEGIN
			i := 0; at := 0;
			WHILE (i<maxNumberOperands) DO
				instructions[numberInstructions].operands[i] := ParseOperand(operands,at);
				INC(i);
			END;
			ASSERT(operands[at] = 0X); (* all operands parsed *)

			EncodeV(code,instructions[numberInstructions].code);

			COPY(mnemonics[mnemonic].name,name);
			IF mnemonics[mnemonic].firstInstruction = -1 THEN
				mnemonics[mnemonic].firstInstruction := numberInstructions;
				mnemonics[mnemonic].lastInstruction := numberInstructions;
			ELSE
				ASSERT(mnemonics[mnemonic].lastInstruction = numberInstructions-1);
				mnemonics[mnemonic].lastInstruction := numberInstructions;
			END;
			INC(numberInstructions);
		END AddInstructionV;

		PROCEDURE AddInstruction(mnemonic: LONGINT; CONST op,code: ARRAY OF CHAR; bitwidthOptions, cpuOptions: SET);
		VAR i: SHORTINT; at: LONGINT;

		BEGIN
			i := 0; at := 0;
			WHILE (i<maxNumberOperands) DO
				instructions[numberInstructions].operands[i] := ParseOperand(op,at);
				INC(i);
			END;
			Encode(code,instructions[numberInstructions].code);

			instructions[numberInstructions].bitwidthOptions := bitwidthOptions;
			instructions[numberInstructions].cpuOptions := cpuOptions;

			IF mnemonics[mnemonic].firstInstruction = -1 THEN
				mnemonics[mnemonic].firstInstruction := numberInstructions;
				mnemonics[mnemonic].lastInstruction := numberInstructions;
			ELSE
				ASSERT(mnemonics[mnemonic].lastInstruction = numberInstructions-1);
				mnemonics[mnemonic].lastInstruction := numberInstructions;
			END;

			INC(numberInstructions);
		END AddInstruction;

	(* the following has partially been generated with
		FoxProgTools.ParseAMDInstructionSet FoxInstructionSetAMD64TabSeperated.txt ~

		Do not change or re-order. The alphabetical order is of importance
	*)

	BEGIN
		numberMnemonics := 0;
		numberInstructions := 0;

		AddMnemonic(opAAA, "AAA");
		AddMnemonic(opAAD, "AAD");
		AddMnemonic(opAAM, "AAM");
		AddMnemonic(opAAS, "AAS");
		AddMnemonic(opADC, "ADC");
		AddMnemonic(opADD, "ADD");
		AddMnemonic(opADDPD, "ADDPD");
		AddMnemonic(opADDPS, "ADDPS");
		AddMnemonic(opADDSD, "ADDSD");
		AddMnemonic(opADDSS, "ADDSS");
		AddMnemonic(opADDSUBPD, "ADDSUBPD");
		AddMnemonic(opADDSUBPS, "ADDSUBPS");
		AddMnemonic(opAND, "AND");
		AddMnemonic(opANDNPD, "ANDNPD");
		AddMnemonic(opANDNPS, "ANDNPS");
		AddMnemonic(opANDPD, "ANDPD");
		AddMnemonic(opANDPS, "ANDPS");
		AddMnemonic(opARPL, "ARPL");
		AddMnemonic(opBOUND, "BOUND");
		AddMnemonic(opBSF, "BSF");
		AddMnemonic(opBSR, "BSR");
		AddMnemonic(opBSWAP, "BSWAP");
		AddMnemonic(opBT, "BT");
		AddMnemonic(opBTC, "BTC");
		AddMnemonic(opBTR, "BTR");
		AddMnemonic(opBTS, "BTS");
		AddMnemonic(opCALL, "CALL");
		AddMnemonic(opCALLFAR, "CALLFAR");
		AddMnemonic(opCBW, "CBW");
		AddMnemonic(opCDQ, "CDQ");
		AddMnemonic(opCDQE, "CDQE");
		AddMnemonic(opCLC, "CLC");
		AddMnemonic(opCLD, "CLD");
		AddMnemonic(opCLFLUSH, "CLFLUSH");
		AddMnemonic(opCLGI, "CLGI");
		AddMnemonic(opCLI, "CLI");
		AddMnemonic(opCLTS, "CLTS");
		AddMnemonic(opCMC, "CMC");
		AddMnemonic(opCMOVA, "CMOVA");
		AddMnemonic(opCMOVAE, "CMOVAE");
		AddMnemonic(opCMOVB, "CMOVB");
		AddMnemonic(opCMOVBE, "CMOVBE");
		AddMnemonic(opCMOVC, "CMOVC");
		AddMnemonic(opCMOVE, "CMOVE");
		AddMnemonic(opCMOVG, "CMOVG");
		AddMnemonic(opCMOVGE, "CMOVGE");
		AddMnemonic(opCMOVL, "CMOVL");
		AddMnemonic(opCMOVLE, "CMOVLE");
		AddMnemonic(opCMOVNA, "CMOVNA");
		AddMnemonic(opCMOVNAE, "CMOVNAE");
		AddMnemonic(opCMOVNB, "CMOVNB");
		AddMnemonic(opCMOVNBE, "CMOVNBE");
		AddMnemonic(opCMOVNC, "CMOVNC");
		AddMnemonic(opCMOVNE, "CMOVNE");
		AddMnemonic(opCMOVNG, "CMOVNG");
		AddMnemonic(opCMOVNGE, "CMOVNGE");
		AddMnemonic(opCMOVNL, "CMOVNL");
		AddMnemonic(opCMOVNLE, "CMOVNLE");
		AddMnemonic(opCMOVNO, "CMOVNO");
		AddMnemonic(opCMOVNP, "CMOVNP");
		AddMnemonic(opCMOVNS, "CMOVNS");
		AddMnemonic(opCMOVNZ, "CMOVNZ");
		AddMnemonic(opCMOVO, "CMOVO");
		AddMnemonic(opCMOVP, "CMOVP");
		AddMnemonic(opCMOVPE, "CMOVPE");
		AddMnemonic(opCMOVPO, "CMOVPO");
		AddMnemonic(opCMOVS, "CMOVS");
		AddMnemonic(opCMOVZ, "CMOVZ");
		AddMnemonic(opCMP, "CMP");
		AddMnemonic(opCMPPD, "CMPPD");
		AddMnemonic(opCMPPS, "CMPPS");
		AddMnemonic(opCMPS, "CMPS");
		AddMnemonic(opCMPSB, "CMPSB");
		AddMnemonic(opCMPSD, "CMPSD");
		AddMnemonic(opCMPSQ, "CMPSQ");
		AddMnemonic(opCMPSS, "CMPSS");
		AddMnemonic(opCMPSW, "CMPSW");
		AddMnemonic(opCMPXCHG, "CMPXCHG");
		AddMnemonic(opCMPXCHG16B, "CMPXCHG16B");
		AddMnemonic(opCMPXCHG8B, "CMPXCHG8B");
		AddMnemonic(opCOMISD, "COMISD");
		AddMnemonic(opCOMISS, "COMISS");
		AddMnemonic(opCPUID, "CPUID");
		AddMnemonic(opCQO, "CQO");
		AddMnemonic(opCVTDQ2PD, "CVTDQ2PD");
		AddMnemonic(opCVTDQ2PS, "CVTDQ2PS");
		AddMnemonic(opCVTPD2DQ, "CVTPD2DQ");
		AddMnemonic(opCVTPD2PI, "CVTPD2PI");
		AddMnemonic(opCVTPD2PS, "CVTPD2PS");
		AddMnemonic(opCVTPI2PD, "CVTPI2PD");
		AddMnemonic(opCVTPI2PS, "CVTPI2PS");
		AddMnemonic(opCVTPS2DQ, "CVTPS2DQ");
		AddMnemonic(opCVTPS2PD, "CVTPS2PD");
		AddMnemonic(opCVTPS2PI, "CVTPS2PI");
		AddMnemonic(opCVTSD2SI, "CVTSD2SI");
		AddMnemonic(opCVTSD2SS, "CVTSD2SS");
		AddMnemonic(opCVTSI2SD, "CVTSI2SD");
		AddMnemonic(opCVTSI2SS, "CVTSI2SS");
		AddMnemonic(opCVTSS2SD, "CVTSS2SD");
		AddMnemonic(opCVTSS2SI, "CVTSS2SI");
		AddMnemonic(opCVTTPD2DQ, "CVTTPD2DQ");
		AddMnemonic(opCVTTPD2PI, "CVTTPD2PI");
		AddMnemonic(opCVTTPS2DQ, "CVTTPS2DQ");
		AddMnemonic(opCVTTPS2PI, "CVTTPS2PI");
		AddMnemonic(opCVTTSD2SI, "CVTTSD2SI");
		AddMnemonic(opCVTTSS2SI, "CVTTSS2SI");
		AddMnemonic(opCWD, "CWD");
		AddMnemonic(opCWDE, "CWDE");
		AddMnemonic(opDAA, "DAA");
		AddMnemonic(opDAS, "DAS");
		AddMnemonic(opDEC, "DEC");
		AddMnemonic(opDIV, "DIV");
		AddMnemonic(opDIVPD, "DIVPD");
		AddMnemonic(opDIVPS, "DIVPS");
		AddMnemonic(opDIVSD, "DIVSD");
		AddMnemonic(opDIVSS, "DIVSS");
		AddMnemonic(opEMMS, "EMMS");
		AddMnemonic(opENTER, "ENTER");
		AddMnemonic(opF2XM1, "F2XM1");
		AddMnemonic(opFABS, "FABS");
		AddMnemonic(opFADD, "FADD");
		AddMnemonic(opFADDP, "FADDP");
		AddMnemonic(opFBLD, "FBLD");
		AddMnemonic(opFBSTP, "FBSTP");
		AddMnemonic(opFCHS, "FCHS");
		AddMnemonic(opFCLEX, "FCLEX");
		AddMnemonic(opFCMOVB, "FCMOVB");
		AddMnemonic(opFCMOVBE, "FCMOVBE");
		AddMnemonic(opFCMOVE, "FCMOVE");
		AddMnemonic(opFCMOVNB, "FCMOVNB");
		AddMnemonic(opFCMOVNBE, "FCMOVNBE");
		AddMnemonic(opFCMOVNE, "FCMOVNE");
		AddMnemonic(opFCMOVNU, "FCMOVNU");
		AddMnemonic(opFCMOVU, "FCMOVU");
		AddMnemonic(opFCOM, "FCOM");
		AddMnemonic(opFCOMI, "FCOMI");
		AddMnemonic(opFCOMIP, "FCOMIP");
		AddMnemonic(opFCOMP, "FCOMP");
		AddMnemonic(opFCOMPP, "FCOMPP");
		AddMnemonic(opFCOS, "FCOS");
		AddMnemonic(opFDECSTP, "FDECSTP");
		AddMnemonic(opFDIV, "FDIV");
		AddMnemonic(opFDIVP, "FDIVP");
		AddMnemonic(opFDIVR, "FDIVR");
		AddMnemonic(opFDIVRP, "FDIVRP");
		AddMnemonic(opFEMMS, "FEMMS");
		AddMnemonic(opFFREE, "FFREE");
		AddMnemonic(opFIADD, "FIADD");
		AddMnemonic(opFICOM, "FICOM");
		AddMnemonic(opFICOMP, "FICOMP");
		AddMnemonic(opFIDIV, "FIDIV");
		AddMnemonic(opFIDIVR, "FIDIVR");
		AddMnemonic(opFILD, "FILD");
		AddMnemonic(opFIMUL, "FIMUL");
		AddMnemonic(opFINCSTP, "FINCSTP");
		AddMnemonic(opFINIT, "FINIT");
		AddMnemonic(opFIST, "FIST");
		AddMnemonic(opFISTP, "FISTP");
		AddMnemonic(opFISTTP, "FISTTP");
		AddMnemonic(opFISUB, "FISUB");
		AddMnemonic(opFISUBR, "FISUBR");
		AddMnemonic(opFLD, "FLD");
		AddMnemonic(opFLD1, "FLD1");
		AddMnemonic(opFLDCW, "FLDCW");
		AddMnemonic(opFLDENV, "FLDENV");
		AddMnemonic(opFLDL2E, "FLDL2E");
		AddMnemonic(opFLDL2T, "FLDL2T");
		AddMnemonic(opFLDLG2, "FLDLG2");
		AddMnemonic(opFLDLN2, "FLDLN2");
		AddMnemonic(opFLDPI, "FLDPI");
		AddMnemonic(opFLDZ, "FLDZ");
		AddMnemonic(opFMUL, "FMUL");
		AddMnemonic(opFMULP, "FMULP");
		AddMnemonic(opFNCLEX, "FNCLEX");
		AddMnemonic(opFNINIT, "FNINIT");
		AddMnemonic(opFNOP, "FNOP");
		AddMnemonic(opFNSAVE, "FNSAVE");
		AddMnemonic(opFNSTCW, "FNSTCW");
		AddMnemonic(opFNSTENV, "FNSTENV");
		AddMnemonic(opFNSTSW, "FNSTSW");
		AddMnemonic(opFPATAN, "FPATAN");
		AddMnemonic(opFPREM, "FPREM");
		AddMnemonic(opFPREM1, "FPREM1");
		AddMnemonic(opFPTAN, "FPTAN");
		AddMnemonic(opFRNDINT, "FRNDINT");
		AddMnemonic(opFRSTOR, "FRSTOR");
		AddMnemonic(opFSAVE, "FSAVE");
		AddMnemonic(opFSCALE, "FSCALE");
		AddMnemonic(opFSIN, "FSIN");
		AddMnemonic(opFSINCOS, "FSINCOS");
		AddMnemonic(opFSQRT, "FSQRT");
		AddMnemonic(opFST, "FST");
		AddMnemonic(opFSTCW, "FSTCW");
		AddMnemonic(opFSTENV, "FSTENV");
		AddMnemonic(opFSTP, "FSTP");
		AddMnemonic(opFSTSW, "FSTSW");
		AddMnemonic(opFSUB, "FSUB");
		AddMnemonic(opFSUBP, "FSUBP");
		AddMnemonic(opFSUBR, "FSUBR");
		AddMnemonic(opFSUBRP, "FSUBRP");
		AddMnemonic(opFTST, "FTST");
		AddMnemonic(opFUCOM, "FUCOM");
		AddMnemonic(opFUCOMI, "FUCOMI");
		AddMnemonic(opFUCOMIP, "FUCOMIP");
		AddMnemonic(opFUCOMP, "FUCOMP");
		AddMnemonic(opFUCOMPP, "FUCOMPP");
		AddMnemonic(opFWAIT, "FWAIT");
		AddMnemonic(opFXAM, "FXAM");
		AddMnemonic(opFXCH, "FXCH");
		AddMnemonic(opFXRSTOR, "FXRSTOR");
		AddMnemonic(opFXSAVE, "FXSAVE");
		AddMnemonic(opFXTRACT, "FXTRACT");
		AddMnemonic(opFYL2X, "FYL2X");
		AddMnemonic(opFYL2XP1, "FYL2XP1");
		AddMnemonic(opHADDPD, "HADDPD");
		AddMnemonic(opHADDPS, "HADDPS");
		AddMnemonic(opHLT, "HLT");
		AddMnemonic(opHSUBPD, "HSUBPD");
		AddMnemonic(opHSUBPS, "HSUBPS");
		AddMnemonic(opIDIV, "IDIV");
		AddMnemonic(opIMUL, "IMUL");
		AddMnemonic(opIN, "IN");
		AddMnemonic(opINC, "INC");
		AddMnemonic(opINS, "INS");
		AddMnemonic(opINSB, "INSB");
		AddMnemonic(opINSD, "INSD");
		AddMnemonic(opINSW, "INSW");
		AddMnemonic(opINT, "INT");
		AddMnemonic(opINT3, "INT3");
		AddMnemonic(opINTO, "INTO");
		AddMnemonic(opINVD, "INVD");
		AddMnemonic(opINVLPG, "INVLPG");
		AddMnemonic(opINVLPGA, "INVLPGA");
		AddMnemonic(opIRET, "IRET");
		AddMnemonic(opIRETD, "IRETD");
		AddMnemonic(opIRETQ, "IRETQ");
		AddMnemonic(opJA, "JA");
		AddMnemonic(opJAE, "JAE");
		AddMnemonic(opJB, "JB");
		AddMnemonic(opJBE, "JBE");
		AddMnemonic(opJC, "JC");
		AddMnemonic(opJCXZ, "JCXZ");
		AddMnemonic(opJE, "JE");
		AddMnemonic(opJECXZ, "JECXZ");
		AddMnemonic(opJG, "JG");
		AddMnemonic(opJGE, "JGE");
		AddMnemonic(opJL, "JL");
		AddMnemonic(opJLE, "JLE");
		AddMnemonic(opJMP, "JMP");
		AddMnemonic(opJMPFAR, "JMPFAR");
		AddMnemonic(opJNA, "JNA");
		AddMnemonic(opJNAE, "JNAE");
		AddMnemonic(opJNB, "JNB");
		AddMnemonic(opJNBE, "JNBE");
		AddMnemonic(opJNC, "JNC");
		AddMnemonic(opJNE, "JNE");
		AddMnemonic(opJNG, "JNG");
		AddMnemonic(opJNGE, "JNGE");
		AddMnemonic(opJNL, "JNL");
		AddMnemonic(opJNLE, "JNLE");
		AddMnemonic(opJNO, "JNO");
		AddMnemonic(opJNP, "JNP");
		AddMnemonic(opJNS, "JNS");
		AddMnemonic(opJNZ, "JNZ");
		AddMnemonic(opJO, "JO");
		AddMnemonic(opJP, "JP");
		AddMnemonic(opJPE, "JPE");
		AddMnemonic(opJPO, "JPO");
		AddMnemonic(opJRCXZ, "JRCXZ");
		AddMnemonic(opJS, "JS");
		AddMnemonic(opJZ, "JZ");
		AddMnemonic(opLAHF, "LAHF");
		AddMnemonic(opLAR, "LAR");
		AddMnemonic(opLDDQU, "LDDQU");
		AddMnemonic(opLDMXCSR, "LDMXCSR");
		AddMnemonic(opLDS, "LDS");
		AddMnemonic(opLEA, "LEA");
		AddMnemonic(opLEAVE, "LEAVE");
		AddMnemonic(opLES, "LES");
		AddMnemonic(opLFENCE, "LFENCE");
		AddMnemonic(opLFS, "LFS");
		AddMnemonic(opLGDT, "LGDT");
		AddMnemonic(opLGS, "LGS");
		AddMnemonic(opLIDT, "LIDT");
		AddMnemonic(opLLDT, "LLDT");
		AddMnemonic(opLMSW, "LMSW");
		AddMnemonic(opLODS, "LODS");
		AddMnemonic(opLODSB, "LODSB");
		AddMnemonic(opLODSD, "LODSD");
		AddMnemonic(opLODSQ, "LODSQ");
		AddMnemonic(opLODSW, "LODSW");
		AddMnemonic(opLOOP, "LOOP");
		AddMnemonic(opLOOPE, "LOOPE");
		AddMnemonic(opLOOPNE, "LOOPNE");
		AddMnemonic(opLOOPNZ, "LOOPNZ");
		AddMnemonic(opLOOPZ, "LOOPZ");
		AddMnemonic(opLSL, "LSL");
		AddMnemonic(opLSS, "LSS");
		AddMnemonic(opLTR, "LTR");
		AddMnemonic(opMASKMOVDQU, "MASKMOVDQU");
		AddMnemonic(opMASKMOVQ, "MASKMOVQ");
		AddMnemonic(opMAXPD, "MAXPD");
		AddMnemonic(opMAXPS, "MAXPS");
		AddMnemonic(opMAXSD, "MAXSD");
		AddMnemonic(opMAXSS, "MAXSS");
		AddMnemonic(opMFENCE, "MFENCE");
		AddMnemonic(opMINPD, "MINPD");
		AddMnemonic(opMINPS, "MINPS");
		AddMnemonic(opMINSD, "MINSD");
		AddMnemonic(opMINSS, "MINSS");
		AddMnemonic(opMOV, "MOV");
		AddMnemonic(opMOVAPD, "MOVAPD");
		AddMnemonic(opMOVAPS, "MOVAPS");
		AddMnemonic(opMOVD, "MOVD");
		AddMnemonic(opMOVDDUP, "MOVDDUP");
		AddMnemonic(opMOVDQ2Q, "MOVDQ2Q");
		AddMnemonic(opMOVDQA, "MOVDQA");
		AddMnemonic(opMOVDQU, "MOVDQU");
		AddMnemonic(opMOVHLPS, "MOVHLPS");
		AddMnemonic(opMOVHPD, "MOVHPD");
		AddMnemonic(opMOVHPS, "MOVHPS");
		AddMnemonic(opMOVLHPS, "MOVLHPS");
		AddMnemonic(opMOVLPD, "MOVLPD");
		AddMnemonic(opMOVLPS, "MOVLPS");
		AddMnemonic(opMOVMSKPD, "MOVMSKPD");
		AddMnemonic(opMOVMSKPS, "MOVMSKPS");
		AddMnemonic(opMOVNTDQ, "MOVNTDQ");
		AddMnemonic(opMOVNTI, "MOVNTI");
		AddMnemonic(opMOVNTPD, "MOVNTPD");
		AddMnemonic(opMOVNTPS, "MOVNTPS");
		AddMnemonic(opMOVNTQ, "MOVNTQ");
		AddMnemonic(opMOVQ, "MOVQ");
		AddMnemonic(opMOVQ2DQ, "MOVQ2DQ");
		AddMnemonic(opMOVS, "MOVS");
		AddMnemonic(opMOVSB, "MOVSB");
		AddMnemonic(opMOVSD, "MOVSD");
		AddMnemonic(opMOVSHDUP, "MOVSHDUP");
		AddMnemonic(opMOVSLDUP, "MOVSLDUP");
		AddMnemonic(opMOVSQ, "MOVSQ");
		AddMnemonic(opMOVSS, "MOVSS");
		AddMnemonic(opMOVSW, "MOVSW");
		AddMnemonic(opMOVSX, "MOVSX");
		AddMnemonic(opMOVSXD, "MOVSXD");
		AddMnemonic(opMOVUPD, "MOVUPD");
		AddMnemonic(opMOVUPS, "MOVUPS");
		AddMnemonic(opMOVZX, "MOVZX");
		AddMnemonic(opMUL, "MUL");
		AddMnemonic(opMULPD, "MULPD");
		AddMnemonic(opMULPS, "MULPS");
		AddMnemonic(opMULSD, "MULSD");
		AddMnemonic(opMULSS, "MULSS");
		AddMnemonic(opNEG, "NEG");
		AddMnemonic(opNOP, "NOP");
		AddMnemonic(opNOT, "NOT");
		AddMnemonic(opOR, "OR");
		AddMnemonic(opORPD, "ORPD");
		AddMnemonic(opORPS, "ORPS");
		AddMnemonic(opOUT, "OUT");
		AddMnemonic(opOUTS, "OUTS");
		AddMnemonic(opOUTSB, "OUTSB");
		AddMnemonic(opOUTSD, "OUTSD");
		AddMnemonic(opOUTSW, "OUTSW");
		AddMnemonic(opPACKSSDW, "PACKSSDW");
		AddMnemonic(opPACKSSWB, "PACKSSWB");
		AddMnemonic(opPACKUSWB, "PACKUSWB");
		AddMnemonic(opPADDB, "PADDB");
		AddMnemonic(opPADDD, "PADDD");
		AddMnemonic(opPADDQ, "PADDQ");
		AddMnemonic(opPADDSB, "PADDSB");
		AddMnemonic(opPADDSW, "PADDSW");
		AddMnemonic(opPADDUSB, "PADDUSB");
		AddMnemonic(opPADDUSW, "PADDUSW");
		AddMnemonic(opPADDW, "PADDW");
		AddMnemonic(opPAND, "PAND");
		AddMnemonic(opPANDN, "PANDN");
		AddMnemonic(opPAUSE, "PAUSE");
		AddMnemonic(opPAVGB, "PAVGB");
		AddMnemonic(opPAVGUSB, "PAVGUSB");
		AddMnemonic(opPAVGW, "PAVGW");
		AddMnemonic(opPCMPEQB, "PCMPEQB");
		AddMnemonic(opPCMPEQD, "PCMPEQD");
		AddMnemonic(opPCMPEQW, "PCMPEQW");
		AddMnemonic(opPCMPGTB, "PCMPGTB");
		AddMnemonic(opPCMPGTD, "PCMPGTD");
		AddMnemonic(opPCMPGTW, "PCMPGTW");
		AddMnemonic(opPEXTRW, "PEXTRW");
		AddMnemonic(opPF2ID, "PF2ID");
		AddMnemonic(opPF2IW, "PF2IW");
		AddMnemonic(opPFACC, "PFACC");
		AddMnemonic(opPFADD, "PFADD");
		AddMnemonic(opPFCMPEQ, "PFCMPEQ");
		AddMnemonic(opPFCMPGE, "PFCMPGE");
		AddMnemonic(opPFCMPGT, "PFCMPGT");
		AddMnemonic(opPFMAX, "PFMAX");
		AddMnemonic(opPFMIN, "PFMIN");
		AddMnemonic(opPFMUL, "PFMUL");
		AddMnemonic(opPFNACC, "PFNACC");
		AddMnemonic(opPFPNACC, "PFPNACC");
		AddMnemonic(opPFRCP, "PFRCP");
		AddMnemonic(opPFRCPIT1, "PFRCPIT1");
		AddMnemonic(opPFRCPIT2, "PFRCPIT2");
		AddMnemonic(opPFRSQIT1, "PFRSQIT1");
		AddMnemonic(opPFRSQRT, "PFRSQRT");
		AddMnemonic(opPFSUB, "PFSUB");
		AddMnemonic(opPFSUBR, "PFSUBR");
		AddMnemonic(opPI2FD, "PI2FD");
		AddMnemonic(opPI2FW, "PI2FW");
		AddMnemonic(opPINSRW, "PINSRW");
		AddMnemonic(opPMADDWD, "PMADDWD");
		AddMnemonic(opPMAXSW, "PMAXSW");
		AddMnemonic(opPMAXUB, "PMAXUB");
		AddMnemonic(opPMINSW, "PMINSW");
		AddMnemonic(opPMINUB, "PMINUB");
		AddMnemonic(opPMOVMSKB, "PMOVMSKB");
		AddMnemonic(opPMULHRW, "PMULHRW");
		AddMnemonic(opPMULHUW, "PMULHUW");
		AddMnemonic(opPMULHW, "PMULHW");
		AddMnemonic(opPMULLW, "PMULLW");
		AddMnemonic(opPMULUDQ, "PMULUDQ");
		AddMnemonic(opPOP, "POP");
		AddMnemonic(opPOPA, "POPA");
		AddMnemonic(opPOPAD, "POPAD");
		AddMnemonic(opPOPAW, "POPAW");
		AddMnemonic(opPOPF, "POPF");
		AddMnemonic(opPOPFD, "POPFD");
		AddMnemonic(opPOPFQ, "POPFQ");
		AddMnemonic(opPOR, "POR");
		AddMnemonic(opPREFETCH, "PREFETCH");
		AddMnemonic(opPREFETCHNTA, "PREFETCHNTA");
		AddMnemonic(opPREFETCHT0, "PREFETCHT0");
		AddMnemonic(opPREFETCHT1, "PREFETCHT1");
		AddMnemonic(opPREFETCHT2, "PREFETCHT2");
		AddMnemonic(opPREFETCHW, "PREFETCHW");
		AddMnemonic(opPSADBW, "PSADBW");
		AddMnemonic(opPSHUFD, "PSHUFD");
		AddMnemonic(opPSHUFHW, "PSHUFHW");
		AddMnemonic(opPSHUFLW, "PSHUFLW");
		AddMnemonic(opPSHUFW, "PSHUFW");
		AddMnemonic(opPSLLD, "PSLLD");
		AddMnemonic(opPSLLDQ, "PSLLDQ");
		AddMnemonic(opPSLLQ, "PSLLQ");
		AddMnemonic(opPSLLW, "PSLLW");
		AddMnemonic(opPSRAD, "PSRAD");
		AddMnemonic(opPSRAW, "PSRAW");
		AddMnemonic(opPSRLD, "PSRLD");
		AddMnemonic(opPSRLDQ, "PSRLDQ");
		AddMnemonic(opPSRLQ, "PSRLQ");
		AddMnemonic(opPSRLW, "PSRLW");
		AddMnemonic(opPSUBB, "PSUBB");
		AddMnemonic(opPSUBD, "PSUBD");
		AddMnemonic(opPSUBQ, "PSUBQ");
		AddMnemonic(opPSUBSB, "PSUBSB");
		AddMnemonic(opPSUBSW, "PSUBSW");
		AddMnemonic(opPSUBUSB, "PSUBUSB");
		AddMnemonic(opPSUBUSW, "PSUBUSW");
		AddMnemonic(opPSUBW, "PSUBW");
		AddMnemonic(opPSWAPD, "PSWAPD");
		AddMnemonic(opPUNPCKHBW, "PUNPCKHBW");
		AddMnemonic(opPUNPCKHDQ, "PUNPCKHDQ");
		AddMnemonic(opPUNPCKHQDQ, "PUNPCKHQDQ");
		AddMnemonic(opPUNPCKHWD, "PUNPCKHWD");
		AddMnemonic(opPUNPCKLBW, "PUNPCKLBW");
		AddMnemonic(opPUNPCKLDQ, "PUNPCKLDQ");
		AddMnemonic(opPUNPCKLQDQ, "PUNPCKLQDQ");
		AddMnemonic(opPUNPCKLWD, "PUNPCKLWD");
		AddMnemonic(opPUSH, "PUSH");
		AddMnemonic(opPUSHA, "PUSHA");
		AddMnemonic(opPUSHAD, "PUSHAD");
		AddMnemonic(opPUSHF, "PUSHF");
		AddMnemonic(opPUSHFD, "PUSHFD");
		AddMnemonic(opPUSHFQ, "PUSHFQ");
		AddMnemonic(opPXOR, "PXOR");
		AddMnemonic(opRCL, "RCL");
		AddMnemonic(opRCPPS, "RCPPS");
		AddMnemonic(opRCPSS, "RCPSS");
		AddMnemonic(opRCR, "RCR");
		AddMnemonic(opRDMSR, "RDMSR");
		AddMnemonic(opRDPMC, "RDPMC");
		AddMnemonic(opRDTSC, "RDTSC");
		AddMnemonic(opRDTSCP, "RDTSCP");
		AddMnemonic(opRET, "RET");
		AddMnemonic(opRETF, "RETF");
		AddMnemonic(opROL, "ROL");
		AddMnemonic(opROR, "ROR");
		AddMnemonic(opRSM, "RSM");
		AddMnemonic(opRSQRTPS, "RSQRTPS");
		AddMnemonic(opRSQRTSS, "RSQRTSS");
		AddMnemonic(opSAHF, "SAHF");
		AddMnemonic(opSAL, "SAL");
		AddMnemonic(opSAR, "SAR");
		AddMnemonic(opSBB, "SBB");
		AddMnemonic(opSCAS, "SCAS");
		AddMnemonic(opSCASB, "SCASB");
		AddMnemonic(opSCASD, "SCASD");
		AddMnemonic(opSCASQ, "SCASQ");
		AddMnemonic(opSCASW, "SCASW");
		AddMnemonic(opSETA, "SETA");
		AddMnemonic(opSETAE, "SETAE");
		AddMnemonic(opSETB, "SETB");
		AddMnemonic(opSETBE, "SETBE");
		AddMnemonic(opSETC, "SETC");
		AddMnemonic(opSETE, "SETE");
		AddMnemonic(opSETG, "SETG");
		AddMnemonic(opSETGE, "SETGE");
		AddMnemonic(opSETL, "SETL");
		AddMnemonic(opSETLE, "SETLE");
		AddMnemonic(opSETNA, "SETNA");
		AddMnemonic(opSETNAE, "SETNAE");
		AddMnemonic(opSETNB, "SETNB");
		AddMnemonic(opSETNBE, "SETNBE");
		AddMnemonic(opSETNC, "SETNC");
		AddMnemonic(opSETNE, "SETNE");
		AddMnemonic(opSETNG, "SETNG");
		AddMnemonic(opSETNGE, "SETNGE");
		AddMnemonic(opSETNL, "SETNL");
		AddMnemonic(opSETNLE, "SETNLE");
		AddMnemonic(opSETNO, "SETNO");
		AddMnemonic(opSETNP, "SETNP");
		AddMnemonic(opSETNS, "SETNS");
		AddMnemonic(opSETNZ, "SETNZ");
		AddMnemonic(opSETO, "SETO");
		AddMnemonic(opSETP, "SETP");
		AddMnemonic(opSETPE, "SETPE");
		AddMnemonic(opSETPO, "SETPO");
		AddMnemonic(opSETS, "SETS");
		AddMnemonic(opSETZ, "SETZ");
		AddMnemonic(opSFENCE, "SFENCE");
		AddMnemonic(opSGDT, "SGDT");
		AddMnemonic(opSHL, "SHL");
		AddMnemonic(opSHLD, "SHLD");
		AddMnemonic(opSHR, "SHR");
		AddMnemonic(opSHRD, "SHRD");
		AddMnemonic(opSHUFPD, "SHUFPD");
		AddMnemonic(opSHUFPS, "SHUFPS");
		AddMnemonic(opSIDT, "SIDT");
		AddMnemonic(opSKINIT, "SKINIT");
		AddMnemonic(opSLDT, "SLDT");
		AddMnemonic(opSMSW, "SMSW");
		AddMnemonic(opSQRTPD, "SQRTPD");
		AddMnemonic(opSQRTPS, "SQRTPS");
		AddMnemonic(opSQRTSD, "SQRTSD");
		AddMnemonic(opSQRTSS, "SQRTSS");
		AddMnemonic(opSTC, "STC");
		AddMnemonic(opSTD, "STD");
		AddMnemonic(opSTGI, "STGI");
		AddMnemonic(opSTI, "STI");
		AddMnemonic(opSTMXCSR, "STMXCSR");
		AddMnemonic(opSTOS, "STOS");
		AddMnemonic(opSTOSB, "STOSB");
		AddMnemonic(opSTOSD, "STOSD");
		AddMnemonic(opSTOSQ, "STOSQ");
		AddMnemonic(opSTOSW, "STOSW");
		AddMnemonic(opSTR, "STR");
		AddMnemonic(opSUB, "SUB");
		AddMnemonic(opSUBPD, "SUBPD");
		AddMnemonic(opSUBPS, "SUBPS");
		AddMnemonic(opSUBSD, "SUBSD");
		AddMnemonic(opSUBSS, "SUBSS");
		AddMnemonic(opSWAPGS, "SWAPGS");
		AddMnemonic(opSYSCALL, "SYSCALL");
		AddMnemonic(opSYSENTER, "SYSENTER");
		AddMnemonic(opSYSEXIT, "SYSEXIT");
		AddMnemonic(opSYSRET, "SYSRET");
		AddMnemonic(opTEST, "TEST");
		AddMnemonic(opUCOMISD, "UCOMISD");
		AddMnemonic(opUCOMISS, "UCOMISS");
		AddMnemonic(opUD2, "UD2");
		AddMnemonic(opUNPCKHPD, "UNPCKHPD");
		AddMnemonic(opUNPCKHPS, "UNPCKHPS");
		AddMnemonic(opUNPCKLPD, "UNPCKLPD");
		AddMnemonic(opUNPCKLPS, "UNPCKLPS");
		AddMnemonic(opVADDPD, "VADDPD");
		AddMnemonic(opVADDPS, "VADDPS");
		AddMnemonic(opVADDSD, "VADDSD");
		AddMnemonic(opVADDSS, "VADDSS");
		AddMnemonic(opVADDSUBPD, "VADDSUBPD");
		AddMnemonic(opVADDSUBPS, "VADDSUBPS");
		AddMnemonic(opVAESDEC, "VAESDEC");
		AddMnemonic(opVAESDECLAST, "VAESDECLAST");
		AddMnemonic(opVAESENC, "VAESENC");
		AddMnemonic(opVAESENCLAST, "VAESENCLAST");
		AddMnemonic(opVAESIMC, "VAESIMC");
		AddMnemonic(opVAESKEYGENASSIST, "VAESKEYGENASSIST");
		AddMnemonic(opVANDNPD, "VANDNPD");
		AddMnemonic(opVANDNPS, "VANDNPS");
		AddMnemonic(opVANDPD, "VANDPD");
		AddMnemonic(opVANDPS, "VANDPS");
		AddMnemonic(opVBLENDPD, "VBLENDPD");
		AddMnemonic(opVBLENDPS, "VBLENDPS");
		AddMnemonic(opVBLENDVPD, "VBLENDVPD");
		AddMnemonic(opVBLENDVPS, "VBLENDVPS");
		AddMnemonic(opVBROADCASTF128, "VBROADCASTF128");
		AddMnemonic(opVBROADCASTI128, "VBROADCASTI128");
		AddMnemonic(opVBROADCASTSD, "VBROADCASTSD");
		AddMnemonic(opVBROADCASTSS, "VBROADCASTSS");
		AddMnemonic(opVCMPPD, "VCMPPD");
		AddMnemonic(opVCMPPS, "VCMPPS");
		AddMnemonic(opVCMPSD, "VCMPSD");
		AddMnemonic(opVCMPSS, "VCMPSS");
		AddMnemonic(opVCOMISD, "VCOMISD");
		AddMnemonic(opVCOMISS, "VCOMISS");
		AddMnemonic(opVCVTDQ2PD, "VCVTDQ2PD");
		AddMnemonic(opVCVTDQ2PS, "VCVTDQ2PS");
		AddMnemonic(opVCVTPD2DQ, "VCVTPD2DQ");
		AddMnemonic(opVCVTPD2PS, "VCVTPD2PS");
		AddMnemonic(opVCVTPH2PS, "VCVTPH2PS");
		AddMnemonic(opVCVTPS2DQ, "VCVTPS2DQ");
		AddMnemonic(opVCVTPS2PD, "VCVTPS2PD");
		AddMnemonic(opVCVTPS2PH, "VCVTPS2PH");
		AddMnemonic(opVCVTSD2SI, "VCVTSD2SI");
		AddMnemonic(opVCVTSD2SS, "VCVTSD2SS");
		AddMnemonic(opVCVTSI2SD, "VCVTSI2SD");
		AddMnemonic(opVCVTSI2SS, "VCVTSI2SS");
		AddMnemonic(opVCVTSS2SD, "VCVTSS2SD");
		AddMnemonic(opVCVTSS2SI, "VCVTSS2SI");
		AddMnemonic(opVCVTTPD2DQ, "VCVTTPD2DQ");
		AddMnemonic(opVCVTTPS2DQ, "VCVTTPS2DQ");
		AddMnemonic(opVCVTTSD2SI, "VCVTTSD2SI");
		AddMnemonic(opVCVTTSS2SI, "VCVTTSS2SI");
		AddMnemonic(opVDIVPD, "VDIVPD");
		AddMnemonic(opVDIVPS, "VDIVPS");
		AddMnemonic(opVDIVSD, "VDIVSD");
		AddMnemonic(opVDIVSS, "VDIVSS");
		AddMnemonic(opVDPPD, "VDPPD");
		AddMnemonic(opVDPPS, "VDPPS");
		AddMnemonic(opVERR, "VERR");
		AddMnemonic(opVERW, "VERW");
		AddMnemonic(opVEXTRACTF128, "VEXTRACTF128");
		AddMnemonic(opVEXTRACTI128, "VEXTRACTI128");
		AddMnemonic(opVEXTRACTPS, "VEXTRACTPS");
		AddMnemonic(opVFMADD132PD, "VFMADD132PD");
		AddMnemonic(opVFMADD132PS, "VFMADD132PS");
		AddMnemonic(opVFMADD132SD, "VFMADD132SD");
		AddMnemonic(opVFMADD132SS, "VFMADD132SS");
		AddMnemonic(opVFMADD213PD, "VFMADD213PD");
		AddMnemonic(opVFMADD213PS, "VFMADD213PS");
		AddMnemonic(opVFMADD213SD, "VFMADD213SD");
		AddMnemonic(opVFMADD213SS, "VFMADD213SS");
		AddMnemonic(opVFMADD231PD, "VFMADD231PD");
		AddMnemonic(opVFMADD231PS, "VFMADD231PS");
		AddMnemonic(opVFMADD231SD, "VFMADD231SD");
		AddMnemonic(opVFMADD231SS, "VFMADD231SS");
		AddMnemonic(opVFMADDPD, "VFMADDPD");
		AddMnemonic(opVFMADDPS, "VFMADDPS");
		AddMnemonic(opVFMADDSD, "VFMADDSD");
		AddMnemonic(opVFMADDSS, "VFMADDSS");
		AddMnemonic(opVFMADDSUB132PD, "VFMADDSUB132PD");
		AddMnemonic(opVFMADDSUB132PS, "VFMADDSUB132PS");
		AddMnemonic(opVFMADDSUB213PD, "VFMADDSUB213PD");
		AddMnemonic(opVFMADDSUB213PS, "VFMADDSUB213PS");
		AddMnemonic(opVFMADDSUB231PD, "VFMADDSUB231PD");
		AddMnemonic(opVFMADDSUB231PS, "VFMADDSUB231PS");
		AddMnemonic(opVFMADDSUBPD, "VFMADDSUBPD");
		AddMnemonic(opVFMADDSUBPS, "VFMADDSUBPS");
		AddMnemonic(opVFMSUB132PD, "VFMSUB132PD");
		AddMnemonic(opVFMSUB132PS, "VFMSUB132PS");
		AddMnemonic(opVFMSUB132SD, "VFMSUB132SD");
		AddMnemonic(opVFMSUB132SS, "VFMSUB132SS");
		AddMnemonic(opVFMSUB213PD, "VFMSUB213PD");
		AddMnemonic(opVFMSUB213PS, "VFMSUB213PS");
		AddMnemonic(opVFMSUB213SD, "VFMSUB213SD");
		AddMnemonic(opVFMSUB213SS, "VFMSUB213SS");
		AddMnemonic(opVFMSUB231PD, "VFMSUB231PD");
		AddMnemonic(opVFMSUB231PS, "VFMSUB231PS");
		AddMnemonic(opVFMSUB231SD, "VFMSUB231SD");
		AddMnemonic(opVFMSUB231SS, "VFMSUB231SS");
		AddMnemonic(opVFMSUBADD132PD, "VFMSUBADD132PD");
		AddMnemonic(opVFMSUBADD132PS, "VFMSUBADD132PS");
		AddMnemonic(opVFMSUBADD213PD, "VFMSUBADD213PD");
		AddMnemonic(opVFMSUBADD213PS, "VFMSUBADD213PS");
		AddMnemonic(opVFMSUBADD231PD, "VFMSUBADD231PD");
		AddMnemonic(opVFMSUBADD231PS, "VFMSUBADD231PS");
		AddMnemonic(opVFMSUBADDPD, "VFMSUBADDPD");
		AddMnemonic(opVFMSUBADDPS, "VFMSUBADDPS");
		AddMnemonic(opVFMSUBPD, "VFMSUBPD");
		AddMnemonic(opVFMSUBPS, "VFMSUBPS");
		AddMnemonic(opVFMSUBSD, "VFMSUBSD");
		AddMnemonic(opVFMSUBSS, "VFMSUBSS");
		AddMnemonic(opVFNMADD132PD, "VFNMADD132PD");
		AddMnemonic(opVFNMADD132PS, "VFNMADD132PS");
		AddMnemonic(opVFNMADD132SD, "VFNMADD132SD");
		AddMnemonic(opVFNMADD132SS, "VFNMADD132SS");
		AddMnemonic(opVFNMADD213PD, "VFNMADD213PD");
		AddMnemonic(opVFNMADD213PS, "VFNMADD213PS");
		AddMnemonic(opVFNMADD213SD, "VFNMADD213SD");
		AddMnemonic(opVFNMADD213SS, "VFNMADD213SS");
		AddMnemonic(opVFNMADD231PD, "VFNMADD231PD");
		AddMnemonic(opVFNMADD231PS, "VFNMADD231PS");
		AddMnemonic(opVFNMADD231SD, "VFNMADD231SD");
		AddMnemonic(opVFNMADD231SS, "VFNMADD231SS");
		AddMnemonic(opVFNMADDPD, "VFNMADDPD");
		AddMnemonic(opVFNMADDPS, "VFNMADDPS");
		AddMnemonic(opVFNMADDSD, "VFNMADDSD");
		AddMnemonic(opVFNMADDSS, "VFNMADDSS");
		AddMnemonic(opVFNMSUB132PD, "VFNMSUB132PD");
		AddMnemonic(opVFNMSUB132PS, "VFNMSUB132PS");
		AddMnemonic(opVFNMSUB132SD, "VFNMSUB132SD");
		AddMnemonic(opVFNMSUB132SS, "VFNMSUB132SS");
		AddMnemonic(opVFNMSUB213PD, "VFNMSUB213PD");
		AddMnemonic(opVFNMSUB213PS, "VFNMSUB213PS");
		AddMnemonic(opVFNMSUB213SD, "VFNMSUB213SD");
		AddMnemonic(opVFNMSUB213SS, "VFNMSUB213SS");
		AddMnemonic(opVFNMSUB231PD, "VFNMSUB231PD");
		AddMnemonic(opVFNMSUB231PS, "VFNMSUB231PS");
		AddMnemonic(opVFNMSUB231SD, "VFNMSUB231SD");
		AddMnemonic(opVFNMSUB231SS, "VFNMSUB231SS");
		AddMnemonic(opVFNMSUBPD, "VFNMSUBPD");
		AddMnemonic(opVFNMSUBPS, "VFNMSUBPS");
		AddMnemonic(opVFNMSUBSD, "VFNMSUBSD");
		AddMnemonic(opVFNMSUBSS, "VFNMSUBSS");
		AddMnemonic(opVFRCZPD, "VFRCZPD");
		AddMnemonic(opVFRCZPS, "VFRCZPS");
		AddMnemonic(opVFRCZSD, "VFRCZSD");
		AddMnemonic(opVFRCZSS, "VFRCZSS");
		AddMnemonic(opVGATHERDPD, "VGATHERDPD");
		AddMnemonic(opVGATHERDPS, "VGATHERDPS");
		AddMnemonic(opVGATHERQPD, "VGATHERQPD");
		AddMnemonic(opVGATHERQPS, "VGATHERQPS");
		AddMnemonic(opVHADDPD, "VHADDPD");
		AddMnemonic(opVHADDPS, "VHADDPS");
		AddMnemonic(opVHSUBPD, "VHSUBPD");
		AddMnemonic(opVHSUBPS, "VHSUBPS");
		AddMnemonic(opVINSERTF128, "VINSERTF128");
		AddMnemonic(opVINSERTI128, "VINSERTI128");
		AddMnemonic(opVINSERTPS, "VINSERTPS");
		AddMnemonic(opVLDDQU, "VLDDQU");
		AddMnemonic(opVLDMXCSR, "VLDMXCSR");
		AddMnemonic(opVMASKMOVDQU, "VMASKMOVDQU");
		AddMnemonic(opVMASKMOVPD, "VMASKMOVPD");
		AddMnemonic(opVMASKMOVPS, "VMASKMOVPS");
		AddMnemonic(opVMAXPD, "VMAXPD");
		AddMnemonic(opVMAXPS, "VMAXPS");
		AddMnemonic(opVMAXSD, "VMAXSD");
		AddMnemonic(opVMAXSS, "VMAXSS");
		AddMnemonic(opVMINPD, "VMINPD");
		AddMnemonic(opVMINPS, "VMINPS");
		AddMnemonic(opVMINSD, "VMINSD");
		AddMnemonic(opVMINSS, "VMINSS");
		AddMnemonic(opVMLOAD, "VMLOAD");
		AddMnemonic(opVMMCALL, "VMMCALL");
		AddMnemonic(opVMOVAPD, "VMOVAPD");
		AddMnemonic(opVMOVAPS, "VMOVAPS");
		AddMnemonic(opVMOVD, "VMOVD");
		AddMnemonic(opVMOVDDUP, "VMOVDDUP");
		AddMnemonic(opVMOVDQA, "VMOVDQA");
		AddMnemonic(opVMOVDQU, "VMOVDQU");
		AddMnemonic(opVMOVHLPS, "VMOVHLPS");
		AddMnemonic(opVMOVHPD, "VMOVHPD");
		AddMnemonic(opVMOVHPS, "VMOVHPS");
		AddMnemonic(opVMOVLHPS, "VMOVLHPS");
		AddMnemonic(opVMOVLPD, "VMOVLPD");
		AddMnemonic(opVMOVLPS, "VMOVLPS");
		AddMnemonic(opVMOVMSKPD, "VMOVMSKPD");
		AddMnemonic(opVMOVMSKPS, "VMOVMSKPS");
		AddMnemonic(opVMOVNTDQ, "VMOVNTDQ");
		AddMnemonic(opVMOVNTDQA, "VMOVNTDQA");
		AddMnemonic(opVMOVNTPD, "VMOVNTPD");
		AddMnemonic(opVMOVNTPS, "VMOVNTPS");
		AddMnemonic(opVMOVQ, "VMOVQ");
		AddMnemonic(opVMOVSD, "VMOVSD");
		AddMnemonic(opVMOVSHDUP, "VMOVSHDUP");
		AddMnemonic(opVMOVSLDUP, "VMOVSLDUP");
		AddMnemonic(opVMOVSS, "VMOVSS");
		AddMnemonic(opVMOVUPD, "VMOVUPD");
		AddMnemonic(opVMOVUPS, "VMOVUPS");
		AddMnemonic(opVMPSADBW, "VMPSADBW");
		AddMnemonic(opVMRUN, "VMRUN");
		AddMnemonic(opVMSAVE, "VMSAVE");
		AddMnemonic(opVMULPD, "VMULPD");
		AddMnemonic(opVMULPS, "VMULPS");
		AddMnemonic(opVMULSD, "VMULSD");
		AddMnemonic(opVMULSS, "VMULSS");
		AddMnemonic(opVORPD, "VORPD");
		AddMnemonic(opVORPS, "VORPS");
		AddMnemonic(opVPABSB, "VPABSB");
		AddMnemonic(opVPABSD, "VPABSD");
		AddMnemonic(opVPABSW, "VPABSW");
		AddMnemonic(opVPACKSSDW, "VPACKSSDW");
		AddMnemonic(opVPACKSSWB, "VPACKSSWB");
		AddMnemonic(opVPACKUSDW, "VPACKUSDW");
		AddMnemonic(opVPACKUSWB, "VPACKUSWB");
		AddMnemonic(opVPADDB, "VPADDB");
		AddMnemonic(opVPADDD, "VPADDD");
		AddMnemonic(opVPADDQ, "VPADDQ");
		AddMnemonic(opVPADDSB, "VPADDSB");
		AddMnemonic(opVPADDSW, "VPADDSW");
		AddMnemonic(opVPADDUSB, "VPADDUSB");
		AddMnemonic(opVPADDUSW, "VPADDUSW");
		AddMnemonic(opVPADDW, "VPADDW");
		AddMnemonic(opVPALIGNR, "VPALIGNR");
		AddMnemonic(opVPAND, "VPAND");
		AddMnemonic(opVPANDN, "VPANDN");
		AddMnemonic(opVPAVGB, "VPAVGB");
		AddMnemonic(opVPAVGW, "VPAVGW");
		AddMnemonic(opVPBLENDD, "VPBLENDD");
		AddMnemonic(opVPBLENDVB, "VPBLENDVB");
		AddMnemonic(opVPBLENDW, "VPBLENDW");
		AddMnemonic(opVPBROADCASTB, "VPBROADCASTB");
		AddMnemonic(opVPBROADCASTD, "VPBROADCASTD");
		AddMnemonic(opVPBROADCASTQ, "VPBROADCASTQ");
		AddMnemonic(opVPBROADCASTW, "VPBROADCASTW");
		AddMnemonic(opVPCLMULQDQ, "VPCLMULQDQ");
		AddMnemonic(opVPCMOV, "VPCMOV");
		AddMnemonic(opVPCMPEQB, "VPCMPEQB");
		AddMnemonic(opVPCMPEQD, "VPCMPEQD");
		AddMnemonic(opVPCMPEQQ, "VPCMPEQQ");
		AddMnemonic(opVPCMPEQW, "VPCMPEQW");
		AddMnemonic(opVPCMPESTRI, "VPCMPESTRI");
		AddMnemonic(opVPCMPESTRM, "VPCMPESTRM");
		AddMnemonic(opVPCMPGTB, "VPCMPGTB");
		AddMnemonic(opVPCMPGTD, "VPCMPGTD");
		AddMnemonic(opVPCMPGTQ, "VPCMPGTQ");
		AddMnemonic(opVPCMPGTW, "VPCMPGTW");
		AddMnemonic(opVPCMPISTRI, "VPCMPISTRI");
		AddMnemonic(opVPCMPISTRM, "VPCMPISTRM");
		AddMnemonic(opVPCOMB, "VPCOMB");
		AddMnemonic(opVPCOMD, "VPCOMD");
		AddMnemonic(opVPCOMQ, "VPCOMQ");
		AddMnemonic(opVPCOMUB, "VPCOMUB");
		AddMnemonic(opVPCOMUD, "VPCOMUD");
		AddMnemonic(opVPCOMUQ, "VPCOMUQ");
		AddMnemonic(opVPCOMUW, "VPCOMUW");
		AddMnemonic(opVPCOMW, "VPCOMW");
		AddMnemonic(opVPERM2F128, "VPERM2F128");
		AddMnemonic(opVPERM2I128, "VPERM2I128");
		AddMnemonic(opVPERMD, "VPERMD");
		AddMnemonic(opVPERMIL2PD, "VPERMIL2PD");
		AddMnemonic(opVPERMIL2PS, "VPERMIL2PS");
		AddMnemonic(opVPERMILPD, "VPERMILPD");
		AddMnemonic(opVPERMILPS, "VPERMILPS");
		AddMnemonic(opVPERMPD, "VPERMPD");
		AddMnemonic(opVPERMPS, "VPERMPS");
		AddMnemonic(opVPERMQ, "VPERMQ");
		AddMnemonic(opVPEXTRB, "VPEXTRB");
		AddMnemonic(opVPEXTRD, "VPEXTRD");
		AddMnemonic(opVPEXTRQ, "VPEXTRQ");
		AddMnemonic(opVPEXTRW, "VPEXTRW");
		AddMnemonic(opVPGATHERDD, "VPGATHERDD");
		AddMnemonic(opVPGATHERDQ, "VPGATHERDQ");
		AddMnemonic(opVPGATHERQD, "VPGATHERQD");
		AddMnemonic(opVPGATHERQQ, "VPGATHERQQ");
		AddMnemonic(opVPHADDBD, "VPHADDBD");
		AddMnemonic(opVPHADDBQ, "VPHADDBQ");
		AddMnemonic(opVPHADDBW, "VPHADDBW");
		AddMnemonic(opVPHADDD, "VPHADDD");
		AddMnemonic(opVPHADDDQ, "VPHADDDQ");
		AddMnemonic(opVPHADDSW, "VPHADDSW");
		AddMnemonic(opVPHADDUBD, "VPHADDUBD");
		AddMnemonic(opVPHADDUBQ, "VPHADDUBQ");
		AddMnemonic(opVPHADDUBW, "VPHADDUBW");
		AddMnemonic(opVPHADDUDQ, "VPHADDUDQ");
		AddMnemonic(opVPHADDUWD, "VPHADDUWD");
		AddMnemonic(opVPHADDUWQ, "VPHADDUWQ");
		AddMnemonic(opVPHADDW, "VPHADDW");
		AddMnemonic(opVPHADDWD, "VPHADDWD");
		AddMnemonic(opVPHADDWQ, "VPHADDWQ");
		AddMnemonic(opVPHMINPOSUW, "VPHMINPOSUW");
		AddMnemonic(opVPHSUBBW, "VPHSUBBW");
		AddMnemonic(opVPHSUBD, "VPHSUBD");
		AddMnemonic(opVPHSUBDQ, "VPHSUBDQ");
		AddMnemonic(opVPHSUBSW, "VPHSUBSW");
		AddMnemonic(opVPHSUBW, "VPHSUBW");
		AddMnemonic(opVPHSUBWD, "VPHSUBWD");
		AddMnemonic(opVPINSRB, "VPINSRB");
		AddMnemonic(opVPINSRD, "VPINSRD");
		AddMnemonic(opVPINSRQ, "VPINSRQ");
		AddMnemonic(opVPINSRW, "VPINSRW");
		AddMnemonic(opVPMACSDD, "VPMACSDD");
		AddMnemonic(opVPMACSDQH, "VPMACSDQH");
		AddMnemonic(opVPMACSDQL, "VPMACSDQL");
		AddMnemonic(opVPMACSSDD, "VPMACSSDD");
		AddMnemonic(opVPMACSSDQH, "VPMACSSDQH");
		AddMnemonic(opVPMACSSDQL, "VPMACSSDQL");
		AddMnemonic(opVPMACSSWD, "VPMACSSWD");
		AddMnemonic(opVPMACSSWW, "VPMACSSWW");
		AddMnemonic(opVPMACSWD, "VPMACSWD");
		AddMnemonic(opVPMACSWW, "VPMACSWW");
		AddMnemonic(opVPMADCSSWD, "VPMADCSSWD");
		AddMnemonic(opVPMADCSWD, "VPMADCSWD");
		AddMnemonic(opVPMADDUBSW, "VPMADDUBSW");
		AddMnemonic(opVPMADDWD, "VPMADDWD");
		AddMnemonic(opVPMASKMOVD, "VPMASKMOVD");
		AddMnemonic(opVPMASKMOVQ, "VPMASKMOVQ");
		AddMnemonic(opVPMAXSB, "VPMAXSB");
		AddMnemonic(opVPMAXSD, "VPMAXSD");
		AddMnemonic(opVPMAXSW, "VPMAXSW");
		AddMnemonic(opVPMAXUB, "VPMAXUB");
		AddMnemonic(opVPMAXUD, "VPMAXUD");
		AddMnemonic(opVPMAXUW, "VPMAXUW");
		AddMnemonic(opVPMINSB, "VPMINSB");
		AddMnemonic(opVPMINSD, "VPMINSD");
		AddMnemonic(opVPMINSW, "VPMINSW");
		AddMnemonic(opVPMINUB, "VPMINUB");
		AddMnemonic(opVPMINUD, "VPMINUD");
		AddMnemonic(opVPMINUW, "VPMINUW");
		AddMnemonic(opVPMOVMSKB, "VPMOVMSKB");
		AddMnemonic(opVPMOVSXBD, "VPMOVSXBD");
		AddMnemonic(opVPMOVSXBQ, "VPMOVSXBQ");
		AddMnemonic(opVPMOVSXBW, "VPMOVSXBW");
		AddMnemonic(opVPMOVSXDQ, "VPMOVSXDQ");
		AddMnemonic(opVPMOVSXWD, "VPMOVSXWD");
		AddMnemonic(opVPMOVSXWQ, "VPMOVSXWQ");
		AddMnemonic(opVPMOVZXBD, "VPMOVZXBD");
		AddMnemonic(opVPMOVZXBQ, "VPMOVZXBQ");
		AddMnemonic(opVPMOVZXBW, "VPMOVZXBW");
		AddMnemonic(opVPMOVZXDQ, "VPMOVZXDQ");
		AddMnemonic(opVPMOVZXWD, "VPMOVZXWD");
		AddMnemonic(opVPMOVZXWQ, "VPMOVZXWQ");
		AddMnemonic(opVPMULDQ, "VPMULDQ");
		AddMnemonic(opVPMULHRSW, "VPMULHRSW");
		AddMnemonic(opVPMULHUW, "VPMULHUW");
		AddMnemonic(opVPMULHW, "VPMULHW");
		AddMnemonic(opVPMULLD, "VPMULLD");
		AddMnemonic(opVPMULLW, "VPMULLW");
		AddMnemonic(opVPMULUDQ, "VPMULUDQ");
		AddMnemonic(opVPOR, "VPOR");
		AddMnemonic(opVPPERM, "VPPERM");
		AddMnemonic(opVPROTB, "VPROTB");
		AddMnemonic(opVPROTD, "VPROTD");
		AddMnemonic(opVPROTQ, "VPROTQ");
		AddMnemonic(opVPROTW, "VPROTW");
		AddMnemonic(opVPSADBW, "VPSADBW");
		AddMnemonic(opVPSHAB, "VPSHAB");
		AddMnemonic(opVPSHAD, "VPSHAD");
		AddMnemonic(opVPSHAQ, "VPSHAQ");
		AddMnemonic(opVPSHAW, "VPSHAW");
		AddMnemonic(opVPSHLB, "VPSHLB");
		AddMnemonic(opVPSHLD, "VPSHLD");
		AddMnemonic(opVPSHLQ, "VPSHLQ");
		AddMnemonic(opVPSHLW, "VPSHLW");
		AddMnemonic(opVPSHUFB, "VPSHUFB");
		AddMnemonic(opVPSHUFD, "VPSHUFD");
		AddMnemonic(opVPSHUFHW, "VPSHUFHW");
		AddMnemonic(opVPSHUFLW, "VPSHUFLW");
		AddMnemonic(opVPSIGNB, "VPSIGNB");
		AddMnemonic(opVPSIGND, "VPSIGND");
		AddMnemonic(opVPSIGNW, "VPSIGNW");
		AddMnemonic(opVPSLLD, "VPSLLD");
		AddMnemonic(opVPSLLDQ, "VPSLLDQ");
		AddMnemonic(opVPSLLQ, "VPSLLQ");
		AddMnemonic(opVPSLLVD, "VPSLLVD");
		AddMnemonic(opVPSLLVQ, "VPSLLVQ");
		AddMnemonic(opVPSLLW, "VPSLLW");
		AddMnemonic(opVPSRAD, "VPSRAD");
		AddMnemonic(opVPSRAVD, "VPSRAVD");
		AddMnemonic(opVPSRAW, "VPSRAW");
		AddMnemonic(opVPSRLD, "VPSRLD");
		AddMnemonic(opVPSRLDQ, "VPSRLDQ");
		AddMnemonic(opVPSRLQ, "VPSRLQ");
		AddMnemonic(opVPSRLVD, "VPSRLVD");
		AddMnemonic(opVPSRLVQ, "VPSRLVQ");
		AddMnemonic(opVPSRLW, "VPSRLW");
		AddMnemonic(opVPSUBB, "VPSUBB");
		AddMnemonic(opVPSUBD, "VPSUBD");
		AddMnemonic(opVPSUBQ, "VPSUBQ");
		AddMnemonic(opVPSUBSB, "VPSUBSB");
		AddMnemonic(opVPSUBSW, "VPSUBSW");
		AddMnemonic(opVPSUBUSB, "VPSUBUSB");
		AddMnemonic(opVPSUBUSW, "VPSUBUSW");
		AddMnemonic(opVPSUBW, "VPSUBW");
		AddMnemonic(opVPTEST, "VPTEST");
		AddMnemonic(opVPUNPCKHBW, "VPUNPCKHBW");
		AddMnemonic(opVPUNPCKHDQ, "VPUNPCKHDQ");
		AddMnemonic(opVPUNPCKHQDQ, "VPUNPCKHQDQ");
		AddMnemonic(opVPUNPCKHWD, "VPUNPCKHWD");
		AddMnemonic(opVPUNPCKLBW, "VPUNPCKLBW");
		AddMnemonic(opVPUNPCKLDQ, "VPUNPCKLDQ");
		AddMnemonic(opVPUNPCKLQDQ, "VPUNPCKLQDQ");
		AddMnemonic(opVPUNPCKLWD, "VPUNPCKLWD");
		AddMnemonic(opVPXOR, "VPXOR");
		AddMnemonic(opVRCPPS, "VRCPPS");
		AddMnemonic(opVRCPSS, "VRCPSS");
		AddMnemonic(opVROUNDPD, "VROUNDPD");
		AddMnemonic(opVROUNDPS, "VROUNDPS");
		AddMnemonic(opVROUNDSD, "VROUNDSD");
		AddMnemonic(opVROUNDSS, "VROUNDSS");
		AddMnemonic(opVRSQRTPS, "VRSQRTPS");
		AddMnemonic(opVRSQRTSS, "VRSQRTSS");
		AddMnemonic(opVSHUFPD, "VSHUFPD");
		AddMnemonic(opVSHUFPS, "VSHUFPS");
		AddMnemonic(opVSQRTPD, "VSQRTPD");
		AddMnemonic(opVSQRTPS, "VSQRTPS");
		AddMnemonic(opVSQRTSD, "VSQRTSD");
		AddMnemonic(opVSQRTSS, "VSQRTSS");
		AddMnemonic(opVSTMXCSR, "VSTMXCSR");
		AddMnemonic(opVSUBPD, "VSUBPD");
		AddMnemonic(opVSUBPS, "VSUBPS");
		AddMnemonic(opVSUBSD, "VSUBSD");
		AddMnemonic(opVSUBSS, "VSUBSS");
		AddMnemonic(opVTESTPD, "VTESTPD");
		AddMnemonic(opVTESTPS, "VTESTPS");
		AddMnemonic(opVUCOMISD, "VUCOMISD");
		AddMnemonic(opVUCOMISS, "VUCOMISS");
		AddMnemonic(opVUNPCKHPD, "VUNPCKHPD");
		AddMnemonic(opVUNPCKHPS, "VUNPCKHPS");
		AddMnemonic(opVUNPCKLPD, "VUNPCKLPD");
		AddMnemonic(opVUNPCKLPS, "VUNPCKLPS");
		AddMnemonic(opVXORPD, "VXORPD");
		AddMnemonic(opVXORPS, "VXORPS");
		AddMnemonic(opVZEROALL, "VZEROALL");
		AddMnemonic(opVZEROUPPER, "VZEROUPPER");
		AddMnemonic(opWBINVD, "WBINVD");
		AddMnemonic(opWRMSR, "WRMSR");
		AddMnemonic(opXADD, "XADD");
		AddMnemonic(opXCHG, "XCHG");
		AddMnemonic(opXLAT, "XLAT");
		AddMnemonic(opXLATB, "XLATB");
		AddMnemonic(opXOR, "XOR");
		AddMnemonic(opXORPD, "XORPD");
		AddMnemonic(opXORPS, "XORPS");

		AddInstruction(opAAA, "", "37", {optNot64}, {cpu8086});
		AddInstruction(opAAD, "", "D50A", {optNot64}, {cpu8086});
		AddInstruction(opAAD, "", "D5ib", {optNot64}, {cpu8086});
		AddInstruction(opAAM, "", "D40A", {optNot64}, {cpu8086});
		AddInstruction(opAAM, "", "D4ib", {optNot64}, {cpu8086});
		AddInstruction(opAAS, "", "3F", {optNot64}, {cpu8086});
		AddInstruction(opADC, "reg/mem8,reg8", "10/r", {}, {cpu8086});
		AddInstruction(opADC, "reg/mem16,reg16", "11/r", {optO16}, {cpu8086});
		AddInstruction(opADC, "reg/mem32,reg32", "11/r", {optO32}, {cpu386});
		AddInstruction(opADC, "reg/mem64,reg64", "11/r", {}, {cpuAMD64});
		AddInstruction(opADC, "reg8,reg/mem8", "12/r", {}, {cpu8086});
		AddInstruction(opADC, "reg16,reg/mem16", "13/r", {optO16}, {cpu8086});
		AddInstruction(opADC, "reg32,reg/mem32", "13/r", {optO32}, {cpu386});
		AddInstruction(opADC, "reg64,reg/mem64", "13/r", {}, {cpuAMD64});
		AddInstruction(opADC, "AL,imm8", "14ib", {}, {cpu8086});
		AddInstruction(opADC, "AX,imm16", "15iw", {optO16}, {cpu8086});
		AddInstruction(opADC, "EAX,imm32", "15id", {optO32}, {cpu386});
		AddInstruction(opADC, "RAX,simm32", "15id", {}, {cpuAMD64});
		AddInstruction(opADC, "reg/mem8,imm8", "80/2ib", {}, {cpu8086});
		AddInstruction(opADC, "reg/mem16,imm16", "81/2iw", {optO16}, {cpu8086});
		AddInstruction(opADC, "reg/mem32,imm32", "81/2id", {optO32}, {cpu386});
		AddInstruction(opADC, "reg/mem64,simm32", "81/2id", {}, {cpuAMD64});
		AddInstruction(opADC, "reg/mem16,simm8", "83/2ib", {optO16}, {cpu8086});
		AddInstruction(opADC, "reg/mem32,simm8", "83/2ib", {optO32}, {cpu386});
		AddInstruction(opADC, "reg/mem64,simm8", "83/2ib", {}, {cpuAMD64});
		AddInstruction(opADD, "reg/mem8,reg8", "00/r", {}, {cpu8086});
		AddInstruction(opADD, "reg/mem16,reg16", "01/r", {optO16}, {cpu8086});
		AddInstruction(opADD, "reg/mem32,reg32", "01/r", {optO32}, {cpu386});
		AddInstruction(opADD, "reg/mem64,reg64", "01/r", {}, {cpuAMD64});
		AddInstruction(opADD, "reg8,reg/mem8", "02/r", {}, {cpu8086});
		AddInstruction(opADD, "reg16,reg/mem16", "03/r", {optO16}, {cpu8086});
		AddInstruction(opADD, "reg32,reg/mem32", "03/r", {optO32}, {cpu386});
		AddInstruction(opADD, "reg64,reg/mem64", "03/r", {}, {cpuAMD64});
		AddInstruction(opADD, "AL,imm8", "04ib", {}, {cpu8086});
		AddInstruction(opADD, "AX,imm16", "05iw", {optO16}, {cpu8086});
		AddInstruction(opADD, "EAX,imm32", "05id", {optO32}, {cpu386});
		AddInstruction(opADD, "RAX,simm32", "05id", {}, {cpuAMD64});
		AddInstruction(opADD, "reg/mem8,imm8", "80/0ib", {}, {cpu8086});
		AddInstruction(opADD, "reg/mem16,imm16", "81/0iw", {optO16}, {cpu8086});
		AddInstruction(opADD, "reg/mem32,imm32", "81/0id", {optO32}, {cpu386});
		AddInstruction(opADD, "reg/mem64,simm32", "81/0id", {}, {cpuAMD64});
		AddInstruction(opADD, "reg/mem16,simm8", "83/0ib", {optO16}, {cpu8086});
		AddInstruction(opADD, "reg/mem32,simm8", "83/0ib", {optO32}, {cpu386});
		AddInstruction(opADD, "reg/mem64,simm8", "83/0ib", {}, {cpuAMD64});
		AddInstruction(opADDPD, "xmm1,xmm2/mem128", "0F58/r", {optPOP}, {cpuSSE2});
		AddInstruction(opADDPS, "xmm1,xmm2/mem128", "0F58/r", {}, {cpuSSE});
		AddInstruction(opADDSD, "xmm1,xmm2/mem64", "F20F58/r", {}, {cpuSSE2});
		AddInstruction(opADDSS, "xmm1,xmm2/mem32", "F30F58/r", {}, {cpuSSE});
		AddInstruction(opADDSUBPD, "xmm1,xmm2/mem128", "0FD0/r", {optPOP}, {cpuSSE3});
		AddInstruction(opADDSUBPS, "xmm1,xmm2/mem128", "F20FD0/r", {}, {cpuSSE3});
		AddInstruction(opAND, "reg/mem8,reg8", "20/r", {}, {cpu8086});
		AddInstruction(opAND, "reg/mem16,reg16", "21/r", {optO16}, {cpu8086});
		AddInstruction(opAND, "reg/mem32,reg32", "21/r", {optO32}, {cpu386});
		AddInstruction(opAND, "reg/mem64,reg64", "21/r", {}, {cpuAMD64});
		AddInstruction(opAND, "reg8,reg/mem8", "22/r", {}, {cpu8086});
		AddInstruction(opAND, "reg16,reg/mem16", "23/r", {optO16}, {cpu8086});
		AddInstruction(opAND, "reg32,reg/mem32", "23/r", {optO32}, {cpu386});
		AddInstruction(opAND, "reg64,reg/mem64", "23/r", {}, {cpuAMD64});
		AddInstruction(opAND, "AL,imm8", "24ib", {}, {cpu8086});
		AddInstruction(opAND, "AX,imm16", "25iw", {optO16}, {cpu8086});
		AddInstruction(opAND, "EAX,imm32", "25id", {optO32}, {cpu386});
		AddInstruction(opAND, "RAX,simm32", "25id", {}, {cpuAMD64});
		AddInstruction(opAND, "reg/mem8,imm8", "80/4ib", {}, {cpu8086});
		AddInstruction(opAND, "reg/mem16,imm16", "81/4iw", {optO16}, {cpu8086});
		AddInstruction(opAND, "reg/mem32,imm32", "81/4id", {optO32}, {cpu386});
		AddInstruction(opAND, "reg/mem64,simm32", "81/4id", {}, {cpuAMD64});
		AddInstruction(opAND, "reg/mem16,simm8", "83/4ib", {optO16}, {cpu8086});
		AddInstruction(opAND, "reg/mem32,simm8", "83/4ib", {optO32}, {cpu386});
		AddInstruction(opAND, "reg/mem64,simm8", "83/4ib", {}, {cpuAMD64});
		AddInstruction(opANDNPD, "xmm1,xmm2/mem128", "0F55/r", {optPOP}, {cpuSSE2});
		AddInstruction(opANDNPS, "xmm1,xmm2/mem128", "0F55/r", {}, {cpuSSE});
		AddInstruction(opANDPD, "xmm1,xmm2/mem128", "0F54/r", {optPOP}, {cpuSSE2});
		AddInstruction(opANDPS, "xmm1,xmm2/mem128", "0F54/r", {}, {cpuSSE});
		AddInstruction(opARPL, "reg/mem16,reg16", "63/r", {}, {cpu286,cpuPrivileged});
		AddInstruction(opBOUND, "reg16,mem16&mem16", "62/r", {optO16,optNot64}, {cpu186});
		AddInstruction(opBOUND, "reg32,mem32&mem32", "62/r", {optO32,optNot64}, {cpu386});
		AddInstruction(opBSF, "reg16,reg/mem16", "0FBC/r", {optO16}, {cpu386});
		AddInstruction(opBSF, "reg32,reg/mem32", "0FBC/r", {optO32}, {cpu386});
		AddInstruction(opBSF, "reg64,reg/mem64", "0FBC/r", {}, {cpuAMD64});
		AddInstruction(opBSR, "reg16,reg/mem16", "0FBD/r", {optO16}, {cpu386});
		AddInstruction(opBSR, "reg32,reg/mem32", "0FBD/r", {optO32}, {cpu386});
		AddInstruction(opBSR, "reg64,reg/mem64", "0FBD/r", {}, {cpuAMD64});
		AddInstruction(opBSWAP, "reg32", "0FC8rd", {optO32}, {cpu486});
		AddInstruction(opBSWAP, "reg64", "0FC8rq", {}, {cpuAMD64});
		AddInstruction(opBT, "reg/mem16,reg16", "0FA3/r", {optO16}, {cpu386});
		AddInstruction(opBT, "reg/mem32,reg32", "0FA3/r", {optO32}, {cpu386});
		AddInstruction(opBT, "reg/mem64,reg64", "0FA3/r", {}, {cpuAMD64});
		AddInstruction(opBT, "reg/mem16,uimm8", "0FBA/4ib", {optO16}, {cpu386});
		AddInstruction(opBT, "reg/mem32,uimm8", "0FBA/4ib", {optO32}, {cpu386});
		AddInstruction(opBT, "reg/mem64,uimm8", "0FBA/4ib", {}, {cpuAMD64});
		AddInstruction(opBTC, "reg/mem16,reg16", "0FBB/r", {optO16}, {cpu386});
		AddInstruction(opBTC, "reg/mem32,reg32", "0FBB/r", {optO32}, {cpu386});
		AddInstruction(opBTC, "reg/mem64,reg64", "0FBB/r", {}, {cpuAMD64});
		AddInstruction(opBTC, "reg/mem16,uimm8", "0FBA/7ib", {optO16}, {cpu386});
		AddInstruction(opBTC, "reg/mem32,uimm8", "0FBA/7ib", {optO32}, {cpu386});
		AddInstruction(opBTC, "reg/mem64,uimm8", "0FBA/7ib", {}, {cpuAMD64});
		AddInstruction(opBTR, "reg/mem16,reg16", "0FB3/r", {optO16}, {cpu386});
		AddInstruction(opBTR, "reg/mem32,reg32", "0FB3/r", {optO32}, {cpu386});
		AddInstruction(opBTR, "reg/mem64,reg64", "0FB3/r", {}, {cpuAMD64});
		AddInstruction(opBTR, "reg/mem16,uimm8", "0FBA/6ib", {optO16}, {cpu386});
		AddInstruction(opBTR, "reg/mem32,uimm8", "0FBA/6ib", {optO32}, {cpu386});
		AddInstruction(opBTR, "reg/mem64,uimm8", "0FBA/6ib", {}, {cpuAMD64});
		AddInstruction(opBTS, "reg/mem16,reg16", "0FAB/r", {optO16}, {cpu386});
		AddInstruction(opBTS, "reg/mem32,reg32", "0FAB/r", {optO32}, {cpu386});
		AddInstruction(opBTS, "reg/mem64,reg64", "0FAB/r", {}, {cpuAMD64});
		AddInstruction(opBTS, "reg/mem16,uimm8", "0FBA/5ib", {optO16}, {cpu386});
		AddInstruction(opBTS, "reg/mem32,uimm8", "0FBA/5ib", {optO32}, {cpu386});
		AddInstruction(opBTS, "reg/mem64,uimm8", "0FBA/5ib", {}, {cpuAMD64});
		AddInstruction(opCALL, "rel16off", "E8iw", {optO16}, {cpu8086});
		AddInstruction(opCALL, "rel32off", "E8id", {optO32}, {cpu8086});
		AddInstruction(opCALL, "reg/mem16", "FF/2", {optO16}, {cpu8086});
		AddInstruction(opCALL, "reg/mem32", "FF/2", {optO32}, {cpu386});
		AddInstruction(opCALL, "reg/mem64", "FF/2", {optO64}, {cpuAMD64});
		AddInstruction(opCALLFAR, "pntr16:16", "9Acd", {optNot64}, {cpu8086});
		AddInstruction(opCALLFAR, "pntr16:32", "9Acp", {optNot64}, {cpu386});
		AddInstruction(opCALLFAR, "mem16:16", "FF/3", {optO16,optNot64}, {cpu8086});
		AddInstruction(opCALLFAR, "mem16:32", "FF/3", {optO32,optNot64}, {cpu386});
		AddInstruction(opCBW, "", "98", {optO16}, {cpu8086});
		AddInstruction(opCDQ, "", "99", {optO32}, {cpu386});
		AddInstruction(opCDQE, "", "98", {}, {cpuAMD64});
		AddInstruction(opCLC, "", "F8", {}, {cpu8086});
		AddInstruction(opCLD, "", "FC", {}, {cpu8086});
		AddInstruction(opCLFLUSH, "mem8", "0FAE/7", {}, {cpuSSE2});
		AddInstruction(opCLGI, "", "0F01DD", {}, {cpuAMD64});
		AddInstruction(opCLI, "", "FA", {}, {cpu8086});
		AddInstruction(opCLTS, "", "0F06", {}, {cpu286,cpuPrivileged});
		AddInstruction(opCMC, "", "F5", {}, {cpu8086});
		AddInstruction(opCMOVA, "reg16,reg/mem16", "0F47/r", {optO16}, {cpuP6});
		AddInstruction(opCMOVA, "reg32,reg/mem32", "0F47/r", {optO32}, {cpuP6});
		AddInstruction(opCMOVA, "reg64,reg/mem64", "0F47/r", {}, {cpuAMD64});
		AddInstruction(opCMOVAE, "reg16,reg/mem16", "0F43/r", {optO16}, {cpuP6});
		AddInstruction(opCMOVAE, "reg32,reg/mem32", "0F43/r", {optO32}, {cpuP6});
		AddInstruction(opCMOVAE, "reg64,reg/mem64", "0F43/r", {}, {cpuAMD64});
		AddInstruction(opCMOVB, "reg16,reg/mem16", "0F42/r", {optO16}, {cpuP6});
		AddInstruction(opCMOVB, "reg32,reg/mem32", "0F42/r", {optO32}, {cpuP6});
		AddInstruction(opCMOVB, "reg64,reg/mem64", "0F42/r", {}, {cpuAMD64});
		AddInstruction(opCMOVBE, "reg16,reg/mem16", "0F46/r", {optO16}, {cpuP6});
		AddInstruction(opCMOVBE, "reg32,reg/mem32", "0F46/r", {optO32}, {cpuP6});
		AddInstruction(opCMOVBE, "reg64,reg/mem64", "0F46/r", {}, {cpuAMD64});
		AddInstruction(opCMOVC, "reg16,reg/mem16", "0F42/r", {optO16}, {cpuP6});
		AddInstruction(opCMOVC, "reg32,reg/mem32", "0F42/r", {optO32}, {cpuP6});
		AddInstruction(opCMOVC, "reg64,reg/mem64", "0F42/r", {}, {cpuAMD64});
		AddInstruction(opCMOVE, "reg16,reg/mem16", "0F44/r", {optO16}, {cpuP6});
		AddInstruction(opCMOVE, "reg32,reg/mem32", "0F44/r", {optO32}, {cpuP6});
		AddInstruction(opCMOVE, "reg64,reg/mem64", "0F44/r", {}, {cpuAMD64});
		AddInstruction(opCMOVG, "reg16,reg/mem16", "0F4F/r", {optO16}, {cpuP6});
		AddInstruction(opCMOVG, "reg32,reg/mem32", "0F4F/r", {optO32}, {cpuP6});
		AddInstruction(opCMOVG, "reg64,reg/mem64", "0F4F/r", {}, {cpuAMD64});
		AddInstruction(opCMOVGE, "reg16,reg/mem16", "0F4D/r", {optO16}, {cpuP6});
		AddInstruction(opCMOVGE, "reg32,reg/mem32", "0F4D/r", {optO32}, {cpuP6});
		AddInstruction(opCMOVGE, "reg64,reg/mem64", "0F4D/r", {}, {cpuAMD64});
		AddInstruction(opCMOVL, "reg16,reg/mem16", "0F4C/r", {optO16}, {cpuP6});
		AddInstruction(opCMOVL, "reg32,reg/mem32", "0F4C/r", {optO32}, {cpuP6});
		AddInstruction(opCMOVL, "reg64,reg/mem64", "0F4C/r", {}, {cpuAMD64});
		AddInstruction(opCMOVLE, "reg16,reg/mem16", "0F4E/r", {optO16}, {cpuP6});
		AddInstruction(opCMOVLE, "reg32,reg/mem32", "0F4E/r", {optO32}, {cpuP6});
		AddInstruction(opCMOVLE, "reg64,reg/mem64", "0F4E/r", {}, {cpuAMD64});
		AddInstruction(opCMOVNA, "reg16,reg/mem16", "0F46/r", {optO16}, {cpuP6});
		AddInstruction(opCMOVNA, "reg32,reg/mem32", "0F46/r", {optO32}, {cpuP6});
		AddInstruction(opCMOVNA, "reg64,reg/mem64", "0F46/r", {}, {cpuAMD64});
		AddInstruction(opCMOVNAE, "reg16,reg/mem16", "0F42/r", {optO16}, {cpuP6});
		AddInstruction(opCMOVNAE, "reg32,reg/mem32", "0F42/r", {optO32}, {cpuP6});
		AddInstruction(opCMOVNAE, "reg64,reg/mem64", "0F42/r", {}, {cpuAMD64});
		AddInstruction(opCMOVNB, "reg16,reg/mem16", "0F43/r", {optO16}, {cpuP6});
		AddInstruction(opCMOVNB, "reg32,reg/mem32", "0F43/r", {optO32}, {cpuP6});
		AddInstruction(opCMOVNB, "reg64,reg/mem64", "0F43/r", {}, {cpuAMD64});
		AddInstruction(opCMOVNBE, "reg16,reg/mem16", "0F47/r", {optO16}, {cpuP6});
		AddInstruction(opCMOVNBE, "reg32,reg/mem32", "0F47/r", {optO32}, {cpuP6});
		AddInstruction(opCMOVNBE, "reg64,reg/mem64", "0F47/r", {}, {cpuAMD64});
		AddInstruction(opCMOVNC, "reg16,reg/mem16", "0F43/r", {optO16}, {cpuP6});
		AddInstruction(opCMOVNC, "reg32,reg/mem32", "0F43/r", {optO32}, {cpuP6});
		AddInstruction(opCMOVNC, "reg64,reg/mem64", "0F43/r", {}, {cpuAMD64});
		AddInstruction(opCMOVNE, "reg16,reg/mem16", "0F45/r", {optO16}, {cpuP6});
		AddInstruction(opCMOVNE, "reg32,reg/mem32", "0F45/r", {optO32}, {cpuP6});
		AddInstruction(opCMOVNE, "reg64,reg/mem64", "0F45/r", {}, {cpuAMD64});
		AddInstruction(opCMOVNG, "reg16,reg/mem16", "0F4E/r", {optO16}, {cpuP6});
		AddInstruction(opCMOVNG, "reg32,reg/mem32", "0F4E/r", {optO32}, {cpuP6});
		AddInstruction(opCMOVNG, "reg64,reg/mem64", "0F4E/r", {}, {cpuAMD64});
		AddInstruction(opCMOVNGE, "reg16,reg/mem16", "0F4C/r", {optO16}, {cpuP6});
		AddInstruction(opCMOVNGE, "reg32,reg/mem32", "0F4C/r", {optO32}, {cpuP6});
		AddInstruction(opCMOVNGE, "reg64,reg/mem64", "0F4C/r", {}, {cpuAMD64});
		AddInstruction(opCMOVNL, "reg16,reg/mem16", "0F4D/r", {optO16}, {cpuP6});
		AddInstruction(opCMOVNL, "reg32,reg/mem32", "0F4D/r", {optO32}, {cpuP6});
		AddInstruction(opCMOVNL, "reg64,reg/mem64", "0F4D/r", {}, {cpuAMD64});
		AddInstruction(opCMOVNLE, "reg16,reg/mem16", "0F4F/r", {optO16}, {cpuP6});
		AddInstruction(opCMOVNLE, "reg32,reg/mem32", "0F4F/r", {optO32}, {cpuP6});
		AddInstruction(opCMOVNLE, "reg64,reg/mem64", "0F4F/r", {}, {cpuAMD64});
		AddInstruction(opCMOVNO, "reg16,reg/mem16", "0F41/r", {optO16}, {cpuP6});
		AddInstruction(opCMOVNO, "reg32,reg/mem32", "0F41/r", {optO32}, {cpuP6});
		AddInstruction(opCMOVNO, "reg64,reg/mem64", "0F41/r", {}, {cpuAMD64});
		AddInstruction(opCMOVNP, "reg16,reg/mem16", "0F4B/r", {optO16}, {cpuP6});
		AddInstruction(opCMOVNP, "reg32,reg/mem32", "0F4B/r", {optO32}, {cpuP6});
		AddInstruction(opCMOVNP, "reg64,reg/mem64", "0F4B/r", {}, {cpuAMD64});
		AddInstruction(opCMOVNS, "reg16,reg/mem16", "0F49/r", {optO16}, {cpuP6});
		AddInstruction(opCMOVNS, "reg32,reg/mem32", "0F49/r", {optO32}, {cpuP6});
		AddInstruction(opCMOVNS, "reg64,reg/mem64", "0F49/r", {}, {cpuAMD64});
		AddInstruction(opCMOVNZ, "reg16,reg/mem16", "0F45/r", {optO16}, {cpuP6});
		AddInstruction(opCMOVNZ, "reg32,reg/mem32", "0F45/r", {optO32}, {cpuP6});
		AddInstruction(opCMOVNZ, "reg64,reg/mem64", "0F45/r", {}, {cpuAMD64});
		AddInstruction(opCMOVO, "reg16,reg/mem16", "0F40/r", {optO16}, {cpuP6});
		AddInstruction(opCMOVO, "reg32,reg/mem32", "0F40/r", {optO32}, {cpuP6});
		AddInstruction(opCMOVO, "reg64,reg/mem64", "0F40/r", {}, {cpuAMD64});
		AddInstruction(opCMOVP, "reg16,reg/mem16", "0F4A/r", {optO16}, {cpuP6});
		AddInstruction(opCMOVP, "reg32,reg/mem32", "0F4A/r", {optO32}, {cpuP6});
		AddInstruction(opCMOVP, "reg64,reg/mem64", "0F4A/r", {}, {cpuAMD64});
		AddInstruction(opCMOVPE, "reg16,reg/mem16", "0F4A/r", {optO16}, {cpuP6});
		AddInstruction(opCMOVPE, "reg32,reg/mem32", "0F4A/r", {optO32}, {cpuP6});
		AddInstruction(opCMOVPE, "reg64,reg/mem64", "0F4A/r", {}, {cpuAMD64});
		AddInstruction(opCMOVPO, "reg16,reg/mem16", "0F4B/r", {optO16}, {cpuP6});
		AddInstruction(opCMOVPO, "reg32,reg/mem32", "0F4B/r", {optO32}, {cpuP6});
		AddInstruction(opCMOVPO, "reg64,reg/mem64", "0F4B/r", {}, {cpuAMD64});
		AddInstruction(opCMOVS, "reg16,reg/mem16", "0F48/r", {optO16}, {cpuP6});
		AddInstruction(opCMOVS, "reg32,reg/mem32", "0F48/r", {optO32}, {cpuP6});
		AddInstruction(opCMOVS, "reg64,reg/mem64", "0F48/r", {}, {cpuAMD64});
		AddInstruction(opCMOVZ, "reg16,reg/mem16", "0F44/r", {optO16}, {cpuP6});
		AddInstruction(opCMOVZ, "reg32,reg/mem32", "0F44/r", {optO32}, {cpuP6});
		AddInstruction(opCMOVZ, "reg64,reg/mem64", "0F44/r", {}, {cpuAMD64});
		AddInstruction(opCMP, "reg/mem8,reg8", "38/r", {}, {cpu8086});
		AddInstruction(opCMP, "reg/mem16,reg16", "39/r", {optO16}, {cpu8086});
		AddInstruction(opCMP, "reg/mem32,reg32", "39/r", {optO32}, {cpu386});
		AddInstruction(opCMP, "reg/mem64,reg64", "39/r", {}, {cpuAMD64});
		AddInstruction(opCMP, "reg8,reg/mem8", "3A/r", {}, {cpu8086});
		AddInstruction(opCMP, "reg16,reg/mem16", "3B/r", {optO16}, {cpu8086});
		AddInstruction(opCMP, "reg32,reg/mem32", "3B/r", {optO32}, {cpu386});
		AddInstruction(opCMP, "reg64,reg/mem64", "3B/r", {}, {cpuAMD64});
		AddInstruction(opCMP, "AL,imm8", "3Cib", {}, {cpu8086});
		AddInstruction(opCMP, "AX,imm16", "3Diw", {optO16}, {cpu8086});
		AddInstruction(opCMP, "EAX,imm32", "3Did", {optO32}, {cpu386});
		AddInstruction(opCMP, "RAX,simm32", "3Did", {}, {cpuAMD64});
		AddInstruction(opCMP, "reg/mem8,imm8", "80/7ib", {}, {cpu8086});
		AddInstruction(opCMP, "reg/mem16,imm16", "81/7iw", {optO16}, {cpu8086});
		AddInstruction(opCMP, "reg/mem32,imm32", "81/7id", {optO32}, {cpu386});
		AddInstruction(opCMP, "reg/mem64,simm32", "81/7id", {}, {cpuAMD64});
		AddInstruction(opCMP, "reg/mem16,simm8", "83/7ib", {optO16}, {cpu8086});
		AddInstruction(opCMP, "reg/mem32,simm8", "83/7ib", {optO32}, {cpu386});
		AddInstruction(opCMP, "reg/mem64,simm8", "83/7ib", {}, {cpuAMD64});
		AddInstruction(opCMPPD, "xmm1,xmm2/mem128,uimm8", "0FC2/rib", {optPOP}, {cpuSSE2});
		AddInstruction(opCMPPS, "xmm1,xmm2/mem128,uimm8", "0FC2/rib", {}, {cpuSSE});
		AddInstruction(opCMPS, "mem8,mem8", "A6", {}, {cpu8086});
		AddInstruction(opCMPS, "mem16,mem16", "A7", {optO16}, {cpu8086});
		AddInstruction(opCMPS, "mem32,mem32", "A7", {optO32}, {cpu386});
		AddInstruction(opCMPS, "mem64,mem64", "A7", {}, {cpuAMD64});
		AddInstruction(opCMPSB, "", "A6", {}, {cpu8086});
		AddInstruction(opCMPSD, "", "A7", {optO32}, {cpu386});
		AddInstruction(opCMPSD, "xmm1,xmm2/mem64,uimm8", "F20FC2/rib", {}, {cpuSSE2});
		AddInstruction(opCMPSQ, "", "A7", {}, {cpuAMD64});
		AddInstruction(opCMPSS, "xmm1,xmm2/mem32,uimm8", "F30FC2/rib", {}, {cpuSSE});
		AddInstruction(opCMPSW, "", "A7", {optO16}, {cpu8086});
		AddInstruction(opCMPXCHG, "reg/mem8,reg8", "0FB0/r", {}, {cpuPentium});
		AddInstruction(opCMPXCHG, "reg/mem16,reg16", "0FB1/r", {optO16}, {cpuPentium});
		AddInstruction(opCMPXCHG, "reg/mem32,reg32", "0FB1/r", {optO32}, {cpuPentium});
		AddInstruction(opCMPXCHG, "reg/mem64,reg64", "0FB1/r", {}, {cpuAMD64});
		AddInstruction(opCMPXCHG16B, "mem128", "0FC7/1m1", {}, {cpuSSE2});
		AddInstruction(opCMPXCHG8B, "mem64", "0FC7/1m6", {}, {cpuPentium});
		AddInstruction(opCOMISD, "xmm1,xmm2/mem64", "0F2F/r", {optPOP}, {cpuSSE2});
		AddInstruction(opCOMISS, "xmm1,xmm2/mem32", "0F2F/r", {}, {cpuSSE});
		AddInstruction(opCPUID, "", "0FA2", {}, {cpuPentium});
		AddInstruction(opCQO, "", "99", {optO64}, {cpuAMD64});
		AddInstruction(opCVTDQ2PD, "xmm1,xmm2/mem64", "F30FE6/r", {}, {cpuSSE2});
		AddInstruction(opCVTDQ2PS, "xmm1,xmm2/mem128", "0F5B/r", {}, {cpuSSE2});
		AddInstruction(opCVTPD2DQ, "xmm1,xmm2/mem128", "F20FE6/r", {}, {cpuSSE2});
		AddInstruction(opCVTPD2PI, "mmx,xmm2/mem128", "0F2D/r", {optPOP}, {cpuSSE2});
		AddInstruction(opCVTPD2PI, "mmx,xmm2/mem128", "0F2D/r", {optPOP}, {cpuSSE2});
		AddInstruction(opCVTPD2PI, "mmx,xmm/mem128", "0F2C/r", {optPOP}, {cpuSSE2});
		AddInstruction(opCVTPD2PS, "xmm1,xmm2/mem128", "0F5A/r", {optPOP}, {cpuSSE2});
		AddInstruction(opCVTPI2PD, "xmm,mmx/mem64", "0F2A/r", {optPOP}, {cpuSSE2});
		AddInstruction(opCVTPI2PD, "xmm,mmx/mem64", "0F2A/r", {optPOP}, {cpuSSE2});
		AddInstruction(opCVTPI2PS, "xmm,mmx/mem64", "0F2A/r", {}, {cpuSSE});
		AddInstruction(opCVTPI2PS, "xmm,mmx/mem64", "0F2A/r", {}, {cpuSSE});
		AddInstruction(opCVTPS2DQ, "xmm1,xmm2/mem128", "0F5B/r", {optPOP}, {cpuSSE2});
		AddInstruction(opCVTPS2PD, "xmm1,xmm2/mem64", "0F5A/r", {}, {cpuSSE2});
		AddInstruction(opCVTPS2PI, "mmx,xmm/mem64", "0F2D/r", {}, {cpuSSE});
		AddInstruction(opCVTPS2PI, "mmx,xmm/mem64", "0F2D/r", {}, {cpuSSE});
		AddInstruction(opCVTSD2SI, "reg32,xmm/mem64", "F20F2D/r", {}, {cpuSSE2});
		AddInstruction(opCVTSD2SI, "reg64,xmm/mem64", "F20F2D/r", {}, {cpuAMD64,cpuSSE2});
		AddInstruction(opCVTSD2SS, "xmm1,xmm2/mem64", "F20F5A/r", {}, {cpuSSE2});
		AddInstruction(opCVTSI2SD, "xmm,reg/mem32", "F20F2A/r", {}, {cpuSSE2});
		AddInstruction(opCVTSI2SD, "xmm,reg/mem64", "F20F2A/r", {}, {cpuAMD64,cpuSSE2});
		AddInstruction(opCVTSI2SS, "xmm,reg/mem32", "F30F2A/r", {}, {cpuSSE});
		AddInstruction(opCVTSI2SS, "xmm,reg/mem64", "F30F2A/r", {}, {cpuAMD64,cpuSSE});
		AddInstruction(opCVTSS2SD, "xmm1,xmm2/mem32", "F30F5A/r", {}, {cpuSSE2});
		AddInstruction(opCVTSS2SI, "reg32,xmm2/mem32", "F30F2D/r", {}, {cpuSSE});
		AddInstruction(opCVTSS2SI, "reg64,xmm2/mem32", "F30F2D/r", {}, {cpuAMD64,cpuSSE});
		AddInstruction(opCVTTPD2DQ, "xmm1,xmm2/mem128", "0FE6/r", {optPOP}, {cpuSSE2});
		AddInstruction(opCVTTPD2PI, "mmx,xmm/mem128", "0F2C/r", {optPOP}, {cpuSSE2});
		AddInstruction(opCVTTPS2DQ, "xmm1,xmm2/mem128", "F30F5B/r", {}, {cpuSSE2});
		AddInstruction(opCVTTPS2PI, "mmx,xmm/mem64", "0F2C/r", {}, {cpuSSE});
		AddInstruction(opCVTTPS2PI, "mmx,xmm/mem64", "0F2C/r", {}, {cpuSSE});
		AddInstruction(opCVTTSD2SI, "reg32,xmm/mem64", "F20F2C/r", {}, {cpuSSE2});
		AddInstruction(opCVTTSD2SI, "reg64,xmm/mem64", "F20F2C/r", {}, {cpuAMD64,cpuSSE2});
		AddInstruction(opCVTTSS2SI, "reg32,xmm/mem32", "F30F2C/r", {}, {cpuSSE});
		AddInstruction(opCVTTSS2SI, "reg64,xmm/mem32", "F30F2C/r", {}, {cpuAMD64,cpuSSE});
		AddInstruction(opCWD, "", "99", {optO16}, {cpu8086});
		AddInstruction(opCWDE, "", "98", {optO32}, {cpu386});
		AddInstruction(opDAA, "", "27", {optNot64}, {cpu8086});
		AddInstruction(opDAS, "", "2F", {optNot64}, {cpu8086});
		AddInstruction(opDEC, "reg16", "48rw", {optO16,optNot64}, {cpu8086});
		AddInstruction(opDEC, "reg32", "48rd", {optO32,optNot64}, {cpu386});
		AddInstruction(opDEC, "reg/mem8", "FE/1", {}, {cpu8086});
		AddInstruction(opDEC, "reg/mem16", "FF/1", {optO16}, {cpu8086});
		AddInstruction(opDEC, "reg/mem32", "FF/1", {optO32}, {cpu386});
		AddInstruction(opDEC, "reg/mem64", "FF/1", {}, {cpuAMD64});
		AddInstruction(opDIV, "reg/mem8", "F6/6", {}, {cpu8086});
		AddInstruction(opDIV, "reg/mem16", "F7/6", {optO16}, {cpu8086});
		AddInstruction(opDIV, "reg/mem32", "F7/6", {optO32}, {cpu386});
		AddInstruction(opDIV, "reg/mem64", "F7/6", {}, {cpuAMD64});
		AddInstruction(opDIVPD, "xmm1,xmm2/mem128", "0F5E/r", {optPOP}, {cpuSSE2});
		AddInstruction(opDIVPS, "xmm1,xmm2/mem128", "0F5E/r", {}, {cpuSSE});
		AddInstruction(opDIVSD, "xmm1,xmm2/mem64", "F20F5E/r", {}, {cpuSSE2});
		AddInstruction(opDIVSS, "xmm1,xmm2/mem32", "F30F5E/r", {}, {cpuSSE});
		AddInstruction(opEMMS, "", "0F77", {}, {cpuMMX});
		AddInstruction(opENTER, "uimm16,uimm8", "C8iwib", {}, {cpu186});
		AddInstruction(opF2XM1, "", "D9F0", {}, {cpu8086,cpuFPU});
		AddInstruction(opFABS, "", "D9E1", {}, {cpu8086,cpuFPU});
		AddInstruction(opFADD, "mem32real", "D8/0", {}, {cpu8086,cpuFPU});
		AddInstruction(opFADD, "mem64real", "DC/0", {}, {cpu8086,cpuFPU});
		AddInstruction(opFADD, "ST(0),ST(i)", "D8C0+i", {}, {cpu8086,cpuFPU});
		AddInstruction(opFADD, "ST(i),ST(0)", "DCC0+i", {}, {cpu8086,cpuFPU});
		AddInstruction(opFADDP, "", "DEC1", {}, {cpu8086,cpuFPU});
		AddInstruction(opFADDP, "ST(i),ST(0)", "DEC0+i", {}, {cpu8086,cpuFPU});
		AddInstruction(opFBLD, "mem80dec", "DF/4", {}, {cpu8086,cpuFPU});
		AddInstruction(opFBSTP, "mem80dec", "DF/6", {}, {cpu8086,cpuFPU});
		AddInstruction(opFCHS, "", "D9E0", {}, {cpu8086,cpuFPU});
		AddInstruction(opFCLEX, "", "9BDBE2", {}, {cpu8086,cpuFPU});
		AddInstruction(opFCMOVB, "ST(0),ST(i)", "DAC0+i", {}, {cpuP6,cpuFPU});
		AddInstruction(opFCMOVBE, "ST(0),ST(i)", "DAD0+i", {}, {cpuP6,cpuFPU});
		AddInstruction(opFCMOVE, "ST(0),ST(i)", "DAC8+i", {}, {cpuP6,cpuFPU});
		AddInstruction(opFCMOVNB, "ST(0),ST(i)", "DBC0+i", {}, {cpuP6,cpuFPU});
		AddInstruction(opFCMOVNBE, "ST(0),ST(i)", "DBD0+i", {}, {cpuP6,cpuFPU});
		AddInstruction(opFCMOVNE, "ST(0),ST(i)", "DBC8+i", {}, {cpuP6,cpuFPU});
		AddInstruction(opFCMOVNU, "ST(0),ST(i)", "DBD8+i", {}, {cpuP6,cpuFPU});
		AddInstruction(opFCMOVU, "ST(0),ST(i)", "DAD8+i", {}, {cpuP6,cpuFPU});
		AddInstruction(opFCOM, "", "D8D1", {}, {cpu8086,cpuFPU});
		AddInstruction(opFCOM, "ST(i)", "D8D0+i", {}, {cpu8086,cpuFPU});
		AddInstruction(opFCOM, "mem32real", "D8/2", {}, {cpu8086,cpuFPU});
		AddInstruction(opFCOM, "mem64real", "DC/2", {}, {cpu8086,cpuFPU});
		AddInstruction(opFCOMI, "ST(0),ST(i)", "DBF0+i", {}, {cpuP6,cpuFPU});
		AddInstruction(opFCOMIP, "ST(0),ST(i)", "DFF0+i", {}, {cpuP6,cpuFPU});
		AddInstruction(opFCOMP, "", "D8D9", {}, {cpu8086,cpuFPU});
		AddInstruction(opFCOMP, "ST(i)", "D8D8+i", {}, {cpu8086,cpuFPU});
		AddInstruction(opFCOMP, "mem32real", "D8/3", {}, {cpu8086,cpuFPU});
		AddInstruction(opFCOMP, "mem64real", "DC/3", {}, {cpu8086,cpuFPU});
		AddInstruction(opFCOMPP, "", "DED9", {}, {cpu8086,cpuFPU});
		AddInstruction(opFCOS, "", "D9FF", {}, {cpu386,cpuFPU});
		AddInstruction(opFDECSTP, "", "D9F6", {}, {cpu8086,cpuFPU});
		AddInstruction(opFDIV, "mem32real", "D8/6", {}, {cpu8086,cpuFPU});
		AddInstruction(opFDIV, "mem64real", "DC/6", {}, {cpu8086,cpuFPU});
		AddInstruction(opFDIV, "ST(0),ST(i)", "D8F0+i", {}, {cpu8086,cpuFPU});
		AddInstruction(opFDIV, "ST(i),ST(0)", "DCF8+i", {}, {cpu8086,cpuFPU});
		AddInstruction(opFDIVP, "", "DEF9", {}, {cpu8086,cpuFPU});
		AddInstruction(opFDIVP, "ST(i),ST(0)", "DEF8+i", {}, {cpu8086,cpuFPU});
		AddInstruction(opFDIVR, "mem32real", "D8/7", {}, {cpu8086,cpuFPU});
		AddInstruction(opFDIVR, "mem64real", "DC/7", {}, {cpu8086,cpuFPU});
		AddInstruction(opFDIVR, "ST(0),ST(i)", "D8F8+i", {}, {cpu8086,cpuFPU});
		AddInstruction(opFDIVR, "ST(i),ST(0)", "DCF0+i", {}, {cpu8086,cpuFPU});
		AddInstruction(opFDIVRP, "", "DEF1", {}, {cpu8086,cpuFPU});
		AddInstruction(opFDIVRP, "ST(i),ST(0)", "DEF0+i", {}, {cpu8086,cpuFPU});
		AddInstruction(opFEMMS, "", "0F0E", {}, {cpu3DNow});
		AddInstruction(opFFREE, "ST(i)", "DDC0+i", {}, {cpu8086,cpuFPU});
		AddInstruction(opFIADD, "mem16int", "DE/0", {}, {cpu8086,cpuFPU});
		AddInstruction(opFIADD, "mem32int", "DA/0", {}, {cpu8086,cpuFPU});
		AddInstruction(opFICOM, "mem16int", "DE/2", {}, {cpu8086,cpuFPU});
		AddInstruction(opFICOM, "mem32int", "DA/2", {}, {cpu8086,cpuFPU});
		AddInstruction(opFICOMP, "mem16int", "DE/3", {}, {cpu8086,cpuFPU});
		AddInstruction(opFICOMP, "mem32int", "DA/3", {}, {cpu8086,cpuFPU});
		AddInstruction(opFIDIV, "mem16int", "DE/6", {}, {cpu8086,cpuFPU});
		AddInstruction(opFIDIV, "mem32int", "DA/6", {}, {cpu8086,cpuFPU});
		AddInstruction(opFIDIVR, "mem16int", "DE/7", {}, {cpu8086,cpuFPU});
		AddInstruction(opFIDIVR, "mem32int", "DA/7", {}, {cpu8086,cpuFPU});
		AddInstruction(opFILD, "mem16int", "DF/0", {}, {cpu8086,cpuFPU});
		AddInstruction(opFILD, "mem32int", "DB/0", {}, {cpu8086,cpuFPU});
		AddInstruction(opFILD, "mem64int", "DF/5", {}, {cpu8086,cpuFPU});
		AddInstruction(opFIMUL, "mem16int", "DE/1", {}, {cpu8086,cpuFPU});
		AddInstruction(opFIMUL, "mem32int", "DA/1", {}, {cpu8086,cpuFPU});
		AddInstruction(opFINCSTP, "", "D9F7", {}, {cpu8086,cpuFPU});
		AddInstruction(opFINIT, "", "9BDBE3", {}, {cpu8086,cpuFPU});
		AddInstruction(opFIST, "mem16int", "DF/2", {}, {cpu8086,cpuFPU});
		AddInstruction(opFIST, "mem32int", "DB/2", {}, {cpu8086,cpuFPU});
		AddInstruction(opFISTP, "mem16int", "DF/3", {}, {cpu8086,cpuFPU});
		AddInstruction(opFISTP, "mem32int", "DB/3", {}, {cpu8086,cpuFPU});
		AddInstruction(opFISTP, "mem64int", "DF/7", {}, {cpu8086,cpuFPU});
		AddInstruction(opFISTTP, "mem16int", "DF/1", {}, {cpuFPU});
		AddInstruction(opFISTTP, "mem32int", "DB/1", {}, {cpuFPU});
		AddInstruction(opFISTTP, "mem64int", "DD/1", {}, {cpuFPU});
		AddInstruction(opFISUB, "mem16int", "DE/4", {}, {cpu8086,cpuFPU});
		AddInstruction(opFISUB, "mem32int", "DA/4", {}, {cpu8086,cpuFPU});
		AddInstruction(opFISUBR, "mem16int", "DE/5", {}, {cpu8086,cpuFPU});
		AddInstruction(opFISUBR, "mem32int", "DA/5", {}, {cpu8086,cpuFPU});
		AddInstruction(opFLD, "ST(i)", "D9C0+i", {}, {cpu8086,cpuFPU});
		AddInstruction(opFLD, "mem32real", "D9/0", {}, {cpu8086,cpuFPU});
		AddInstruction(opFLD, "mem64real", "DD/0", {}, {cpu8086,cpuFPU});
		AddInstruction(opFLD, "mem80real", "DB/5", {}, {cpu8086,cpuFPU});
		AddInstruction(opFLD1, "", "D9E8", {}, {cpu8086,cpuFPU});
		AddInstruction(opFLDCW, "mem2env", "D9/5", {}, {cpu8086,cpuFPU});
		AddInstruction(opFLDENV, "mem14/28env", "D9/4", {}, {cpu8086,cpuFPU});
		AddInstruction(opFLDL2E, "", "D9EA", {}, {cpu8086,cpuFPU});
		AddInstruction(opFLDL2T, "", "D9E9", {}, {cpu8086,cpuFPU});
		AddInstruction(opFLDLG2, "", "D9EC", {}, {cpu8086,cpuFPU});
		AddInstruction(opFLDLN2, "", "D9ED", {}, {cpu8086,cpuFPU});
		AddInstruction(opFLDPI, "", "D9EB", {}, {cpu8086,cpuFPU});
		AddInstruction(opFLDZ, "", "D9EE", {}, {cpu8086,cpuFPU});
		AddInstruction(opFMUL, "mem32real", "D8/1", {}, {cpu8086,cpuFPU});
		AddInstruction(opFMUL, "mem64real", "DC/1", {}, {cpu8086,cpuFPU});
		AddInstruction(opFMUL, "ST(0),ST(i)", "D8C8+i", {}, {cpu8086,cpuFPU});
		AddInstruction(opFMUL, "ST(i),ST(0)", "DCC8+i", {}, {cpu8086,cpuFPU});
		AddInstruction(opFMULP, "", "DEC9", {}, {cpu8086,cpuFPU});
		AddInstruction(opFMULP, "ST(i),ST(0)", "DEC8+i", {}, {cpu8086,cpuFPU});
		AddInstruction(opFNCLEX, "", "DBE2", {}, {cpu8086,cpuFPU});
		AddInstruction(opFNINIT, "", "DBE3", {}, {cpu8086,cpuFPU});
		AddInstruction(opFNOP, "", "D9D0", {}, {cpu8086,cpuFPU});
		AddInstruction(opFNSAVE, "mem94/108env", "DD/6", {}, {cpu8086,cpuFPU});
		AddInstruction(opFNSAVE, "mem94/108env", "DD/6", {}, {cpu8086,cpuFPU});
		AddInstruction(opFNSTCW, "mem2env", "D9/7", {}, {cpu8086,cpuFPU});
		AddInstruction(opFNSTENV, "mem14/28env", "D9/6", {}, {cpu8086,cpuFPU});
		AddInstruction(opFNSTSW, "AX", "DFE0", {}, {cpu286,cpuFPU});
		AddInstruction(opFNSTSW, "mem2env", "DD/7", {}, {cpu8086,cpuFPU});
		AddInstruction(opFPATAN, "", "D9F3", {}, {cpu8086,cpuFPU});
		AddInstruction(opFPREM, "", "D9F8", {}, {cpu8086,cpuFPU});
		AddInstruction(opFPREM1, "", "D9F5", {}, {cpu386,cpuFPU});
		AddInstruction(opFPTAN, "", "D9F2", {}, {cpu8086,cpuFPU});
		AddInstruction(opFRNDINT, "", "D9FC", {}, {cpu8086,cpuFPU});
		AddInstruction(opFRSTOR, "mem94/108env", "DD/4", {}, {cpu8086,cpuFPU});
		AddInstruction(opFRSTOR, "mem94/108env", "DD/4", {}, {cpu8086,cpuFPU});
		AddInstruction(opFSAVE, "mem94/108env", "9BDD/6", {}, {cpu8086,cpuFPU});
		AddInstruction(opFSAVE, "mem94/108env", "9BDD/6", {}, {cpu8086,cpuFPU});
		AddInstruction(opFSCALE, "", "D9FD", {}, {cpu8086,cpuFPU});
		AddInstruction(opFSIN, "", "D9FE", {}, {cpu386,cpuFPU});
		AddInstruction(opFSINCOS, "", "D9FB", {}, {cpu386,cpuFPU});
		AddInstruction(opFSQRT, "", "D9FA", {}, {cpu8086,cpuFPU});
		AddInstruction(opFST, "ST(i)", "DDD0+i", {}, {cpu8086,cpuFPU});
		AddInstruction(opFST, "mem32real", "D9/2", {}, {cpu8086,cpuFPU});
		AddInstruction(opFST, "mem64real", "DD/2", {}, {cpu8086,cpuFPU});
		AddInstruction(opFSTCW, "mem2env", "9BD9/7", {}, {cpu8086,cpuFPU});
		AddInstruction(opFSTENV, "mem14/28env", "9BD9/6", {}, {cpu8086,cpuFPU});
		AddInstruction(opFSTP, "ST(i)", "DDD8+i", {}, {cpu8086,cpuFPU});
		AddInstruction(opFSTP, "mem32real", "D9/3", {}, {cpu8086,cpuFPU});
		AddInstruction(opFSTP, "mem64real", "DD/3", {}, {cpu8086,cpuFPU});
		AddInstruction(opFSTP, "mem80real", "DB/7", {}, {cpu8086,cpuFPU});
		AddInstruction(opFSTSW, "AX", "9BDFE0", {}, {cpu286,cpuFPU});
		AddInstruction(opFSTSW, "mem2env", "9BDD/7", {}, {cpu8086,cpuFPU});
		AddInstruction(opFSUB, "mem32real", "D8/4", {}, {cpu8086,cpuFPU});
		AddInstruction(opFSUB, "mem64real", "DC/4", {}, {cpu8086,cpuFPU});
		AddInstruction(opFSUB, "ST(0),ST(i)", "D8E0+i", {}, {cpu8086,cpuFPU});
		AddInstruction(opFSUB, "ST(i),ST(0)", "DCE8+i", {}, {cpu8086,cpuFPU});
		AddInstruction(opFSUBP, "", "DEE9", {}, {cpu8086,cpuFPU});
		AddInstruction(opFSUBP, "ST(i),ST(0)", "DEE8+i", {}, {cpu8086,cpuFPU});
		AddInstruction(opFSUBR, "mem32real", "D8/5", {}, {cpu8086,cpuFPU});
		AddInstruction(opFSUBR, "mem64real", "DC/5", {}, {cpu8086,cpuFPU});
		AddInstruction(opFSUBR, "ST(0),ST(i)", "D8E8+i", {}, {cpu8086,cpuFPU});
		AddInstruction(opFSUBR, "ST(i),ST(0)", "DCE0+i", {}, {cpu8086,cpuFPU});
		AddInstruction(opFSUBRP, "", "DEE1", {}, {cpu8086,cpuFPU});
		AddInstruction(opFSUBRP, "ST(i),ST(0)", "DEE0+i", {}, {cpu8086,cpuFPU});
		AddInstruction(opFTST, "", "D9E4", {}, {cpu8086,cpuFPU});
		AddInstruction(opFUCOM, "", "DDE1", {}, {cpu386,cpuFPU});
		AddInstruction(opFUCOM, "ST(i)", "DDE0+i", {}, {cpu386,cpuFPU});
		AddInstruction(opFUCOMI, "ST(0),ST(i)", "DBE8+i", {}, {cpuP6,cpuFPU});
		AddInstruction(opFUCOMIP, "ST(0),ST(i)", "DFE8+i", {}, {cpuP6,cpuFPU});
		AddInstruction(opFUCOMP, "", "DDE9", {}, {cpu386,cpuFPU});
		AddInstruction(opFUCOMP, "ST(i)", "DDE8+i", {}, {cpu386,cpuFPU});
		AddInstruction(opFUCOMPP, "", "DAE9", {}, {cpu386,cpuFPU});
		AddInstruction(opFWAIT, "", "9B", {}, {cpu8086});
		AddInstruction(opFXAM, "", "D9E5", {}, {cpu8086,cpuFPU});
		AddInstruction(opFXCH, "", "D9C9", {}, {cpu8086,cpuFPU});
		AddInstruction(opFXCH, "ST(i)", "D9C8+i", {}, {cpu8086,cpuFPU});
		AddInstruction(opFXRSTOR, "mem512env", "0FAE/1", {}, {cpuP6,cpuSSE,cpuFPU});
		AddInstruction(opFXRSTOR, "mem512env", "0FAE/1", {}, {cpuP6,cpuSSE,cpuFPU});
		AddInstruction(opFXRSTOR, "mem512env", "0FAE/1", {}, {cpuP6,cpuSSE,cpuFPU});
		AddInstruction(opFXSAVE, "mem512env", "0FAE/0", {}, {cpuP6,cpuSSE,cpuFPU});
		AddInstruction(opFXSAVE, "mem512env", "0FAE/0", {}, {cpuP6,cpuSSE,cpuFPU});
		AddInstruction(opFXSAVE, "mem512env", "0FAE/0", {}, {cpuP6,cpuSSE,cpuFPU});
		AddInstruction(opFXTRACT, "", "D9F4", {}, {cpu8086,cpuFPU});
		AddInstruction(opFYL2X, "", "D9F1", {}, {cpu8086,cpuFPU});
		AddInstruction(opFYL2XP1, "", "D9F9", {}, {cpu8086,cpuFPU});
		AddInstruction(opHADDPD, "xmm1,xmm2/mem128", "0F7C/r", {optPOP}, {cpuSSE3});
		AddInstruction(opHADDPS, "xmm1,xmm2/mem128", "F20F7C/r", {}, {cpuSSE3});
		AddInstruction(opHLT, "", "F4", {}, {cpu8086,cpuPrivileged});
		AddInstruction(opHSUBPD, "xmm1,xmm2/mem128", "0F7D/r", {optPOP}, {cpuSSE3});
		AddInstruction(opHSUBPS, "xmm1,xmm2/mem128", "F20F7D/r", {}, {cpuSSE3});
		AddInstruction(opIDIV, "reg/mem8", "F6/7", {}, {cpu8086});
		AddInstruction(opIDIV, "reg/mem16", "F7/7", {optO16}, {cpu8086});
		AddInstruction(opIDIV, "reg/mem32", "F7/7", {optO32}, {cpu386});
		AddInstruction(opIDIV, "reg/mem64", "F7/7", {}, {cpuAMD64});
		AddInstruction(opIMUL, "reg/mem8", "F6/5", {}, {cpu8086});
		AddInstruction(opIMUL, "reg/mem16", "F7/5", {optO16}, {cpu8086});
		AddInstruction(opIMUL, "reg/mem32", "F7/5", {optO32}, {cpu386});
		AddInstruction(opIMUL, "reg/mem64", "F7/5", {}, {cpuAMD64});
		AddInstruction(opIMUL, "reg16,reg/mem16", "0FAF/r", {optO16}, {cpu386});
		AddInstruction(opIMUL, "reg32,reg/mem32", "0FAF/r", {optO32}, {cpu386});
		AddInstruction(opIMUL, "reg64,reg/mem64", "0FAF/r", {}, {cpuAMD64});
		AddInstruction(opIMUL, "reg16,reg/mem16,simm8", "6B/rib", {optO16}, {cpu186});
		AddInstruction(opIMUL, "reg32,reg/mem32,simm8", "6B/rib", {optO32}, {cpu386});
		AddInstruction(opIMUL, "reg64,reg/mem64,simm8", "6B/rib", {}, {cpuAMD64});
		AddInstruction(opIMUL, "reg16,reg/mem16,simm16", "69/riw", {optO16}, {cpu186});
		AddInstruction(opIMUL, "reg32,reg/mem32,simm32", "69/rid", {optO32}, {cpu386});
		AddInstruction(opIMUL, "reg64,reg/mem64,simm32", "69/rid", {}, {cpuAMD64});
		AddInstruction(opIN, "AL,uimm8", "E4ib", {}, {cpu8086});
		AddInstruction(opIN, "AX,uimm8", "E5ib", {optO16}, {cpu8086});
		AddInstruction(opIN, "EAX,uimm8", "E5ib", {optO32}, {cpu386});
		AddInstruction(opIN, "AL,DX", "EC", {}, {cpu8086});
		AddInstruction(opIN, "AX,DX", "ED", {optO16}, {cpu8086});
		AddInstruction(opIN, "EAX,DX", "ED", {optO32}, {cpu386});
		AddInstruction(opINC, "reg16", "40rw", {optO16,optNot64}, {cpu8086});
		AddInstruction(opINC, "reg32", "40rd", {optO32,optNot64}, {cpu386});
		AddInstruction(opINC, "reg/mem8", "FE/0", {}, {cpu8086});
		AddInstruction(opINC, "reg/mem16", "FF/0", {optO16}, {cpu8086});
		AddInstruction(opINC, "reg/mem32", "FF/0", {optO32}, {cpu386});
		AddInstruction(opINC, "reg/mem64", "FF/0", {}, {cpuAMD64});
		AddInstruction(opINS, "mem8,DX", "6C", {}, {cpu186});
		AddInstruction(opINS, "mem16,DX", "6D", {optO16}, {cpu186});
		AddInstruction(opINS, "mem32,DX", "6D", {optO32}, {cpu386});
		AddInstruction(opINSB, "", "6C", {}, {cpu186});
		AddInstruction(opINSD, "", "6D", {optO32}, {cpu386});
		AddInstruction(opINSW, "", "6D", {optO16}, {cpu186});
		AddInstruction(opINT, "uimm8", "CDib", {}, {cpu8086});
		AddInstruction(opINT3, "", "CC", {}, {cpu8086});
		AddInstruction(opINTO, "", "CE", {optNot64}, {cpu8086});
		AddInstruction(opINVD, "", "0F08", {}, {cpu486,cpuPrivileged});
		AddInstruction(opINVLPG, "mem8", "0F01/7", {}, {cpu486});
		AddInstruction(opINVLPGA, "rAX,ECX", "0F01DF", {}, {cpu386});
		AddInstruction(opIRET, "", "CF", {optO16}, {cpu8086});
		AddInstruction(opIRETD, "", "CF", {optO32}, {cpu386});
		AddInstruction(opIRETQ, "", "CF", {optO64}, {cpuAMD64});
		AddInstruction(opJA, "rel8off", "77cb", {}, {cpu8086});
		AddInstruction(opJA, "rel16off", "0F87cw", {optO16}, {cpu386});
		AddInstruction(opJA, "rel32off", "0F87cd", {optO32}, {cpu386});
		AddInstruction(opJAE, "rel8off", "73cb", {}, {cpu8086});
		AddInstruction(opJAE, "rel16off", "0F83cw", {optO16}, {cpu386});
		AddInstruction(opJAE, "rel32off", "0F83cd", {optO32}, {cpu386});
		AddInstruction(opJB, "rel8off", "72cb", {}, {cpu8086});
		AddInstruction(opJB, "rel16off", "0F82cw", {optO16}, {cpu386});
		AddInstruction(opJB, "rel32off", "0F82cd", {optO32}, {cpu386});
		AddInstruction(opJBE, "rel8off", "76cb", {}, {cpu8086});
		AddInstruction(opJBE, "rel16off", "0F86cw", {optO16}, {cpu386});
		AddInstruction(opJBE, "rel32off", "0F86cd", {optO32}, {cpu386});
		AddInstruction(opJC, "rel8off", "72cb", {}, {cpu8086});
		AddInstruction(opJC, "rel16off", "0F82cw", {optO16}, {cpu386});
		AddInstruction(opJC, "rel32off", "0F82cd", {optO32}, {cpu386});
		AddInstruction(opJCXZ, "rel8off", "E3cb", {optA16}, {cpu8086});
		AddInstruction(opJE, "rel8off", "74cb", {}, {cpu8086});
		AddInstruction(opJE, "rel16off", "0F84cw", {optO16}, {cpu386});
		AddInstruction(opJE, "rel32off", "0F84cd", {optO32}, {cpu386});
		AddInstruction(opJECXZ, "rel8off", "E3cb", {optA32}, {cpu386});
		AddInstruction(opJG, "rel8off", "7Fcb", {}, {cpu8086});
		AddInstruction(opJG, "rel16off", "0F8Fcw", {optO16}, {cpu386});
		AddInstruction(opJG, "rel32off", "0F8Fcd", {optO32}, {cpu386});
		AddInstruction(opJGE, "rel8off", "7Dcb", {}, {cpu8086});
		AddInstruction(opJGE, "rel16off", "0F8Dcw", {optO16}, {cpu386});
		AddInstruction(opJGE, "rel32off", "0F8Dcd", {optO32}, {cpu386});
		AddInstruction(opJL, "rel8off", "7Ccb", {}, {cpu8086});
		AddInstruction(opJL, "rel16off", "0F8Ccw", {optO16}, {cpu386});
		AddInstruction(opJL, "rel32off", "0F8Ccd", {optO32}, {cpu386});
		AddInstruction(opJLE, "rel8off", "7Ecb", {}, {cpu8086});
		AddInstruction(opJLE, "rel16off", "0F8Ecw", {optO16}, {cpu386});
		AddInstruction(opJLE, "rel32off", "0F8Ecd", {optO32}, {cpu386});
		AddInstruction(opJMP, "rel8off", "EBcb", {}, {cpu8086});
		AddInstruction(opJMP, "rel16off", "E9cw", {optO16}, {cpu8086});
		AddInstruction(opJMP, "rel32off", "E9cd", {optO32}, {cpu8086});
		AddInstruction(opJMP, "reg/mem16", "FF/4", {optO16}, {cpu8086});
		AddInstruction(opJMP, "reg/mem32", "FF/4", {optO32}, {cpu386});
		AddInstruction(opJMP, "reg/mem64", "FF/4", {}, {cpuAMD64});
		AddInstruction(opJMPFAR, "pntr16:16", "EAcd", {optO16,optNot64}, {cpu8086});
		AddInstruction(opJMPFAR, "pntr16:32", "EAcp", {optO32,optNot64}, {cpu386});
		AddInstruction(opJMPFAR, "mem16:16", "FF/5", {optO16}, {cpu8086});
		AddInstruction(opJMPFAR, "mem16:32", "FF/5", {optO32}, {cpu386});
		AddInstruction(opJNA, "rel8off", "76cb", {}, {cpu8086});
		AddInstruction(opJNA, "rel16off", "0F86cw", {optO16}, {cpu386});
		AddInstruction(opJNA, "rel32off", "0F86cd", {optO32}, {cpu386});
		AddInstruction(opJNAE, "rel8off", "72cb", {}, {cpu8086});
		AddInstruction(opJNAE, "rel16off", "0F82cw", {optO16}, {cpu386});
		AddInstruction(opJNAE, "rel32off", "0F82cd", {optO32}, {cpu386});
		AddInstruction(opJNB, "rel8off", "73cb", {}, {cpu8086});
		AddInstruction(opJNB, "rel16off", "0F83cw", {optO16}, {cpu386});
		AddInstruction(opJNB, "rel32off", "0F83cd", {optO32}, {cpu386});
		AddInstruction(opJNBE, "rel8off", "77cb", {}, {cpu8086});
		AddInstruction(opJNBE, "rel16off", "0F87cw", {optO16}, {cpu386});
		AddInstruction(opJNBE, "rel32off", "0F87cd", {optO32}, {cpu386});
		AddInstruction(opJNC, "rel8off", "73cb", {}, {cpu8086});
		AddInstruction(opJNC, "rel16off", "0F83cw", {optO16}, {cpu386});
		AddInstruction(opJNC, "rel32off", "0F83cd", {optO32}, {cpu386});
		AddInstruction(opJNE, "rel8off", "75cb", {}, {cpu8086});
		AddInstruction(opJNE, "rel16off", "0F85cw", {optO16}, {cpu386});
		AddInstruction(opJNE, "rel32off", "0F85cd", {optO32}, {cpu386});
		AddInstruction(opJNG, "rel8off", "7Ecb", {}, {cpu8086});
		AddInstruction(opJNG, "rel16off", "0F8Ecw", {optO16}, {cpu386});
		AddInstruction(opJNG, "rel32off", "0F8Ecd", {optO32}, {cpu386});
		AddInstruction(opJNGE, "rel8off", "7Ccb", {}, {cpu8086});
		AddInstruction(opJNGE, "rel16off", "0F8Ccw", {optO16}, {cpu386});
		AddInstruction(opJNGE, "rel32off", "0F8Ccd", {optO32}, {cpu386});
		AddInstruction(opJNL, "rel8off", "7Dcb", {}, {cpu8086});
		AddInstruction(opJNL, "rel16off", "0F8Dcw", {optO16}, {cpu386});
		AddInstruction(opJNL, "rel32off", "0F8Dcd", {optO32}, {cpu386});
		AddInstruction(opJNLE, "rel8off", "7Fcb", {}, {cpu8086});
		AddInstruction(opJNLE, "rel16off", "0F8Fcw", {optO16}, {cpu386});
		AddInstruction(opJNLE, "rel32off", "0F8Fcd", {optO32}, {cpu386});
		AddInstruction(opJNO, "rel8off", "71cb", {}, {cpu8086});
		AddInstruction(opJNO, "rel16off", "0F81cw", {optO16}, {cpu386});
		AddInstruction(opJNO, "rel32off", "0F81cd", {optO32}, {cpu386});
		AddInstruction(opJNP, "rel8off", "7Bcb", {}, {cpu8086});
		AddInstruction(opJNP, "rel16off", "0F8Bcw", {optO16}, {cpu386});
		AddInstruction(opJNP, "rel32off", "0F8Bcd", {optO32}, {cpu386});
		AddInstruction(opJNS, "rel8off", "79cb", {}, {cpu8086});
		AddInstruction(opJNS, "rel16off", "0F89cw", {optO16}, {cpu386});
		AddInstruction(opJNS, "rel32off", "0F89cd", {optO32}, {cpu386});
		AddInstruction(opJNZ, "rel8off", "75cb", {}, {cpu8086});
		AddInstruction(opJNZ, "rel16off", "0F85cw", {optO16}, {cpu386});
		AddInstruction(opJNZ, "rel32off", "0F85cd", {optO32}, {cpu386});
		AddInstruction(opJO, "rel8off", "70cb", {}, {cpu8086});
		AddInstruction(opJO, "rel16off", "0F80cw", {optO16}, {cpu386});
		AddInstruction(opJO, "rel32off", "0F80cd", {optO32}, {cpu386});
		AddInstruction(opJP, "rel8off", "7Acb", {}, {cpu8086});
		AddInstruction(opJP, "rel16off", "0F8Acw", {optO16}, {cpu386});
		AddInstruction(opJP, "rel32off", "0F8Acd", {optO32}, {cpu386});
		AddInstruction(opJPE, "rel8off", "7Acb", {}, {cpu8086});
		AddInstruction(opJPE, "rel16off", "0F8Acw", {optO16}, {cpu386});
		AddInstruction(opJPE, "rel32off", "0F8Acd", {optO32}, {cpu386});
		AddInstruction(opJPO, "rel8off", "7Bcb", {}, {cpu8086});
		AddInstruction(opJPO, "rel16off", "0F8Bcw", {optO16}, {cpu386});
		AddInstruction(opJPO, "rel32off", "0F8Bcd", {optO32}, {cpu386});
		AddInstruction(opJRCXZ, "rel8off", "E3cb", {}, {cpuAMD64});
		AddInstruction(opJS, "rel8off", "78cb", {}, {cpu8086});
		AddInstruction(opJS, "rel16off", "0F88cw", {optO16}, {cpu386});
		AddInstruction(opJS, "rel32off", "0F88cd", {optO32}, {cpu386});
		AddInstruction(opJZ, "rel8off", "74cb", {}, {cpu8086});
		AddInstruction(opJZ, "rel16off", "0F84cw", {optO16}, {cpu386});
		AddInstruction(opJZ, "rel32off", "0F84cd", {optO32}, {cpu386});
		AddInstruction(opLAHF, "", "9F", {}, {cpu8086});
		AddInstruction(opLAR, "reg16,reg/mem16", "0F02/r", {optO16}, {cpu286,cpuPrivileged});
		AddInstruction(opLAR, "reg32,reg/mem16", "0F02/r", {optO32}, {cpu286,cpuPrivileged});
		AddInstruction(opLAR, "reg64,reg/mem16", "0F02/r", {}, {cpuAMD64,cpuPrivileged});
		AddInstruction(opLDDQU, "xmm1,mem128", "F20FF0/r", {}, {cpuSSE3});
		AddInstruction(opLDMXCSR, "mem32", "0FAE/2", {}, {cpuSSE});
		AddInstruction(opLDS, "reg16,mem16:16", "C5/r", {optO16,optNot64}, {cpu8086});
		AddInstruction(opLDS, "reg32,mem16:32", "C5/r", {optO32,optNot64}, {cpu386});
		AddInstruction(opLEA, "reg16,mem", "8D/r", {optO16}, {cpu8086});
		AddInstruction(opLEA, "reg32,mem", "8D/r", {optO32}, {cpu386});
		AddInstruction(opLEA, "reg64,mem", "8D/r", {}, {cpuAMD64});
		AddInstruction(opLEAVE, "", "C9", {}, {cpu186});
		AddInstruction(opLES, "reg16,mem16:16", "C4/r", {optO16,optNot64}, {cpu8086});
		AddInstruction(opLES, "reg32,mem16:32", "C4/r", {optO32,optNot64}, {cpu386});
		AddInstruction(opLFENCE, "", "0FAEE8", {}, {cpuSSE2});
		AddInstruction(opLFS, "reg16,mem16:16", "0FB4/r", {optO16}, {cpu386});
		AddInstruction(opLFS, "reg32,mem16:32", "0FB4/r", {optO32}, {cpu386});
		AddInstruction(opLGDT, "mem16:32", "0F01/2", {}, {cpu286,cpuPrivileged});
		AddInstruction(opLGDT, "mem16:64", "0F01/2", {}, {cpuAMD64,cpuPrivileged});
		AddInstruction(opLGS, "reg16,mem16:16", "0FB5/r", {optO16}, {cpu386});
		AddInstruction(opLGS, "reg32,mem16:32", "0FB5/r", {optO32}, {cpu386});
		AddInstruction(opLIDT, "mem16:32", "0F01/3", {}, {cpu286,cpuPrivileged});
		AddInstruction(opLIDT, "mem16:64", "0F01/3", {}, {cpuAMD64,cpuPrivileged});
		AddInstruction(opLLDT, "reg/mem16", "0F00/2", {}, {cpu286,cpuPrivileged});
		AddInstruction(opLMSW, "reg/mem16", "0F01/6", {}, {cpu286,cpuPrivileged});
		AddInstruction(opLODS, "mem8", "AC", {}, {cpu8086});
		AddInstruction(opLODS, "mem16", "AD", {optO16}, {cpu8086});
		AddInstruction(opLODS, "mem32", "AD", {optO32}, {cpu386});
		AddInstruction(opLODS, "mem64", "AD", {}, {cpuAMD64});
		AddInstruction(opLODSB, "", "AC", {}, {cpu8086});
		AddInstruction(opLODSD, "", "AD", {optO32}, {cpu386});
		AddInstruction(opLODSQ, "", "AD", {}, {cpuAMD64});
		AddInstruction(opLODSW, "", "AD", {optO16}, {cpu8086});
		AddInstruction(opLOOP, "rel8off", "E2cb", {}, {cpu8086});
		AddInstruction(opLOOPE, "rel8off", "E1cb", {}, {cpu8086});
		AddInstruction(opLOOPNE, "rel8off", "E0cb", {}, {cpu8086});
		AddInstruction(opLOOPNZ, "rel8off", "E0cb", {}, {cpu8086});
		AddInstruction(opLOOPZ, "rel8off", "E1cb", {}, {cpu8086});
		AddInstruction(opLSL, "reg16,reg/mem16", "0F03/r", {}, {cpu286,cpuPrivileged});
		AddInstruction(opLSL, "reg32,reg/mem16", "0F03/r", {}, {cpu286,cpuPrivileged});
		AddInstruction(opLSL, "reg64,reg/mem16", "0F03/r", {}, {cpuAMD64,cpuPrivileged});
		AddInstruction(opLSS, "reg16,mem16:16", "0FB2/r", {optO16}, {cpu386});
		AddInstruction(opLSS, "reg32,mem16:32", "0FB2/r", {optO32}, {cpu386});
		AddInstruction(opLTR, "reg/mem16", "0F00/3", {}, {cpu286,cpuPrivileged});
		AddInstruction(opMASKMOVDQU, "xmm1,xmm2", "0FF7/r", {optPOP}, {cpuSSE2});
		AddInstruction(opMASKMOVQ, "mmx1,mmx2", "0FF7/r", {}, {cpuMMX});
		AddInstruction(opMAXPD, "xmm1,xmm2/mem128", "0F5F/r", {optPOP}, {cpuSSE2});
		AddInstruction(opMAXPS, "xmm1,xmm2/mem128", "0F5F/r", {}, {cpuSSE});
		AddInstruction(opMAXSD, "xmm1,xmm2/mem64", "F20F5F/r", {}, {cpuSSE2});
		AddInstruction(opMAXSS, "xmm1,xmm2/mem32", "F30F5F/r", {}, {cpuSSE});
		AddInstruction(opMFENCE, "", "0FAEF0", {}, {cpuSSE2});
		AddInstruction(opMINPD, "xmm1,xmm2/mem128", "0F5D/r", {optPOP}, {cpuSSE2});
		AddInstruction(opMINPS, "xmm1,xmm2/mem128", "0F5D/r", {}, {cpuSSE});
		AddInstruction(opMINSD, "xmm1,xmm2/mem64", "F20F5D/r", {}, {cpuSSE2});
		AddInstruction(opMINSS, "xmm1,xmm2/mem32", "F30F5D/r", {}, {cpuSSE});
		AddInstruction(opMOV, "reg/mem8,reg8", "88/r", {}, {cpu8086});
		AddInstruction(opMOV, "reg/mem16,reg16", "89/r", {optO16}, {cpu8086});
		AddInstruction(opMOV, "reg/mem32,reg32", "89/r", {optO32}, {cpu386});
		AddInstruction(opMOV, "reg/mem64,reg64", "89/r", {}, {cpuAMD64});
		AddInstruction(opMOV, "reg8,reg/mem8", "8A/r", {}, {cpu8086});
		AddInstruction(opMOV, "reg16,reg/mem16", "8B/r", {optO16}, {cpu8086});
		AddInstruction(opMOV, "reg32,reg/mem32", "8B/r", {optO32}, {cpu386});
		AddInstruction(opMOV, "reg64,reg/mem64", "8B/r", {}, {cpuAMD64});
		AddInstruction(opMOV, "reg8,imm8", "B0rbib", {}, {cpu8086});
		AddInstruction(opMOV, "reg16,imm16", "B8rwiw", {optO16}, {cpu8086});
		AddInstruction(opMOV, "reg32,imm32", "B8rdid", {optO32}, {cpu386});
		AddInstruction(opMOV, "reg64,imm64", "B8rqiq", {}, {cpuAMD64});
		AddInstruction(opMOV, "CRn,reg32", "0F22/r", {}, {cpu386});
		AddInstruction(opMOV, "CRn,reg64", "0F22/r", {}, {cpuAMD64});
		AddInstruction(opMOV, "reg32,CRn", "0F20/r", {}, {cpu386});
		AddInstruction(opMOV, "reg64,CRn", "0F20/r", {}, {cpuAMD64});
		AddInstruction(opMOV, "CR8,reg32", "F00F22/r", {}, {cpu386});
		AddInstruction(opMOV, "CR8,reg64", "F00F22/r", {}, {cpuAMD64});
		AddInstruction(opMOV, "reg32,CR8", "F00F20/r", {}, {cpu386});
		AddInstruction(opMOV, "reg64,CR8", "F00F20/r", {}, {cpuAMD64});
		AddInstruction(opMOV, "reg32,DRn", "0F21/r", {}, {cpu386});
		AddInstruction(opMOV, "reg64,DRn", "0F21/r", {}, {cpuAMD64});
		AddInstruction(opMOV, "DRn,reg32", "0F23/r", {}, {cpu386});
		AddInstruction(opMOV, "DRn,reg64", "0F23/r", {}, {cpuAMD64});
		AddInstruction(opMOV, "reg/mem16,segReg", "8C/r", {optO16}, {cpu8086});
		AddInstruction(opMOV, "reg/mem32,segReg", "8C/r", {optO32}, {cpu386});
		AddInstruction(opMOV, "reg/mem64,segReg", "8C/r", {}, {cpuAMD64});
		AddInstruction(opMOV, "segReg,reg/mem16", "8E/r", {optO16}, {cpu8086});
		AddInstruction(opMOV, "segReg,reg/mem32", "8E/r", {optO32}, {cpu386});
		AddInstruction(opMOV, "segReg,reg/mem64", "8E/r", {}, {cpuAMD64});
		AddInstruction(opMOV, "AL,moffset8", "A0+o", {}, {cpu8086});
		AddInstruction(opMOV, "AX,moffset16", "A1+o", {optO16}, {cpu8086});
		AddInstruction(opMOV, "EAX,moffset32", "A1+o", {optO32}, {cpu386});
		AddInstruction(opMOV, "RAX,moffset64", "A1+o", {}, {cpuAMD64});
		AddInstruction(opMOV, "moffset8,AL", "A2+o", {}, {cpu8086});
		AddInstruction(opMOV, "moffset16,AX", "A3+o", {optO16}, {cpu8086});
		AddInstruction(opMOV, "moffset32,EAX", "A3+o", {optO32}, {cpu386});
		AddInstruction(opMOV, "moffset64,RAX", "A3+o", {}, {cpuAMD64});
		AddInstruction(opMOV, "reg/mem8,imm8", "C6/0ib", {}, {cpu8086});
		AddInstruction(opMOV, "reg/mem16,imm16", "C7/0iw", {optO16}, {cpu8086});
		AddInstruction(opMOV, "reg/mem32,imm32", "C7/0id", {optO32}, {cpu386});
		AddInstruction(opMOV, "reg/mem64,simm32", "C7/0id", {}, {cpuAMD64});
		AddInstruction(opMOVAPD, "xmm1,xmm2/mem128", "0F28/r", {optPOP}, {cpuSSE2});
		AddInstruction(opMOVAPD, "xmm1/mem128,xmm2", "0F29/r", {optPOP}, {cpuSSE2});
		AddInstruction(opMOVAPS, "xmm1,xmm2/mem128", "0F28/r", {}, {cpuSSE});
		AddInstruction(opMOVAPS, "xmm1/mem128,xmm2", "0F29/r", {}, {cpuSSE});
		AddInstruction(opMOVD, "xmm,reg/mem32", "0F6E/r", {optPOP}, {cpuSSE2});
		AddInstruction(opMOVD, "xmm,reg/mem64", "0F6E/r", {optPOP}, {cpuAMD64,cpuSSE2});
		AddInstruction(opMOVD, "reg/mem32,xmm", "0F7E/r", {optPOP}, {cpuSSE2});
		AddInstruction(opMOVD, "reg/mem64,xmm", "0F7E/r", {optPOP}, {cpuAMD64,cpuSSE2});
		AddInstruction(opMOVD, "mmx,reg/mem32", "0F6E/r", {}, {cpuMMX});
		AddInstruction(opMOVD, "mmx,reg/mem64", "0F6E/r", {}, {cpuAMD64,cpuMMX});
		AddInstruction(opMOVD, "reg/mem32,mmx", "0F7E/r", {}, {cpuMMX});
		AddInstruction(opMOVD, "reg/mem64,mmx", "0F7E/r", {}, {cpuAMD64,cpuMMX});
		AddInstruction(opMOVDDUP, "xmm1,xmm2/mem64", "F20F12/r", {}, {cpuSSE3});
		AddInstructionV(opVMOVDDUP,"xmm1,xmm2/mem64","C4 RXB.00001 X.1111.0.11 12 /r");
		AddInstructionV(opVMOVDDUP,"ymm1,ymm2/mem256","C4 RXB.00001 X.1111.1.11 12 /r");
		AddInstruction(opMOVDQ2Q, "mmx,xmm", "F20FD6/r", {}, {cpuSSE2});
		AddInstruction(opMOVDQ2Q, "mmx,xmm", "F20FD6/r", {}, {cpuSSE2});
		AddInstruction(opMOVDQA, "xmm1,xmm2/mem128", "0F6F/r", {optPOP}, {cpuSSE2});
		AddInstruction(opMOVDQA, "xmm1/mem128,xmm2", "0F7F/r", {optPOP}, {cpuSSE2});
		AddInstruction(opMOVDQU, "xmm1,xmm2/mem128", "F30F6F/r", {}, {cpuSSE2});
		AddInstruction(opMOVDQU, "xmm1/mem128,xmm2", "F30F7F/r", {}, {cpuSSE2});
		AddInstruction(opMOVHLPS, "xmm1,xmm2", "0F12/r", {}, {cpuSSE});
		AddInstruction(opMOVHPD, "xmm,mem64", "0F16/r", {optPOP}, {cpuSSE2});
		AddInstruction(opMOVHPD, "mem64,xmm", "0F17/r", {optPOP}, {cpuSSE2});
		AddInstruction(opMOVHPS, "xmm,mem64", "0F16/r", {}, {cpuSSE});
		AddInstruction(opMOVHPS, "mem64,xmm", "0F17/r", {}, {cpuSSE});
		AddInstruction(opMOVLHPS, "xmm1,xmm2", "0F16/r", {}, {cpuSSE});
		AddInstruction(opMOVLPD, "xmm,mem64", "0F12/r", {optPOP}, {cpuSSE2});
		AddInstruction(opMOVLPD, "mem64,xmm", "0F13/r", {optPOP}, {cpuSSE2});
		AddInstruction(opMOVLPS, "xmm,mem64", "0F12/r", {}, {cpuSSE});
		AddInstruction(opMOVLPS, "mem64,xmm", "0F13/r", {}, {cpuSSE});
		AddInstruction(opMOVMSKPD, "reg32,xmm", "0F50/r", {optPOP}, {cpuSSE2});
		AddInstruction(opMOVMSKPS, "reg32,xmm", "0F50/r", {}, {cpuSSE});
		AddInstruction(opMOVMSKPS, "reg32,xmm", "0F50/r", {}, {cpuSSE});
		AddInstruction(opMOVNTDQ, "mem128,xmm", "0FE7/r", {optPOP}, {cpuSSE2});
		AddInstruction(opMOVNTI, "mem32,reg32", "0FC3/r", {}, {cpuSSE2});
		AddInstruction(opMOVNTI, "mem64,reg64", "0FC3/r", {}, {cpuAMD64,cpuSSE2});
		AddInstruction(opMOVNTPD, "mem128,xmm", "0F2B/r", {}, {cpuSSE2});
		AddInstruction(opMOVNTPS, "mem128,xmm", "0F2B/r", {}, {cpuSSE});
		AddInstruction(opMOVNTQ, "mem64,mmx", "0FE7/r", {}, {cpuMMX});
		AddInstruction(opMOVQ, "xmm1,xmm2/mem64", "F30F7E/r", {}, {cpuSSE2});
		AddInstruction(opMOVQ, "xmm1/mem64,xmm2", "0FD6/r", {optPOP}, {cpuSSE2});
		AddInstruction(opMOVQ, "mmx1,mmx2/mem64", "0F6F/r", {}, {cpuMMX});
		AddInstruction(opMOVQ, "mmx1/mem64,mmx2", "0F7F/r", {}, {cpuMMX});
		AddInstruction(opMOVQ2DQ, "xmm,mmx", "F30FD6/r", {}, {cpuSSE2});
		AddInstruction(opMOVQ2DQ, "xmm,mmx", "F30FD6/r", {}, {cpuSSE2});
		AddInstruction(opMOVS, "mem8,mem8", "A4", {}, {cpu8086});
		AddInstruction(opMOVS, "mem16,mem16", "A5", {optO16}, {cpu8086});
		AddInstruction(opMOVS, "mem32,mem32", "A5", {optO32}, {cpu386});
		AddInstruction(opMOVS, "mem64,mem64", "A5", {}, {cpuAMD64});
		AddInstruction(opMOVSB, "", "A4", {}, {cpu8086});
		AddInstruction(opMOVSD, "", "A5", {optO32}, {cpu386});
		AddInstruction(opMOVSD, "xmm1,xmm2/mem64", "F20F10/r", {}, {cpuSSE2});
		AddInstruction(opMOVSD, "xmm1/mem64,xmm2", "F20F11/r", {}, {cpuSSE2});
		AddInstruction(opMOVSHDUP, "xmm1,xmm2/mem128", "F30F16/r", {}, {cpuSSE3});
		AddInstruction(opMOVSLDUP, "xmm1,xmm2/mem128", "F30F12/r", {}, {cpuSSE3});
		AddInstruction(opMOVSQ, "", "A5", {}, {cpuAMD64});
		AddInstruction(opMOVSS, "xmm1,xmm2/mem32", "F30F10/r", {}, {cpuSSE});
		AddInstruction(opMOVSS, "xmm1/mem32,xmm2", "F30F11/r", {}, {cpuSSE});
		AddInstruction(opMOVSW, "", "A5", {optO16}, {cpu8086});
		AddInstruction(opMOVSX, "reg16,reg/mem8", "0FBE/r", {optO16}, {cpu386});
		AddInstruction(opMOVSX, "reg32,reg/mem8", "0FBE/r", {optO32}, {cpu386});
		AddInstruction(opMOVSX, "reg64,reg/mem8", "0FBE/r", {}, {cpuAMD64});
		AddInstruction(opMOVSX, "reg32,reg/mem16", "0FBF/r", {optO32}, {cpu386});
		AddInstruction(opMOVSX, "reg64,reg/mem16", "0FBF/r", {}, {cpuAMD64});
		AddInstruction(opMOVSXD, "reg64,reg/mem32", "63/r", {}, {cpuAMD64});
		AddInstruction(opMOVUPD, "xmm1,xmm2/mem128", "0F10/r", {optPOP}, {cpuSSE2});
		AddInstruction(opMOVUPD, "xmm1/mem128,xmm2", "0F11/r", {optPOP}, {cpuSSE2});
		AddInstruction(opMOVUPS, "xmm1,xmm2/mem128", "0F10/r", {}, {cpuSSE});
		AddInstruction(opMOVUPS, "xmm1/mem128,xmm2", "0F11/r", {}, {cpuSSE});
		AddInstruction(opMOVZX, "reg16,reg/mem8", "0FB6/r", {optO16}, {cpu386});
		AddInstruction(opMOVZX, "reg32,reg/mem8", "0FB6/r", {optO32}, {cpu386});
		AddInstruction(opMOVZX, "reg64,reg/mem8", "0FB6/r", {}, {cpuAMD64});
		AddInstruction(opMOVZX, "reg32,reg/mem16", "0FB7/r", {optO32}, {cpu386});
		AddInstruction(opMOVZX, "reg64,reg/mem16", "0FB7/r", {}, {cpuAMD64});
		AddInstruction(opMUL, "reg/mem8", "F6/4", {}, {cpu8086});
		AddInstruction(opMUL, "reg/mem16", "F7/4", {optO16}, {cpu8086});
		AddInstruction(opMUL, "reg/mem32", "F7/4", {optO32}, {cpu386});
		AddInstruction(opMUL, "reg/mem64", "F7/4", {}, {cpuAMD64});
		AddInstruction(opMUL, "AL,reg/mem8", "F6/4", {}, {cpu8086});
		AddInstruction(opMUL, "AX,reg/mem16", "F7/4", {optO16}, {cpu8086});
		AddInstruction(opMUL, "EAX,reg/mem32", "F7/4", {optO32}, {cpu386});
		AddInstruction(opMUL, "RAX,reg/mem64", "F7/4", {}, {cpuAMD64});
		AddInstruction(opMULPD, "xmm1,xmm2/mem128", "0F59/r", {optPOP}, {cpuSSE2});
		AddInstruction(opMULPS, "xmm1,xmm2/mem128", "0F59/r", {}, {cpuSSE});
		AddInstruction(opMULSD, "xmm1,xmm2/mem64", "F20F59/r", {}, {cpuSSE2});
		AddInstruction(opMULSS, "xmm1,xmm2/mem32", "F30F59/r", {}, {cpuSSE});
		AddInstruction(opNEG, "reg/mem8", "F6/3", {}, {cpu8086});
		AddInstruction(opNEG, "reg/mem16", "F7/3", {optO16}, {cpu8086});
		AddInstruction(opNEG, "reg/mem32", "F7/3", {optO32}, {cpu386});
		AddInstruction(opNEG, "reg/mem64", "F7/3", {}, {cpuAMD64});
		AddInstruction(opNOP, "", "90", {}, {cpu8086});
		AddInstruction(opNOT, "reg/mem8", "F6/2", {}, {cpu8086});
		AddInstruction(opNOT, "reg/mem16", "F7/2", {optO16}, {cpu8086});
		AddInstruction(opNOT, "reg/mem32", "F7/2", {optO32}, {cpu386});
		AddInstruction(opNOT, "reg/mem64", "F7/2", {}, {cpuAMD64});
		AddInstruction(opOR, "reg/mem8,reg8", "08/r", {}, {cpu8086});
		AddInstruction(opOR, "reg/mem16,reg16", "09/r", {optO16}, {cpu8086});
		AddInstruction(opOR, "reg/mem32,reg32", "09/r", {optO32}, {cpu386});
		AddInstruction(opOR, "reg/mem64,reg64", "09/r", {}, {cpuAMD64});
		AddInstruction(opOR, "reg8,reg/mem8", "0A/r", {}, {cpu8086});
		AddInstruction(opOR, "reg16,reg/mem16", "0B/r", {optO16}, {cpu8086});
		AddInstruction(opOR, "reg32,reg/mem32", "0B/r", {optO32}, {cpu386});
		AddInstruction(opOR, "reg64,reg/mem64", "0B/r", {}, {cpuAMD64});
		AddInstruction(opOR, "AL,imm8", "0Cib", {}, {cpu8086});
		AddInstruction(opOR, "AX,imm16", "0Diw", {optO16}, {cpu8086});
		AddInstruction(opOR, "EAX,imm32", "0Did", {optO32}, {cpu386});
		AddInstruction(opOR, "RAX,simm32", "0Did", {}, {cpuAMD64});
		AddInstruction(opOR, "reg/mem8,imm8", "80/1ib", {}, {cpu8086});
		AddInstruction(opOR, "reg/mem16,imm16", "81/1iw", {optO16}, {cpu8086});
		AddInstruction(opOR, "reg/mem32,imm32", "81/1id", {optO32}, {cpu386});
		AddInstruction(opOR, "reg/mem64,simm32", "81/1id", {}, {cpuAMD64});
		AddInstruction(opOR, "reg/mem16,simm8", "83/1ib", {optO16}, {cpu8086});
		AddInstruction(opOR, "reg/mem32,simm8", "83/1ib", {optO32}, {cpu386});
		AddInstruction(opOR, "reg/mem64,simm8", "83/1ib", {}, {cpuAMD64});
		AddInstruction(opORPD, "xmm1,xmm2/mem128", "0F56/r", {optPOP}, {cpuSSE2});
		AddInstruction(opORPS, "xmm1,xmm2/mem128", "0F56/r", {}, {cpuSSE});
		AddInstruction(opOUT, "uimm8,AL", "E6ib", {}, {cpu8086});
		AddInstruction(opOUT, "uimm8,AX", "E7ib", {optO16}, {cpu8086});
		AddInstruction(opOUT, "uimm8,EAX", "E7ib", {optO32}, {cpu386});
		AddInstruction(opOUT, "DX,AL", "EE", {}, {cpu8086});
		AddInstruction(opOUT, "DX,AX", "EF", {optO16}, {cpu8086});
		AddInstruction(opOUT, "DX,EAX", "EF", {optO32}, {cpu386});
		AddInstruction(opOUTS, "DX,mem8", "6E", {}, {cpu186});
		AddInstruction(opOUTS, "DX,mem16", "6F", {optO16}, {cpu186});
		AddInstruction(opOUTS, "DX,mem32", "6F", {optO32}, {cpu386});
		AddInstruction(opOUTSB, "", "6E", {}, {cpu186});
		AddInstruction(opOUTSD, "", "6F", {optO32}, {cpu386});
		AddInstruction(opOUTSW, "", "6F", {optO16}, {cpu186});
		AddInstruction(opPACKSSDW, "xmm1,xmm2/mem128", "0F6B/r", {optPOP}, {cpuSSE2});
		AddInstruction(opPACKSSDW, "mmx1,mmx2/mem64", "0F6B/r", {}, {cpuMMX});
		AddInstruction(opPACKSSWB, "xmm1,xmm2/mem128", "0F63/r", {optPOP}, {cpuSSE2});
		AddInstruction(opPACKSSWB, "mmx1,mmx2/mem64", "0F63/r", {}, {cpuMMX});
		AddInstruction(opPACKUSWB, "xmm1,xmm2/mem128", "0F67/r", {optPOP}, {cpuSSE2});
		AddInstruction(opPACKUSWB, "mmx1,mmx2/mem64", "0F67/r", {}, {cpuMMX});
		AddInstruction(opPADDB, "xmm1,xmm2/mem128", "0FFC/r", {optPOP}, {cpuSSE2});
		AddInstruction(opPADDB, "mmx1,mmx2/mem64", "0FFC/r", {}, {cpuMMX});
		AddInstruction(opPADDD, "xmm1,xmm2/mem128", "0FFE/r", {optPOP}, {cpuSSE2});
		AddInstruction(opPADDD, "mmx1,mmx2/mem64", "0FFE/r", {}, {cpuMMX});
		AddInstruction(opPADDQ, "xmm1,xmm2/mem128", "0FD4/r", {optPOP}, {cpuSSE2});
		AddInstruction(opPADDQ, "mmx1,mmx2/mem64", "0FD4/r", {}, {cpuMMX});
		AddInstruction(opPADDSB, "xmm1,xmm2/mem128", "0FEC/r", {optPOP}, {cpuSSE2});
		AddInstruction(opPADDSB, "mmx1,mmx2/mem64", "0FEC/r", {}, {cpuMMX});
		AddInstruction(opPADDSW, "xmm1,xmm2/mem128", "0FED/r", {optPOP}, {cpuSSE2});
		AddInstruction(opPADDSW, "mmx1,mmx2/mem64", "0FED/r", {}, {cpuMMX});
		AddInstruction(opPADDUSB, "xmm1,xmm2/mem128", "0FDC/r", {optPOP}, {cpuSSE2});
		AddInstruction(opPADDUSB, "mmx1,mmx2/mem64", "0FDC/r", {}, {cpuMMX});
		AddInstruction(opPADDUSW, "xmm1,xmm2/mem128", "0FDD/r", {optPOP}, {cpuSSE2});
		AddInstruction(opPADDUSW, "mmx1,mmx2/mem64", "0FDD/r", {}, {cpuMMX});
		AddInstruction(opPADDW, "xmm1,xmm2/mem128", "0FFD/r", {optPOP}, {cpuSSE2});
		AddInstruction(opPADDW, "mmx1,mmx2/mem64", "0FFD/r", {}, {cpuMMX});
		AddInstruction(opPAND, "xmm1,xmm2/mem128", "0FDB/r", {optPOP}, {cpuSSE2});
		AddInstruction(opPAND, "mmx1,mmx2/mem64", "0FDB/r", {}, {cpuMMX});
		AddInstruction(opPANDN, "xmm1,xmm2/mem128", "0FDF/r", {optPOP}, {cpuSSE2});
		AddInstruction(opPANDN, "mmx1,mmx2/mem64", "0FDF/r", {}, {cpuMMX});
		AddInstruction(opPAUSE, "", "F390", {}, {cpuSSE2});
		AddInstruction(opPAVGB, "xmm1,xmm2/mem128", "0FE0/r", {optPOP}, {cpuSSE2});
		AddInstruction(opPAVGB, "mmx1,mmx2/mem64", "0FE0/r", {}, {cpuMMX});
		AddInstruction(opPAVGUSB, "mmx1,mmx2/mem64", "0F0F/rBF", {}, {cpu3DNow});
		AddInstruction(opPAVGW, "xmm1,xmm2/mem128", "0FE3/r", {optPOP}, {cpuSSE2});
		AddInstruction(opPAVGW, "mmx1,mmx2/mem64", "0FE3/r", {}, {cpuMMX});
		AddInstruction(opPCMPEQB, "xmm1,xmm2/mem128", "0F74/r", {optPOP}, {cpuSSE2});
		AddInstruction(opPCMPEQB, "mmx1,mmx2/mem64", "0F74/r", {}, {cpuMMX});
		AddInstruction(opPCMPEQD, "xmm1,xmm2/mem128", "0F76/r", {optPOP}, {cpuSSE2});
		AddInstruction(opPCMPEQD, "mmx1,mmx2/mem64", "0F76/r", {}, {cpuMMX});
		AddInstruction(opPCMPEQW, "xmm1,xmm2/mem128", "0F75/r", {optPOP}, {cpuSSE2});
		AddInstruction(opPCMPEQW, "mmx1,mmx2/mem64", "0F75/r", {}, {cpuMMX});
		AddInstruction(opPCMPGTB, "xmm1,xmm2/mem128", "0F64/r", {optPOP}, {cpuSSE2});
		AddInstruction(opPCMPGTB, "mmx1,mmx2/mem64", "0F64/r", {}, {cpuMMX});
		AddInstruction(opPCMPGTD, "xmm1,xmm2/mem128", "0F66/r", {optPOP}, {cpuSSE2});
		AddInstruction(opPCMPGTD, "mmx1,mmx2/mem64", "0F66/r", {}, {cpuMMX});
		AddInstruction(opPCMPGTW, "xmm1,xmm2/mem128", "0F65/r", {optPOP}, {cpuSSE2});
		AddInstruction(opPCMPGTW, "mmx1,mmx2/mem64", "0F65/r", {}, {cpuMMX});
		AddInstruction(opPEXTRW, "reg32,xmm,uimm8", "0FC5/rib", {optPOP}, {cpuSSE2});
		AddInstruction(opPEXTRW, "reg32,mmx,uimm8", "0FC5/rib", {}, {cpuMMX});
		AddInstruction(opPF2ID, "mmx1,mmx2/mem64", "0F0F/r1D", {}, {cpu3DNow});
		AddInstruction(opPF2IW, "mmx1,mmx2/mem64", "0F0F/r1C", {}, {cpu3DNow});
		AddInstruction(opPFACC, "mmx1,mmx2/mem64", "0F0F/rAE", {}, {cpu3DNow});
		AddInstruction(opPFADD, "mmx1,mmx2/mem64", "0F0F/r9E", {}, {cpu3DNow});
		AddInstruction(opPFCMPEQ, "mmx1,mmx2/mem64", "0F0F/rB0", {}, {cpu3DNow});
		AddInstruction(opPFCMPGE, "mmx1,mmx2/mem64", "0F0F/r90", {}, {cpu3DNow});
		AddInstruction(opPFCMPGT, "mmx1,mmx2/mem64", "0F0F/rA0", {}, {cpu3DNow});
		AddInstruction(opPFMAX, "mmx1,mmx2/mem64", "0F0F/rA4", {}, {cpu3DNow});
		AddInstruction(opPFMIN, "mmx1,mmx2/mem64", "0F0F/r94", {}, {cpu3DNow});
		AddInstruction(opPFMUL, "mmx1,mmx2/mem64", "0F0F/rB4", {}, {cpu3DNow});
		AddInstruction(opPFNACC, "mmx1,mmx2/mem64", "0F0F/r8A", {}, {cpu3DNow});
		AddInstruction(opPFPNACC, "mmx1,mmx2/mem64", "0F0F/r8E", {}, {cpu3DNow});
		AddInstruction(opPFRCP, "mmx1,mmx2/mem64", "0F0F/r96", {}, {cpu3DNow});
		AddInstruction(opPFRCPIT1, "mmx1,mmx2/mem64", "0F0F/rA6", {}, {cpu3DNow});
		AddInstruction(opPFRCPIT2, "mmx1,mmx2/mem64", "0F0F/rB6", {}, {cpu3DNow});
		AddInstruction(opPFRSQIT1, "mmx1,mmx2/mem64", "0F0F/rA7", {}, {cpu3DNow});
		AddInstruction(opPFRSQRT, "mmx1,mmx2/mem64", "0F0F/r97", {}, {cpu3DNow});
		AddInstruction(opPFSUB, "mmx1,mmx2/mem64", "0F0F/r9A", {}, {cpu3DNow});
		AddInstruction(opPFSUBR, "mmx1,mmx2/mem64", "0F0F/rAA", {}, {cpu3DNow});
		AddInstruction(opPI2FD, "mmx1,mmx2/mem64", "0F0F/r0D", {}, {cpu3DNow});
		AddInstruction(opPI2FW, "mmx1,mmx2/mem64", "0F0F/r0C", {}, {cpu3DNow});
		AddInstruction(opPINSRW, "xmm,reg/mem16,uimm8", "0FC4/rib", {optPOP}, {cpuSSE2});
		AddInstruction(opPINSRW, "xmm,reg/mem32,uimm8", "0FC4/rib", {optPOP}, {cpuSSE2});
		AddInstruction(opPINSRW, "mmx,reg/mem16,uimm8", "0FC4/rib", {}, {cpuMMX});
		AddInstruction(opPINSRW, "mmx,reg/mem32,uimm8", "0FC4/rib", {}, {cpuMMX});
		AddInstruction(opPMADDWD, "xmm1,xmm2/mem128", "0FF5/r", {optPOP}, {cpuSSE2});
		AddInstruction(opPMADDWD, "mmx1,mmx2/mem64", "0FF5/r", {}, {cpuMMX});
		AddInstruction(opPMAXSW, "xmm1,xmm2/mem128", "0FEE/r", {optPOP}, {cpuSSE2});
		AddInstruction(opPMAXSW, "mmx1,mmx2/mem64", "0FEE/r", {}, {cpuMMX});
		AddInstruction(opPMAXUB, "xmm1,xmm2/mem128", "0FDE/r", {optPOP}, {cpuSSE2});
		AddInstruction(opPMAXUB, "mmx1,mmx2/mem64", "0FDE/r", {}, {cpuMMX});
		AddInstruction(opPMINSW, "xmm1,xmm2/mem128", "0FEA/r", {optPOP}, {cpuSSE2});
		AddInstruction(opPMINSW, "mmx1,mmx2/mem64", "0FEA/r", {}, {cpuMMX});
		AddInstruction(opPMINUB, "xmm1,xmm2/mem128", "0FDA/r", {optPOP}, {cpuSSE2});
		AddInstruction(opPMINUB, "mmx1,mmx2/mem64", "0FDA/r", {}, {cpuMMX});
		AddInstruction(opPMOVMSKB, "reg32,xmm", "0FD7/r", {optPOP}, {cpuSSE2});
		AddInstruction(opPMOVMSKB, "reg32,mmx", "0FD7/r", {}, {cpuMMX});
		AddInstruction(opPMULHRW, "mmx1,mmx2/mem64", "0F0F/rB7", {}, {cpu3DNow});
		AddInstruction(opPMULHUW, "xmm1,xmm2/mem128", "0FE4/r", {optPOP}, {cpuSSE2});
		AddInstruction(opPMULHUW, "mmx1,mmx2/mem64", "0FE4/r", {}, {cpuMMX});
		AddInstruction(opPMULHW, "xmm1,xmm2/mem128", "0FE5/r", {optPOP}, {cpuSSE2});
		AddInstruction(opPMULHW, "mmx1,mmx2/mem64", "0FE5/r", {}, {cpuMMX});
		AddInstruction(opPMULLW, "xmm1,xmm2/mem128", "0FD5/r", {optPOP}, {cpuSSE2});
		AddInstruction(opPMULLW, "mmx1,mmx2/mem64", "0FD5/r", {}, {cpuMMX});
		AddInstruction(opPMULUDQ, "xmm1,xmm2/mem128", "0FF4/r", {optPOP}, {cpuSSE2});
		AddInstruction(opPMULUDQ, "mmx1,mmx2/mem64", "0FF4/r", {}, {cpuSSE2});
		AddInstruction(opPOP, "reg16", "58rw", {optO16}, {cpu8086});
		AddInstruction(opPOP, "reg32", "58rd", {optO32}, {cpu386});
		AddInstruction(opPOP, "reg64", "58rq", {}, {cpuAMD64});
		AddInstruction(opPOP, "reg/mem16", "8F/0", {optO16}, {cpu8086});
		AddInstruction(opPOP, "reg/mem32", "8F/0", {optO32}, {cpu386});
		AddInstruction(opPOP, "reg/mem64", "8F/0", {}, {cpuAMD64});
		AddInstruction(opPOP, "DS", "1F", {optNot64}, {cpu8086});
		AddInstruction(opPOP, "ES", "07", {optNot64}, {cpu8086});
		AddInstruction(opPOP, "SS", "17", {optNot64}, {cpu8086});
		AddInstruction(opPOP, "FS", "0FA1", {}, {cpu386});
		AddInstruction(opPOP, "GS", "0FA9", {}, {cpu386});
		AddInstruction(opPOPA, "", "61", {optNot64}, {cpu186});
		AddInstruction(opPOPAD, "", "61", {optO32,optNot64}, {cpu386});
		AddInstruction(opPOPAW, "", "61", {optO16,optNot64}, {cpu186});
		AddInstruction(opPOPF, "", "9D", {}, {cpu8086});
		AddInstruction(opPOPFD, "", "9D", {optO32}, {cpu386});
		AddInstruction(opPOPFQ, "", "9D", {}, {cpuAMD64});
		AddInstruction(opPOR, "xmm1,xmm2/mem128", "0FEB/r", {optPOP}, {cpuSSE2});
		AddInstruction(opPOR, "mmx1,mmx2/mem64", "0FEB/r", {}, {cpuMMX});
		AddInstruction(opPREFETCH, "mem8", "0F0D/0", {}, {cpu3DNow});
		AddInstruction(opPREFETCHNTA, "mem8", "0F18/0", {}, {cpuSSE,cpuMMX});
		AddInstruction(opPREFETCHT0, "mem8", "0F18/1", {}, {cpuSSE,cpuMMX});
		AddInstruction(opPREFETCHT1, "mem8", "0F18/2", {}, {cpuSSE,cpuMMX});
		AddInstruction(opPREFETCHT2, "mem8", "0F18/3", {}, {cpuSSE,cpuMMX});
		AddInstruction(opPREFETCHW, "mem8", "0F0D/1", {}, {cpu3DNow});
		AddInstruction(opPSADBW, "xmm1,xmm2/mem128", "0FF6/r", {optPOP}, {cpuSSE2});
		AddInstruction(opPSADBW, "mmx1,mmx2/mem64", "0FF6/r", {}, {cpuMMX});
		AddInstruction(opPSHUFD, "xmm1,xmm2/mem128,uimm8", "0F70/rib", {optPOP}, {cpuSSE2});
		AddInstruction(opPSHUFHW, "xmm1,xmm2/mem128,uimm8", "F30F70/rib", {}, {cpuSSE2});
		AddInstruction(opPSHUFLW, "xmm1,xmm2/mem128,uimm8", "F20F70/rib", {}, {cpuSSE2});
		AddInstruction(opPSHUFW, "mmx1,mmx2/mem64,imm8", "0F70/rib", {}, {cpuSSE2});
		AddInstruction(opPSLLD, "xmm1,xmm2/mem128", "0FF2/r", {optPOP}, {cpuSSE2});
		AddInstruction(opPSLLD, "xmm,uimm8", "0F72/6ib", {optPOP}, {cpuSSE2});
		AddInstruction(opPSLLD, "mmx1,mmx2/mem64", "0FF2/r", {}, {cpuMMX});
		AddInstruction(opPSLLD, "mmx,imm8", "0F72/6ib", {}, {cpuMMX});
		AddInstruction(opPSLLDQ, "xmm,uimm8", "0F73/7ib", {optPOP}, {cpuSSE2});
		AddInstruction(opPSLLQ, "xmm1,xmm2/mem128", "0FF3/r", {optPOP}, {cpuSSE2});
		AddInstruction(opPSLLQ, "xmm,uimm8", "0F73/6ib", {optPOP}, {cpuSSE2});
		AddInstruction(opPSLLQ, "mmx1,mmx2/mem64", "0FF3/r", {}, {cpuMMX});
		AddInstruction(opPSLLQ, "mmx,imm8", "0F73/6ib", {}, {cpuMMX});
		AddInstruction(opPSLLW, "xmm1,xmm2/mem128", "0FF1/r", {optPOP}, {cpuSSE2});
		AddInstruction(opPSLLW, "xmm,uimm8", "0F71/6ib", {optPOP}, {cpuSSE2});
		AddInstruction(opPSLLW, "mmx1,mmx2/mem64", "0FF1/r", {}, {cpuMMX});
		AddInstruction(opPSLLW, "mmx,imm8", "0F71/6ib", {}, {cpuMMX});
		AddInstruction(opPSRAD, "xmm1,xmm2/mem128", "0FE2/r", {optPOP}, {cpuSSE2});
		AddInstruction(opPSRAD, "xmm,uimm8", "0F72/4ib", {optPOP}, {cpuSSE2});
		AddInstruction(opPSRAD, "mmx1,mmx2/mem64", "0FE2/r", {}, {cpuMMX});
		AddInstruction(opPSRAD, "mmx,imm8", "0F72/4ib", {}, {cpuMMX});
		AddInstruction(opPSRAW, "xmm1,xmm2/mem128", "0FE1/r", {optPOP}, {cpuSSE2});
		AddInstruction(opPSRAW, "xmm,uimm8", "0F71/4ib", {optPOP}, {cpuSSE2});
		AddInstruction(opPSRAW, "mmx1,mmx2/mem64", "0FE1/r", {}, {cpuMMX});
		AddInstruction(opPSRAW, "mmx,imm8", "0F71/4ib", {}, {cpuMMX});
		AddInstruction(opPSRLD, "xmm1,xmm2/mem128", "0FD2/r", {optPOP}, {cpuSSE2});
		AddInstruction(opPSRLD, "xmm,uimm8", "0F72/2ib", {optPOP}, {cpuSSE2});
		AddInstruction(opPSRLD, "mmx1,mmx2/mem64", "0FD2/r", {}, {cpuMMX});
		AddInstruction(opPSRLD, "mmx,imm8", "0F72/2ib", {}, {cpuMMX});
		AddInstruction(opPSRLDQ, "xmm,uimm8", "0F73/3ib", {optPOP}, {cpuSSE2});
		AddInstruction(opPSRLQ, "xmm1,xmm2/mem128", "0FD3/r", {optPOP}, {cpuSSE2});
		AddInstruction(opPSRLQ, "xmm,uimm8", "0F73/2ib", {optPOP}, {cpuSSE2});
		AddInstruction(opPSRLQ, "mmx1,mmx2/mem64", "0FD3/r", {}, {cpuMMX});
		AddInstruction(opPSRLQ, "mmx,imm8", "0F73/2ib", {}, {cpuMMX});
		AddInstruction(opPSRLW, "xmm1,xmm2/mem128", "0FD1/r", {optPOP}, {cpuSSE2});
		AddInstruction(opPSRLW, "xmm,uimm8", "0F71/2ib", {optPOP}, {cpuSSE2});
		AddInstruction(opPSRLW, "mmx1,mmx2/mem64", "0FD1/r", {}, {cpuMMX});
		AddInstruction(opPSRLW, "mmx,imm8", "0F71/2ib", {}, {cpuMMX});
		AddInstruction(opPSUBB, "xmm1,xmm2/mem128", "0FF8/r", {optPOP}, {cpuSSE2});
		AddInstruction(opPSUBB, "mmx1,mmx2/mem64", "0FF8/r", {}, {cpuMMX});
		AddInstruction(opPSUBD, "xmm1,xmm2/mem128", "0FFA/r", {optPOP}, {cpuSSE2});
		AddInstruction(opPSUBD, "mmx1,mmx2/mem64", "0FFA/r", {}, {cpuMMX});
		AddInstruction(opPSUBQ, "xmm1,xmm2/mem128", "0FFB/r", {optPOP}, {cpuSSE2});
		AddInstruction(opPSUBQ, "mmx1,mmx2/mem64", "0FFB/r", {}, {cpuMMX});
		AddInstruction(opPSUBSB, "xmm1,xmm2/mem128", "0FE8/r", {optPOP}, {cpuSSE2});
		AddInstruction(opPSUBSB, "mmx1,mmx2/mem64", "0FE8/r", {}, {cpuMMX});
		AddInstruction(opPSUBSW, "xmm1,xmm2/mem128", "0FE9/r", {optPOP}, {cpuSSE2});
		AddInstruction(opPSUBSW, "mmx1,mmx2/mem64", "0FE9/r", {}, {cpuMMX});
		AddInstruction(opPSUBUSB, "xmm1,xmm2/mem128", "0FD8/r", {optPOP}, {cpuSSE2});
		AddInstruction(opPSUBUSB, "mmx1,mmx2/mem64", "0FD8/r", {}, {cpuMMX});
		AddInstruction(opPSUBUSW, "xmm1,xmm2/mem128", "0FD9/r", {optPOP}, {cpuSSE2});
		AddInstruction(opPSUBUSW, "mmx1,mmx2/mem64", "0FD9/r", {}, {cpuMMX});
		AddInstruction(opPSUBW, "xmm1,xmm2/mem128", "0FF9/r", {optPOP}, {cpuSSE2});
		AddInstruction(opPSUBW, "mmx1,mmx2/mem64", "0FF9/r", {}, {cpuMMX});
		AddInstruction(opPSWAPD, "mmx1,mmx2/mem64", "0F0F/rBB", {}, {cpu3DNow});
		AddInstruction(opPUNPCKHBW, "xmm1,xmm2/mem128", "0F68/r", {optPOP}, {cpuSSE2});
		AddInstruction(opPUNPCKHBW, "mmx1,mmx2/mem64", "0F68/r", {}, {cpuMMX});
		AddInstruction(opPUNPCKHDQ, "xmm1,xmm2/mem128", "0F6A/r", {optPOP}, {cpuSSE2});
		AddInstruction(opPUNPCKHDQ, "mmx1,mmx2/mem64", "0F6A/r", {}, {cpuMMX});
		AddInstruction(opPUNPCKHQDQ, "xmm1,xmm2/mem128", "0F6D/r", {optPOP}, {cpuSSE2});
		AddInstruction(opPUNPCKHWD, "xmm1,xmm2/mem128", "0F69/r", {optPOP}, {cpuSSE2});
		AddInstruction(opPUNPCKHWD, "mmx1,mmx2/mem64", "0F69/r", {}, {cpuMMX});
		AddInstruction(opPUNPCKLBW, "xmm1,xmm2/mem128", "0F60/r", {optPOP}, {cpuSSE2});
		AddInstruction(opPUNPCKLBW, "mmx1,mmx2/mem32", "0F60/r", {}, {cpuMMX});
		AddInstruction(opPUNPCKLDQ, "xmm1,xmm2/mem128", "0F62/r", {optPOP}, {cpuSSE2});
		AddInstruction(opPUNPCKLDQ, "mmx1,mmx2/mem32", "0F62/r", {}, {cpuMMX});
		AddInstruction(opPUNPCKLQDQ, "xmm1,xmm2/mem128", "0F6C/r", {optPOP}, {cpuSSE2});
		AddInstruction(opPUNPCKLWD, "xmm1,xmm2/mem128", "0F61/r", {optPOP}, {cpuSSE2});
		AddInstruction(opPUNPCKLWD, "mmx1,mmx2/mem32", "0F61/r", {}, {cpuMMX});
		AddInstruction(opPUSH, "reg16", "50rw", {optO16}, {cpu8086});
		AddInstruction(opPUSH, "reg32", "50rd", {optO32}, {cpu386});
		AddInstruction(opPUSH, "reg64", "50rq", {}, {cpuAMD64});
		AddInstruction(opPUSH, "reg/mem16", "FF/6", {optO16}, {cpu8086});
		AddInstruction(opPUSH, "reg/mem32", "FF/6", {optO32}, {cpu386});
		AddInstruction(opPUSH, "reg/mem64", "FF/6", {}, {cpuAMD64});
		AddInstruction(opPUSH, "imm8", "6Aib", {}, {cpu186});
		AddInstruction(opPUSH, "imm16", "68iw", {}, {cpu186});
		AddInstruction(opPUSH, "imm32", "68id", {optNot64}, {cpu186});
		AddInstruction(opPUSH, "simm32", "68id", {}, {cpuAMD64});
		AddInstruction(opPUSH, "CS", "0E", {optNot64}, {cpu8086});
		AddInstruction(opPUSH, "SS", "16", {optNot64}, {cpu8086});
		AddInstruction(opPUSH, "DS", "1E", {optNot64}, {cpu8086});
		AddInstruction(opPUSH, "ES", "06", {optNot64}, {cpu8086});
		AddInstruction(opPUSH, "FS", "0FA0", {}, {cpu386});
		AddInstruction(opPUSH, "GS", "0FA8", {}, {cpu386});
		AddInstruction(opPUSHA, "", "60", {optNot64}, {cpu186});
		AddInstruction(opPUSHAD, "", "60", {optO32,optNot64}, {cpu386});
		AddInstruction(opPUSHF, "", "9C", {}, {cpu8086});
		AddInstruction(opPUSHFD, "", "9C", {optO32}, {cpu386});
		AddInstruction(opPUSHFQ, "", "9C", {}, {cpuAMD64});
		AddInstruction(opPXOR, "xmm1,xmm2/mem128", "0FEF/r", {optPOP}, {cpuSSE2});
		AddInstruction(opPXOR, "mmx1,mmx2/mem64", "0FEF/r", {}, {cpuMMX});
		AddInstruction(opRCL, "reg/mem8,1", "D0/2", {}, {cpu8086});
		AddInstruction(opRCL, "reg/mem8,CL", "D2/2", {}, {cpu8086});
		AddInstruction(opRCL, "reg/mem8,uimm8", "C0/2ib", {}, {cpu186});
		AddInstruction(opRCL, "reg/mem16,1", "D1/2", {optO16}, {cpu8086});
		AddInstruction(opRCL, "reg/mem16,CL", "D3/2", {optO16}, {cpu8086});
		AddInstruction(opRCL, "reg/mem16,uimm8", "C1/2ib", {optO16}, {cpu186});
		AddInstruction(opRCL, "reg/mem32,1", "D1/2", {optO32}, {cpu386});
		AddInstruction(opRCL, "reg/mem32,CL", "D3/2", {optO32}, {cpu386});
		AddInstruction(opRCL, "reg/mem32,uimm8", "C1/2ib", {optO32}, {cpu386});
		AddInstruction(opRCL, "reg/mem64,1", "D1/2", {}, {cpuAMD64});
		AddInstruction(opRCL, "reg/mem64,CL", "D3/2", {}, {cpuAMD64});
		AddInstruction(opRCL, "reg/mem64,uimm8", "C1/2ib", {}, {cpuAMD64});
		AddInstruction(opRCPPS, "xmm1,xmm2/mem128", "0F53/r", {}, {cpuSSE});
		AddInstruction(opRCPSS, "xmm1,xmm2/mem32", "F30F53/r", {}, {cpuSSE});
		AddInstruction(opRCR, "reg/mem8,1", "D0/3", {}, {cpu8086});
		AddInstruction(opRCR, "reg/mem8,CL", "D2/3", {}, {cpu8086});
		AddInstruction(opRCR, "reg/mem8,uimm8", "C0/3ib", {}, {cpu186});
		AddInstruction(opRCR, "reg/mem16,1", "D1/3", {optO16}, {cpu8086});
		AddInstruction(opRCR, "reg/mem16,CL", "D3/3", {optO16}, {cpu8086});
		AddInstruction(opRCR, "reg/mem16,uimm8", "C1/3ib", {optO16}, {cpu186});
		AddInstruction(opRCR, "reg/mem32,1", "D1/3", {optO32}, {cpu386});
		AddInstruction(opRCR, "reg/mem32,CL", "D3/3", {optO32}, {cpu386});
		AddInstruction(opRCR, "reg/mem32,uimm8", "C1/3ib", {optO32}, {cpu386});
		AddInstruction(opRCR, "reg/mem64,1", "D1/3", {}, {cpuAMD64});
		AddInstruction(opRCR, "reg/mem64,CL", "D3/3", {}, {cpuAMD64});
		AddInstruction(opRCR, "reg/mem64,uimm8", "C1/3ib", {}, {cpuAMD64});
		AddInstruction(opRDMSR, "", "0F32", {}, {cpuPentium,cpuPrivileged});
		AddInstruction(opRDPMC, "", "0F33", {}, {cpuP6});
		AddInstruction(opRDTSC, "", "0F31", {}, {cpuPentium});
		AddInstruction(opRDTSCP, "", "0F01F9", {}, {cpuPentium});
		AddInstruction(opRET, "", "C3", {}, {cpu8086});
		AddInstruction(opRET, "uimm16", "C2iw", {}, {cpu8086});
		AddInstruction(opRETF, "", "CB", {}, {cpu8086});
		AddInstruction(opRETF, "uimm16", "CAiw", {}, {cpu8086});
		AddInstruction(opROL, "reg/mem8,1", "D0/0", {}, {cpu8086});
		AddInstruction(opROL, "reg/mem8,CL", "D2/0", {}, {cpu8086});
		AddInstruction(opROL, "reg/mem8,uimm8", "C0/0ib", {}, {cpu186});
		AddInstruction(opROL, "reg/mem16,1", "D1/0", {optO16}, {cpu8086});
		AddInstruction(opROL, "reg/mem16,CL", "D3/0", {optO16}, {cpu8086});
		AddInstruction(opROL, "reg/mem16,uimm8", "C1/0ib", {optO16}, {cpu186});
		AddInstruction(opROL, "reg/mem32,1", "D1/0", {optO32}, {cpu386});
		AddInstruction(opROL, "reg/mem32,CL", "D3/0", {optO32}, {cpu386});
		AddInstruction(opROL, "reg/mem32,uimm8", "C1/0ib", {optO32}, {cpu386});
		AddInstruction(opROL, "reg/mem64,1", "D1/0", {}, {cpuAMD64});
		AddInstruction(opROL, "reg/mem64,CL", "D3/0", {}, {cpuAMD64});
		AddInstruction(opROL, "reg/mem64,uimm8", "C1/0ib", {}, {cpuAMD64});
		AddInstruction(opROR, "reg/mem8,1", "D0/1", {}, {cpu8086});
		AddInstruction(opROR, "reg/mem8,CL", "D2/1", {}, {cpu8086});
		AddInstruction(opROR, "reg/mem8,uimm8", "C0/1ib", {}, {cpu186});
		AddInstruction(opROR, "reg/mem16,1", "D1/1", {optO16}, {cpu8086});
		AddInstruction(opROR, "reg/mem16,CL", "D3/1", {optO16}, {cpu8086});
		AddInstruction(opROR, "reg/mem16,uimm8", "C1/1ib", {optO16}, {cpu186});
		AddInstruction(opROR, "reg/mem32,1", "D1/1", {optO32}, {cpu386});
		AddInstruction(opROR, "reg/mem32,CL", "D3/1", {optO32}, {cpu386});
		AddInstruction(opROR, "reg/mem32,uimm8", "C1/1ib", {optO32}, {cpu386});
		AddInstruction(opROR, "reg/mem64,1", "D1/1", {}, {cpuAMD64});
		AddInstruction(opROR, "reg/mem64,CL", "D3/1", {}, {cpuAMD64});
		AddInstruction(opROR, "reg/mem64,uimm8", "C1/1ib", {}, {cpuAMD64});
		AddInstruction(opRSM, "", "0FAA", {}, {});
		AddInstruction(opRSQRTPS, "xmm1,xmm2/mem128", "0F52/r", {}, {cpuSSE});
		AddInstruction(opRSQRTSS, "xmm1,xmm2/mem32", "F30F52/r", {}, {cpuSSE});
		AddInstruction(opSAHF, "", "9E", {}, {cpu8086});
		AddInstruction(opSAL, "reg/mem8,1", "D0/4", {}, {cpu8086});
		AddInstruction(opSAL, "reg/mem8,CL", "D2/4", {}, {cpu8086});
		AddInstruction(opSAL, "reg/mem8,uimm8", "C0/4ib", {}, {cpu186});
		AddInstruction(opSAL, "reg/mem16,1", "D1/4", {optO16}, {cpu8086});
		AddInstruction(opSAL, "reg/mem16,CL", "D3/4", {optO16}, {cpu8086});
		AddInstruction(opSAL, "reg/mem16,uimm8", "C1/4ib", {optO16}, {cpu186});
		AddInstruction(opSAL, "reg/mem32,1", "D1/4", {optO32}, {cpu386});
		AddInstruction(opSAL, "reg/mem32,CL", "D3/4", {optO32}, {cpu386});
		AddInstruction(opSAL, "reg/mem32,uimm8", "C1/4ib", {optO32}, {cpu386});
		AddInstruction(opSAL, "reg/mem64,1", "D1/4", {}, {cpuAMD64});
		AddInstruction(opSAL, "reg/mem64,CL", "D3/4", {}, {cpuAMD64});
		AddInstruction(opSAL, "reg/mem64,uimm8", "C1/4ib", {}, {cpuAMD64});
		AddInstruction(opSAR, "reg/mem8,1", "D0/7", {}, {cpu8086});
		AddInstruction(opSAR, "reg/mem8,CL", "D2/7", {}, {cpu8086});
		AddInstruction(opSAR, "reg/mem8,uimm8", "C0/7ib", {}, {cpu186});
		AddInstruction(opSAR, "reg/mem16,1", "D1/7", {optO16}, {cpu8086});
		AddInstruction(opSAR, "reg/mem16,CL", "D3/7", {optO16}, {cpu8086});
		AddInstruction(opSAR, "reg/mem16,uimm8", "C1/7ib", {optO16}, {cpu186});
		AddInstruction(opSAR, "reg/mem32,1", "D1/7", {optO32}, {cpu386});
		AddInstruction(opSAR, "reg/mem32,CL", "D3/7", {optO32}, {cpu386});
		AddInstruction(opSAR, "reg/mem32,uimm8", "C1/7ib", {optO32}, {cpu386});
		AddInstruction(opSAR, "reg/mem64,1", "D1/7", {}, {cpuAMD64});
		AddInstruction(opSAR, "reg/mem64,CL", "D3/7", {}, {cpuAMD64});
		AddInstruction(opSAR, "reg/mem64,uimm8", "C1/7ib", {}, {cpuAMD64});
		AddInstruction(opSBB, "reg/mem8,reg8", "18/r", {}, {cpu8086});
		AddInstruction(opSBB, "reg/mem16,reg16", "19/r", {optO16}, {cpu8086});
		AddInstruction(opSBB, "reg/mem32,reg32", "19/r", {optO32}, {cpu386});
		AddInstruction(opSBB, "reg/mem64,reg64", "19/r", {}, {cpuAMD64});
		AddInstruction(opSBB, "reg8,reg/mem8", "1A/r", {}, {cpu8086});
		AddInstruction(opSBB, "reg16,reg/mem16", "1B/r", {optO16}, {cpu8086});
		AddInstruction(opSBB, "reg32,reg/mem32", "1B/r", {optO32}, {cpu386});
		AddInstruction(opSBB, "reg64,reg/mem64", "1B/r", {}, {cpuAMD64});
		AddInstruction(opSBB, "AL,imm8", "1Cib", {}, {cpu8086});
		AddInstruction(opSBB, "AX,imm16", "1Diw", {optO16}, {cpu8086});
		AddInstruction(opSBB, "EAX,imm32", "1Did", {optO32}, {cpu386});
		AddInstruction(opSBB, "RAX,simm32", "1Did", {}, {cpuAMD64});
		AddInstruction(opSBB, "reg/mem8,imm8", "80/3ib", {}, {cpu8086});
		AddInstruction(opSBB, "reg/mem16,imm16", "81/3iw", {optO16}, {cpu8086});
		AddInstruction(opSBB, "reg/mem32,imm32", "81/3id", {optO32}, {cpu386});
		AddInstruction(opSBB, "reg/mem64,simm32", "81/3id", {}, {cpuAMD64});
		AddInstruction(opSBB, "reg/mem16,simm8", "83/3ib", {optO16}, {cpu8086});
		AddInstruction(opSBB, "reg/mem32,simm8", "83/3ib", {optO32}, {cpu386});
		AddInstruction(opSBB, "reg/mem64,simm8", "83/3ib", {}, {cpuAMD64});
		AddInstruction(opSCAS, "mem8", "AE", {}, {cpu8086});
		AddInstruction(opSCAS, "mem16", "AF", {optO16}, {cpu8086});
		AddInstruction(opSCAS, "mem32", "AF", {optO32}, {cpu386});
		AddInstruction(opSCAS, "mem64", "AF", {}, {cpuAMD64});
		AddInstruction(opSCASB, "", "AE", {}, {cpu8086});
		AddInstruction(opSCASD, "", "AF", {optO32}, {cpu386});
		AddInstruction(opSCASQ, "", "AF", {}, {cpuAMD64});
		AddInstruction(opSCASW, "", "AF", {optO16}, {cpu8086});
		AddInstruction(opSETA, "reg/mem8", "0F97/0", {}, {cpu386});
		AddInstruction(opSETAE, "reg/mem8", "0F93/0", {}, {cpu386});
		AddInstruction(opSETB, "reg/mem8", "0F92/0", {}, {cpu386});
		AddInstruction(opSETBE, "reg/mem8", "0F96/0", {}, {cpu386});
		AddInstruction(opSETC, "reg/mem8", "0F92/0", {}, {cpu386});
		AddInstruction(opSETE, "reg/mem8", "0F94/0", {}, {cpu386});
		AddInstruction(opSETG, "reg/mem8", "0F9F/0", {}, {cpu386});
		AddInstruction(opSETGE, "reg/mem8", "0F9D/0", {}, {cpu386});
		AddInstruction(opSETL, "reg/mem8", "0F9C/0", {}, {cpu386});
		AddInstruction(opSETLE, "reg/mem8", "0F9E/0", {}, {cpu386});
		AddInstruction(opSETNA, "reg/mem8", "0F96/0", {}, {cpu386});
		AddInstruction(opSETNAE, "reg/mem8", "0F92/0", {}, {cpu386});
		AddInstruction(opSETNB, "reg/mem8", "0F93/0", {}, {cpu386});
		AddInstruction(opSETNBE, "reg/mem8", "0F97/0", {}, {cpu386});
		AddInstruction(opSETNC, "reg/mem8", "0F93/0", {}, {cpu386});
		AddInstruction(opSETNE, "reg/mem8", "0F95/0", {}, {cpu386});
		AddInstruction(opSETNG, "reg/mem8", "0F9E/0", {}, {cpu386});
		AddInstruction(opSETNGE, "reg/mem8", "0F9C/0", {}, {cpu386});
		AddInstruction(opSETNL, "reg/mem8", "0F9D/0", {}, {cpu386});
		AddInstruction(opSETNLE, "reg/mem8", "0F9F/0", {}, {cpu386});
		AddInstruction(opSETNO, "reg/mem8", "0F91/0", {}, {cpu386});
		AddInstruction(opSETNP, "reg/mem8", "0F9B/0", {}, {cpu386});
		AddInstruction(opSETNS, "reg/mem8", "0F99/0", {}, {cpu386});
		AddInstruction(opSETNZ, "reg/mem8", "0F95/0", {}, {cpu386});
		AddInstruction(opSETO, "reg/mem8", "0F90/0", {}, {cpu386});
		AddInstruction(opSETP, "reg/mem8", "0F9A/0", {}, {cpu386});
		AddInstruction(opSETPE, "reg/mem8", "0F9A/0", {}, {cpu386});
		AddInstruction(opSETPO, "reg/mem8", "0F9B/0", {}, {cpu386});
		AddInstruction(opSETS, "reg/mem8", "0F98/0", {}, {cpu386});
		AddInstruction(opSETZ, "reg/mem8", "0F94/0", {}, {cpu386});
		AddInstruction(opSFENCE, "", "0FAEF8", {}, {cpuSSE,cpuMMX});
		AddInstruction(opSGDT, "mem16:32", "0F01/0", {}, {cpu286,cpuPrivileged});
		AddInstruction(opSGDT, "mem16:64", "0F01/0", {}, {cpuAMD64,cpuPrivileged});
		AddInstruction(opSHL, "reg/mem8,1", "D0/4", {}, {cpu8086});
		AddInstruction(opSHL, "reg/mem8,CL", "D2/4", {}, {cpu8086});
		AddInstruction(opSHL, "reg/mem8,uimm8", "C0/4ib", {}, {cpu186});
		AddInstruction(opSHL, "reg/mem16,1", "D1/4", {optO16}, {cpu8086});
		AddInstruction(opSHL, "reg/mem16,CL", "D3/4", {optO16}, {cpu8086});
		AddInstruction(opSHL, "reg/mem16,uimm8", "C1/4ib", {optO16}, {cpu186});
		AddInstruction(opSHL, "reg/mem32,1", "D1/4", {optO32}, {cpu386});
		AddInstruction(opSHL, "reg/mem32,CL", "D3/4", {optO32}, {cpu386});
		AddInstruction(opSHL, "reg/mem32,uimm8", "C1/4ib", {optO32}, {cpu386});
		AddInstruction(opSHL, "reg/mem64,1", "D1/4", {}, {cpuAMD64});
		AddInstruction(opSHL, "reg/mem64,CL", "D3/4", {}, {cpuAMD64});
		AddInstruction(opSHL, "reg/mem64,uimm8", "C1/4ib", {}, {cpuAMD64});
		AddInstruction(opSHLD, "reg/mem16,reg16,uimm8", "0FA4/rib", {optO16}, {cpu386});
		AddInstruction(opSHLD, "reg/mem16,reg16,CL", "0FA5/r", {optO16}, {cpu386});
		AddInstruction(opSHLD, "reg/mem32,reg32,uimm8", "0FA4/rib", {optO32}, {cpu386});
		AddInstruction(opSHLD, "reg/mem32,reg32,CL", "0FA5/r", {optO32}, {cpu386});
		AddInstruction(opSHLD, "reg/mem64,reg64,uimm8", "0FA4/rib", {}, {cpuAMD64});
		AddInstruction(opSHLD, "reg/mem64,reg64,CL", "0FA5/r", {}, {cpuAMD64});
		AddInstruction(opSHR, "reg/mem8,1", "D0/5", {}, {cpu8086});
		AddInstruction(opSHR, "reg/mem8,CL", "D2/5", {}, {cpu8086});
		AddInstruction(opSHR, "reg/mem8,uimm8", "C0/5ib", {}, {cpu186});
		AddInstruction(opSHR, "reg/mem16,1", "D1/5", {optO16}, {cpu8086});
		AddInstruction(opSHR, "reg/mem16,CL", "D3/5", {optO16}, {cpu8086});
		AddInstruction(opSHR, "reg/mem16,uimm8", "C1/5ib", {optO16}, {cpu186});
		AddInstruction(opSHR, "reg/mem32,1", "D1/5", {optO32}, {cpu386});
		AddInstruction(opSHR, "reg/mem32,CL", "D3/5", {optO32}, {cpu386});
		AddInstruction(opSHR, "reg/mem32,uimm8", "C1/5ib", {optO32}, {cpu386});
		AddInstruction(opSHR, "reg/mem64,1", "D1/5", {}, {cpuAMD64});
		AddInstruction(opSHR, "reg/mem64,CL", "D3/5", {}, {cpuAMD64});
		AddInstruction(opSHR, "reg/mem64,uimm8", "C1/5ib", {}, {cpuAMD64});
		AddInstruction(opSHRD, "reg/mem16,reg16,uimm8", "0FAC/rib", {optO16}, {cpu386});
		AddInstruction(opSHRD, "reg/mem16,reg16,CL", "0FAD/r", {optO16}, {cpu386});
		AddInstruction(opSHRD, "reg/mem32,reg32,uimm8", "0FAC/rib", {optO32}, {cpu386});
		AddInstruction(opSHRD, "reg/mem32,reg32,CL", "0FAD/r", {optO32}, {cpu386});
		AddInstruction(opSHRD, "reg/mem64,reg64,uimm8", "0FAC/rib", {}, {cpuAMD64});
		AddInstruction(opSHRD, "reg/mem64,reg64,CL", "0FAD/r", {}, {cpuAMD64});
		AddInstruction(opSHUFPD, "xmm1,xmm2/mem128,uimm8", "0FC6/rib", {optPOP}, {cpuSSE2});
		AddInstruction(opSHUFPS, "xmm1,xmm2/mem128,uimm8", "0FC6/rib", {}, {cpuSSE});
		AddInstruction(opSIDT, "mem16:32", "0F01/1", {}, {cpu286,cpuPrivileged});
		AddInstruction(opSIDT, "mem16:64", "0F01/1", {}, {cpuAMD64,cpuPrivileged});
		AddInstruction(opSKINIT, "EAX", "0F01DE", {}, {cpuAMD64});
		AddInstruction(opSLDT, "reg16", "0F00/0", {optO16}, {cpu286});
		AddInstruction(opSLDT, "reg32", "0F00/0", {optO32}, {cpu386});
		AddInstruction(opSLDT, "reg64", "0F00/0", {}, {cpuAMD64});
		AddInstruction(opSLDT, "mem16", "0F00/0", {}, {cpu286});
		AddInstruction(opSMSW, "reg16", "0F01/4", {optO16}, {cpu286});
		AddInstruction(opSMSW, "reg32", "0F01/4", {optO32}, {cpu386});
		AddInstruction(opSMSW, "reg64", "0F01/4", {}, {cpuAMD64});
		AddInstruction(opSMSW, "mem16", "0F01/4", {}, {cpu286});
		AddInstruction(opSQRTPD, "xmm1,xmm2/mem128", "0F51/r", {optPOP}, {cpuSSE2});
		AddInstruction(opSQRTPS, "xmm1,xmm2/mem128", "0F51/r", {}, {cpuSSE});
		AddInstruction(opSQRTSD, "xmm1,xmm2/mem64", "F20F51/r", {}, {cpuSSE2});
		AddInstruction(opSQRTSS, "xmm1,xmm2/mem32", "F30F51/r", {}, {cpuSSE});
		AddInstruction(opSTC, "", "F9", {}, {cpu8086});
		AddInstruction(opSTD, "", "FD", {}, {cpu8086});
		AddInstruction(opSTGI, "", "0F01DC", {}, {cpuPentium});
		AddInstruction(opSTI, "", "FB", {}, {cpu8086});
		AddInstruction(opSTMXCSR, "mem32", "0FAE/3", {}, {cpuSSE});
		AddInstruction(opSTOS, "mem8", "AA", {}, {cpu8086});
		AddInstruction(opSTOS, "mem16", "AB", {optO16}, {cpu8086});
		AddInstruction(opSTOS, "mem32", "AB", {optO32}, {cpu386});
		AddInstruction(opSTOS, "mem64", "AB", {}, {cpuAMD64});
		AddInstruction(opSTOSB, "", "AA", {}, {cpu8086});
		AddInstruction(opSTOSD, "", "AB", {optO32}, {cpu386});
		AddInstruction(opSTOSQ, "", "AB", {}, {cpuAMD64});
		AddInstruction(opSTOSW, "", "AB", {optO16}, {cpu8086});
		AddInstruction(opSTR, "reg16", "0F00/1", {optO16}, {cpu286,cpuProtected});
		AddInstruction(opSTR, "reg32", "0F00/1", {optO32}, {cpu386,cpuProtected});
		AddInstruction(opSTR, "reg64", "0F00/1", {}, {cpuAMD64});
		AddInstruction(opSTR, "mem16", "0F00/1", {}, {cpu286,cpuProtected});
		AddInstruction(opSUB, "reg/mem8,reg8", "28/r", {}, {cpu8086});
		AddInstruction(opSUB, "reg/mem16,reg16", "29/r", {optO16}, {cpu8086});
		AddInstruction(opSUB, "reg/mem32,reg32", "29/r", {optO32}, {cpu386});
		AddInstruction(opSUB, "reg/mem64,reg64", "29/r", {}, {cpuAMD64});
		AddInstruction(opSUB, "reg8,reg/mem8", "2A/r", {}, {cpu8086});
		AddInstruction(opSUB, "reg16,reg/mem16", "2B/r", {optO16}, {cpu8086});
		AddInstruction(opSUB, "reg32,reg/mem32", "2B/r", {optO32}, {cpu386});
		AddInstruction(opSUB, "reg64,reg/mem64", "2B/r", {}, {cpuAMD64});
		AddInstruction(opSUB, "AL,imm8", "2Cib", {}, {cpu8086});
		AddInstruction(opSUB, "AX,imm16", "2Diw", {optO16}, {cpu8086});
		AddInstruction(opSUB, "EAX,imm32", "2Did", {optO32}, {cpu386});
		AddInstruction(opSUB, "RAX,simm32", "2Did", {}, {cpuAMD64});
		AddInstruction(opSUB, "reg/mem8,imm8", "80/5ib", {}, {cpu8086});
		AddInstruction(opSUB, "reg/mem16,imm16", "81/5iw", {optO16}, {cpu8086});
		AddInstruction(opSUB, "reg/mem32,imm32", "81/5id", {optO32}, {cpu386});
		AddInstruction(opSUB, "reg/mem64,simm32", "81/5id", {}, {cpuAMD64});
		AddInstruction(opSUB, "reg/mem16,simm8", "83/5ib", {optO16}, {cpu8086});
		AddInstruction(opSUB, "reg/mem32,simm8", "83/5ib", {optO32}, {cpu386});
		AddInstruction(opSUB, "reg/mem64,simm8", "83/5ib", {}, {cpuAMD64});
		AddInstruction(opSUBPD, "xmm1,xmm2/mem128", "0F5C/r", {optPOP}, {cpuSSE2});
		AddInstruction(opSUBPS, "xmm1,xmm2/mem128", "0F5C/r", {}, {cpuSSE});
		AddInstruction(opSUBSD, "xmm1,xmm2/mem64", "F20F5C/r", {}, {cpuSSE2});
		AddInstruction(opSUBSS, "xmm1,xmm2/mem32", "F30F5C/r", {}, {cpuSSE});
		AddInstruction(opSWAPGS, "", "0F01F8", {}, {cpuAMD64});
		AddInstruction(opSYSCALL, "", "0F05", {}, {cpuP6});
		AddInstruction(opSYSENTER, "", "0F34", {optNot64}, {cpuP6});
		AddInstruction(opSYSEXIT, "", "0F35", {optNot64}, {cpuP6,cpuPrivileged});
		AddInstruction(opSYSRET, "", "0F07", {}, {cpuP6,cpuPrivileged});
		AddInstruction(opTEST, "reg/mem8,reg8", "84/r", {}, {cpu8086});
		AddInstruction(opTEST, "reg/mem16,reg16", "85/r", {optO16}, {cpu8086});
		AddInstruction(opTEST, "reg/mem32,reg32", "85/r", {optO32}, {cpu386});
		AddInstruction(opTEST, "reg/mem64,reg64", "85/r", {}, {cpuAMD64});
		AddInstruction(opTEST, "AL,imm8", "A8ib", {}, {cpu8086});
		AddInstruction(opTEST, "AX,imm16", "A9iw", {optO16}, {cpu8086});
		AddInstruction(opTEST, "EAX,imm32", "A9id", {optO32}, {cpu386});
		AddInstruction(opTEST, "RAX,simm32", "A9id", {}, {cpuAMD64});
		AddInstruction(opTEST, "reg/mem8,imm8", "F6/0ib", {}, {cpu8086});
		AddInstruction(opTEST, "reg/mem16,imm16", "F7/0iw", {optO16}, {cpu8086});
		AddInstruction(opTEST, "reg/mem32,imm32", "F7/0id", {optO32}, {cpu386});
		AddInstruction(opTEST, "reg/mem64,simm32", "F7/0id", {}, {cpuAMD64});
		AddInstruction(opUCOMISD, "xmm1,xmm2/mem64", "0F2E/r", {optPOP}, {cpuSSE2});
		AddInstruction(opUCOMISS, "xmm1,xmm2/mem32", "0F2E/r", {}, {cpuSSE});
		AddInstruction(opUD2, "", "0F0B", {}, {cpu286});
		AddInstruction(opUNPCKHPD, "xmm1,xmm2/mem128", "0F15/r", {optPOP}, {cpuSSE2});
		AddInstruction(opUNPCKHPS, "xmm1,xmm2/mem128", "0F15/r", {}, {cpuSSE});
		AddInstruction(opUNPCKLPD, "xmm1,xmm2/mem128", "0F14/r", {optPOP}, {cpuSSE2});
		AddInstruction(opUNPCKLPS, "xmm1,xmm2/mem128", "0F14/r", {}, {cpuSSE});
		AddInstruction(opVERR, "reg/mem16", "0F00/4", {}, {cpu286,cpuPrivileged});
		AddInstruction(opVERW, "reg/mem16", "0F00/5", {}, {cpu286,cpuPrivileged});
		AddInstruction(opVMLOAD, "rAX", "0F01DA", {}, {cpuAMD64});
		AddInstruction(opVMMCALL, "", "0F01D9", {}, {cpuAMD64});
		AddInstruction(opVMRUN, "rAX", "0F01D8", {}, {cpuAMD64});
		AddInstruction(opVMSAVE, "rAX", "0F01DB", {}, {cpuAMD64});
		AddInstruction(opWBINVD, "", "0F09", {}, {cpu486,cpuPrivileged});
		AddInstruction(opWRMSR, "", "0F30", {}, {cpuPentium,cpuPrivileged});
		AddInstruction(opXADD, "reg/mem8,reg8", "0FC0/r", {}, {cpu486});
		AddInstruction(opXADD, "reg/mem16,reg16", "0FC1/r", {optO16}, {cpu486});
		AddInstruction(opXADD, "reg/mem32,reg32", "0FC1/r", {optO32}, {cpu486});
		AddInstruction(opXADD, "reg/mem64,reg64", "0FC1/r", {}, {cpuAMD64});
		AddInstruction(opXCHG, "AX,reg16", "90rw", {optO16}, {cpu8086});
		AddInstruction(opXCHG, "reg16,AX", "90rw", {optO16}, {cpu8086});
		AddInstruction(opXCHG, "EAX,reg32", "90rd", {optO32}, {cpu386});
		AddInstruction(opXCHG, "reg32,EAX", "90rd", {optO32}, {cpu386});
		AddInstruction(opXCHG, "RAX,reg64", "90rq", {}, {cpuAMD64});
		AddInstruction(opXCHG, "reg64,RAX", "90rq", {}, {cpuAMD64});
		AddInstruction(opXCHG, "reg/mem8,reg8", "86/r", {}, {cpu8086});
		AddInstruction(opXCHG, "reg8,reg/mem8", "86/r", {}, {cpu8086});
		AddInstruction(opXCHG, "reg/mem16,reg16", "87/r", {optO16}, {cpu8086});
		AddInstruction(opXCHG, "reg16,reg/mem16", "87/r", {optO16}, {cpu8086});
		AddInstruction(opXCHG, "reg/mem32,reg32", "87/r", {optO32}, {cpu386});
		AddInstruction(opXCHG, "reg32,reg/mem32", "87/r", {optO32}, {cpu386});
		AddInstruction(opXCHG, "reg/mem64,reg64", "87/r", {}, {cpuAMD64});
		AddInstruction(opXCHG, "reg64,reg/mem64", "87/r", {}, {cpuAMD64});
		AddInstruction(opXLAT, "mem8", "D7", {}, {cpu8086});
		AddInstruction(opXLATB, "", "D7", {}, {cpu8086});
		AddInstruction(opXOR, "reg/mem8,reg8", "30/r", {}, {cpu8086});
		AddInstruction(opXOR, "reg/mem16,reg16", "31/r", {optO16}, {cpu8086});
		AddInstruction(opXOR, "reg/mem32,reg32", "31/r", {optO32}, {cpu386});
		AddInstruction(opXOR, "reg/mem64,reg64", "31/r", {}, {cpuAMD64});
		AddInstruction(opXOR, "reg8,reg/mem8", "32/r", {}, {cpu8086});
		AddInstruction(opXOR, "reg16,reg/mem16", "33/r", {optO16}, {cpu8086});
		AddInstruction(opXOR, "reg32,reg/mem32", "33/r", {optO32}, {cpu386});
		AddInstruction(opXOR, "reg64,reg/mem64", "33/r", {}, {cpuAMD64});
		AddInstruction(opXOR, "AL,imm8", "34ib", {}, {cpu8086});
		AddInstruction(opXOR, "AX,imm16", "35iw", {optO16}, {cpu8086});
		AddInstruction(opXOR, "EAX,imm32", "35id", {optO32}, {cpu386});
		AddInstruction(opXOR, "RAX,simm32", "35id", {}, {cpuAMD64});
		AddInstruction(opXOR, "reg/mem8,imm8", "80/6ib", {}, {cpu8086});
		AddInstruction(opXOR, "reg/mem16,imm16", "81/6iw", {optO16}, {cpu8086});
		AddInstruction(opXOR, "reg/mem32,imm32", "81/6id", {optO32}, {cpu386});
		AddInstruction(opXOR, "reg/mem64,simm32", "81/6id", {}, {cpuAMD64});
		AddInstruction(opXOR, "reg/mem16,simm8", "83/6ib", {optO16}, {cpu8086});
		AddInstruction(opXOR, "reg/mem32,simm8", "83/6ib", {optO32}, {cpu386});
		AddInstruction(opXOR, "reg/mem64,simm8", "83/6ib", {}, {cpuAMD64});
		AddInstruction(opXORPD, "xmm1,xmm2/mem128", "0F57/r", {optPOP}, {cpuSSE2});
		AddInstruction(opXORPS, "xmm1,xmm2/mem128", "0F57/r", {}, {cpuSSE});

		AddInstructionV(opVAESKEYGENASSIST,"xmm1,xmm2/mem128,imm8","C4 RXB.00011 X.src.0.01 DF /r ib");
		AddInstructionV(opVPMADCSWD,"xmm1,xmm2,xmm3/mem128,xmm4","8F RXB.08 0.src1.0.00 B6 /r ib");
		AddInstructionV(opVADDPD,"xmm1,xmm2,xmm3/mem128","C4 RXB.00001 X.src.0.01 58 /r");
		AddInstructionV(opVADDPD,"ymm1,ymm2,ymm3/mem256","C4 RXB.00001 X.src.1.01 58 /r");
		AddInstructionV(opVADDPS,"xmm1,xmm2,xmm3/mem128","C4 RXB.00001 X.src.0.00 58 /r");
		AddInstructionV(opVADDPS,"ymm1,ymm2,ymm3/mem256","C4 RXB.00001 X.src.1.00 58 /r");
		AddInstructionV(opVADDSD,"xmm1,xmm2,xmm3/mem64","C4 RXB.00001 X.src.X.11 58 /r");
		AddInstructionV(opVADDSS,"xmm1,xmm2,xmm3/mem32","C4 RXB.00001 X.src.X.10 58 /r");
		AddInstructionV(opVADDSUBPD,"xmm1,xmm2,xmm3/mem128","C4 RXB.00001 X.src.0.01 D0 /r");
		AddInstructionV(opVADDSUBPD,"ymm1,ymm2,ymm3/mem256","C4 RXB.00001 X.src.1.01 D0 /r");
		AddInstructionV(opVADDSUBPS,"xmm1,xmm2,xmm3/mem128","C4 RXB.00001 X.src.0.11 D0 /r");
		AddInstructionV(opVADDSUBPS,"ymm1,ymm2,ymm3/mem256","C4 RXB.00001 X.src.1.11 D0 /r");
		AddInstructionV(opVAESDEC,"xmm1,xmm2,xmm3/mem128","C4 RXB.00010 X.src.0.01 DE /r");
		AddInstructionV(opVAESDECLAST,"xmm1,xmm2,xmm3/mem128","C4 RXB.00010 X.src.0.01 DF /r");
		AddInstructionV(opVAESENC,"xmm1,xmm2,xmm3/mem128","C4 RXB.00010 X.src.0.01 DC /r");
		AddInstructionV(opVAESENCLAST,"xmm1,xmm2,xmm3/mem128","C4 RXB.00010 X.src.0.01 DD /r");
		AddInstructionV(opVAESIMC,"xmm1,xmm2/mem128","C4 RXB.00010 X.src.0.01 DB /r");
		AddInstructionV(opVANDNPD,"xmm1,xmm2,xmm3/mem128","C4 RXB.00001 X.src.0.01 55 /r");
		AddInstructionV(opVANDNPD,"ymm1,ymm2,ymm3/mem256","C4 RXB.00001 X.src.1.01 55 /r");
		AddInstructionV(opVANDNPS,"xmm1,xmm2,xmm3/mem128","C4 RXB.00001 X.src.0.00 55 /r");
		AddInstructionV(opVANDNPS,"ymm1,ymm2,ymm3/mem256","C4 RXB.00001 X.src.1.00 55 /r");
		AddInstructionV(opVANDPD,"xmm1,xmm2,xmm3/mem128","C4 RXB.00001 X.src.0.01 54 /r");
		AddInstructionV(opVANDPD,"ymm1,ymm2,ymm3/mem256","C4 RXB.00001 X.src.1.01 54 /r");
		AddInstructionV(opVANDPS,"xmm1,xmm2,xmm3/mem128","C4 RXB.00001 X.src.0.00 54 /r");
		AddInstructionV(opVANDPS,"ymm1,ymm2,ymm3/mem256","C4 RXB.00001 X.src.1.00 54 /r");
		AddInstructionV(opVBLENDPD,"xmm1,xmm2,xmm3/mem128,imm8","C4 RXB.00011 X.src.0.01 0D /r ib");
		AddInstructionV(opVBLENDPD,"ymm1,ymm2,ymm3/mem256,imm8","C4 RXB.00011 X.src.1.01 0D /r ib");
		AddInstructionV(opVBLENDPS,"xmm1,xmm2,xmm3/mem128,imm8","C4 RXB.00011 X.src.0.01 0C /r ib");
		AddInstructionV(opVBLENDPS,"ymm1,ymm2,ymm3/mem256,imm8","C4 RXB.00011 X.src.1.01 0C /r ib");
		AddInstructionV(opVBLENDVPD,"xmm1,xmm2,xmm3/mem128,xmm4","C4 RXB.00011 X.src.0.01 4B /r");
		AddInstructionV(opVBLENDVPD,"ymm1,ymm2,ymm3/mem256,ymm4","C4 RXB.00011 X.src.1.01 4B /r");
		AddInstructionV(opVBLENDVPS,"xmm1,xmm2,xmm3/mem128,xmm4","C4 RXB.00011 X.src.0.01 4A /r");
		AddInstructionV(opVBLENDVPS,"ymm1,ymm2,ymm3/mem256,ymm4","C4 RXB.00011 X.src.1.01 4A /r");
		AddInstructionV(opVBROADCASTF128,"ymm1,mem128","C4 RXB.02 0.1111.1.01 1A /r");
		AddInstructionV(opVBROADCASTI128,"ymm1,mem128","C4 RXB.02 0.1111.1.01 5A /r");
		AddInstructionV(opVBROADCASTSD,"ymm1,xmm2/mem64","C4 RXB.02 0.1111.1.01 19 /r");
		AddInstructionV(opVBROADCASTSS,"xmm1,xmm2/mem32","C4 RXB.02 0.1111.0.01 18 /r");
		AddInstructionV(opVBROADCASTSS,"ymm1,xmm2/mem32","C4 RXB.02 0.1111.1.01 18 /r");
		AddInstructionV(opVCMPPD,"xmm1,xmm2,xmm3/mem128,imm8","C4 RXB.00001 X.src.0.01 C2 /r ib");
		AddInstructionV(opVCMPPD,"ymm1,ymm2,ymm3/mem256,imm8","C4 RXB.00001 X.src.1.01 C2 /r ib");
		AddInstructionV(opVCMPPS,"xmm1,xmm2,xmm3/mem128,imm8","C4 RXB.00001 X.src.0.00 C2 /r ib");
		AddInstructionV(opVCMPSD,"xmm1,xmm2,xmm3/mem64,imm8","C4 RXB.00001 X.src.X.11 C2 /r ib");
		AddInstructionV(opVCMPSS,"xmm1,xmm2,xmm3/mem32,imm8","C4 RXB.00001 X.src.X.10 C2 /r ib");
		AddInstructionV(opVCOMISD,"xmm1,xmm2/mem64","C4 RXB.00001 X.src.X.01 2F /r");
		AddInstructionV(opVCOMISS,"xmm1,xmm2/mem32","C4 RXB.00001 X.src.X.00 2F /r");
		AddInstructionV(opVCVTDQ2PD,"xmm1,xmm2/mem64","C4 RXB.00001 X.1111.0.10 E6 /r");
		AddInstructionV(opVCVTDQ2PD,"ymm1,ymm2/mem128","C4 RXB.00001 X.1111.1.10 E6 /r");
		AddInstructionV(opVCVTDQ2PS,"xmm1,xmm2/mem128","C4 RXB.00001 X.1111.0.00 5B /r");
		AddInstructionV(opVCVTDQ2PS,"ymm1,ymm2/mem256","C4 RXB.00001 X.1111.1.00 5B /r");
		AddInstructionV(opVCVTPD2DQ,"xmm1,xmm2/mem128","C4 RXB.00001 X.1111.0.11 E6 /r");
		AddInstructionV(opVCVTPD2DQ,"xmm1,ymm2/mem256","C4 RXB.00001 X.1111.1.11 E6 /r");
		AddInstructionV(opVCVTPD2PS,"xmm1,xmm2/mem128","C4 RXB.00001 X.1111.0.01 5A /r");
		AddInstructionV(opVCVTPD2PS,"xmm1,ymm2/mem256","C4 RXB.00001 X.1111.1.01 5A /r");
		AddInstructionV(opVCVTPH2PS,"xmm1,xmm2/mem64","C4 RXB.02 0.1111.0.01 13 /r");
		AddInstructionV(opVCVTPH2PS,"ymm1,xmm2/mem128","C4 RXB.02 0.1111.1.01 13 /r");
		AddInstructionV(opVCVTPS2DQ,"xmm1,xmm2/mem128","C4 RXB.00001 X.1111.0.01 5B /r");
		AddInstructionV(opVCVTPS2DQ,"ymm1,ymm2/mem256","C4 RXB.00001 X.1111.1.01 5B /r");
		AddInstructionV(opVCVTPS2PD,"xmm1,xmm2/mem64","C4 RXB.00001 X.1111.0.00 5A /r");
		AddInstructionV(opVCVTPS2PD,"ymm1,ymm2/mem128","C4 RXB.00001 X.1111.1.00 5A /r");
		AddInstructionV(opVCVTPS2PH,"xmm1/mem64,xmm2,imm8","C4 RXB.03 0.1111.0.01 1D /r /ib");
		AddInstructionV(opVCVTPS2PH,"xmm1/mem128,ymm2,imm8","C4 RXB.03 0.1111.1.01 1D /r /ib");
		AddInstructionV(opVCVTSD2SI,"reg32,xmm2/mem64","C4 RXB.00001 0.1111.X.11 2D /r");
		AddInstructionV(opVCVTSD2SI,"reg64,xmm2/mem64","C4 RXB.00001 1.1111.X.11 2D /r");
		AddInstructionV(opVCVTSD2SS,"xmm1,xmm2,xmm3/mem64","C4 RXB.00001 X.src.X.11 5A /r");
		AddInstructionV(opVCVTSI2SD,"xmm1,xmm2,reg32/mem32","C4 RXB.00001 0.src.X.11 2A /r");
		AddInstructionV(opVCVTSI2SD,"xmm1,xmm2,reg64/mem64","C4 RXB.00001 1.src.X.11 2A /r");
		AddInstructionV(opVCVTSI2SS,"xmm1,xmm2,reg32/mem32","C4 RXB.00001 0.src.X.10 2A /r");
		AddInstructionV(opVCVTSI2SS,"xmm1,xmm2,reg64/mem64","C4 RXB.00001 1.src.X.10 2A /r");
		AddInstructionV(opVCVTSS2SD,"xmm1,xmm2,xmm3/mem64","C4 RXB.00001 X.src.X.10 5A /r");
		AddInstructionV(opVCVTSS2SI,"reg32,xmm1/mem32","C4 RXB.00001 0.1111.X.10 2D /r");
		AddInstructionV(opVCVTSS2SI,"reg64,xmm1/mem32","C4 RXB.00001 1.1111.X.10 2D /r");
		AddInstructionV(opVCVTTPD2DQ,"xmm1,xmm2/mem128","C4 RXB.00001 X.1111.0.01 E6 /r");
		AddInstructionV(opVCVTTPD2DQ,"xmm1,ymm2/mem256","C4 RXB.00001 X.1111.1.01 E6 /r");
		AddInstructionV(opVCVTTPS2DQ,"xmm1,xmm2/mem128","C4 RXB.00001 X.1111.0.10 5B /r");
		AddInstructionV(opVCVTTPS2DQ,"ymm1,ymm2/mem256","C4 RXB.00001 X.1111.1.10 5B /r");
		AddInstructionV(opVCVTTSD2SI,"reg32,xmm2/mem64","C4 RXB.00001 0.1111.X.11 2C /r");
		AddInstructionV(opVCVTTSD2SI,"reg64,xmm2/mem64","C4 RXB.00001 1.1111.X.11 2C /r");
		AddInstructionV(opVCVTTSS2SI,"reg32,xmm1/mem32","C4 RXB.00001 0.1111.X.10 2C /r");
		AddInstructionV(opVCVTTSS2SI,"reg64,xmm1/mem32","C4 RXB.00001 1.1111.X.10 2C /r");
		AddInstructionV(opVDIVPD,"xmm1,xmm2,xmm3/mem128","C4 RXB.00001 X.src.0.01 5E /r");
		AddInstructionV(opVDIVPD,"ymm1,ymm2,ymm3/mem256","C4 RXB.00001 X.src.1.01 5E /r");
		AddInstructionV(opVDIVPS,"xmm1,xmm2,xmm3/mem128","C4 RXB.00001 X.src.0.00 5E /r");
		AddInstructionV(opVDIVPS,"ymm1,ymm2,ymm3/mem256","C4 RXB.00001 X.src.1.00 5E /r");
		AddInstructionV(opVDIVSD,"xmm1,xmm2,xmm3/mem64","C4 RXB.00001 X.src.X.11 5E /r");
		AddInstructionV(opVDIVSS,"xmm1,xmm2,xmm3/mem32","C4 RXB.00001 X.src.X.10 5E /r");
		AddInstructionV(opVDPPD,"xmm1,xmm2,xmm3/mem128,imm8","C4 RXB.00011 X.src.0.01 41 /r ib");
		AddInstructionV(opVDPPS,"xmm1,xmm2,xmm3/mem128,imm8","C4 RXB.00011 X.src.0.01 40 /r ib");
		AddInstructionV(opVDPPS,"ymm1,ymm2,ymm3/mem256,imm8","C4 RXB.00011 X.src.1.01 40 /r ib");
		AddInstructionV(opVEXTRACTF128,"xmm1/mem128,ymm2,imm8","C4 RXB.03 0.1111.1.01 19 /r ib");
		AddInstructionV(opVEXTRACTI128,"xmm1/mem128,ymm2,imm8","C4 RXB.03 0.1111.1.01 39 /r ib");
		AddInstructionV(opVEXTRACTPS,"reg32/mem32,xmm1,imm8","C4 RXB.00011 X.1111.0.01 17 /r ib");
		AddInstructionV(opVFMADD132PD,"xmm0,xmm1,xmm2/m128","C4 RXB.02 1.src2.0.01 98 /r");
		AddInstructionV(opVFMADD132PD,"ymm0,ymm1,ymm2/m256","C4 RXB.02 1.src2.1.01 98 /r");
		AddInstructionV(opVFMADD132PS,"xmm0,xmm1,xmm2/m128","C4 RXB.02 0.src2.0.01 98 /r");
		AddInstructionV(opVFMADD132PS,"ymm0,ymm1,ymm2/m256","C4 RXB.02 0.src2.1.01 98 /r");
		AddInstructionV(opVFMADD132SD,"xmm0,xmm1,xmm2/m64","C4 RXB.02 1.src2.X.01 99 /r");
		AddInstructionV(opVFMADD132SS,"xmm1,xmm2,xmm3/mem32","C4 RXB.02 0.src2.X.01 99 /r");
		AddInstructionV(opVFMADD213PD,"xmm0,xmm1,xmm2/m128","C4 RXB.02 1.src2.0.01 A8 /r");
		AddInstructionV(opVFMADD213PD,"ymm0,ymm1,ymm2/m256","C4 RXB.02 1.src2.1.01 A8 /r");
		AddInstructionV(opVFMADD213PS,"xmm0,xmm1,xmm2/m128","C4 RXB.02 0.src2.0.01 A8 /r");
		AddInstructionV(opVFMADD213PS,"ymm0,ymm1,ymm2/m256","C4 RXB.02 0.src2.1.01 A8 /r");
		AddInstructionV(opVFMADD213SD,"xmm0,xmm1,xmm2/m64","C4 RXB.02 1.src2.X.01 A9 /r");
		AddInstructionV(opVFMADD213SS,"xmm1,xmm2,xmm3/mem32","C4 RXB.02 0.src2.X.01 A9 /r");
		AddInstructionV(opVFMADD231PD,"xmm0,xmm1,xmm2/m128","C4 RXB.02 1.src2.0.01 B8 /r");
		AddInstructionV(opVFMADD231PD,"ymm0,ymm1,ymm2/m256","C4 RXB.02 1.src2.1.01 B8 /r");
		AddInstructionV(opVFMADD231PS,"xmm0,xmm1,xmm2/m128","C4 RXB.02 0.src2.0.01 B8 /r");
		AddInstructionV(opVFMADD231PS,"ymm0,ymm1,ymm2/m256","C4 RXB.02 0.src2.1.01 B8 /r");
		AddInstructionV(opVFMADD231SD,"xmm0,xmm1,xmm2/m64","C4 RXB.02 1.src2.X.01 B9 /r");
		AddInstructionV(opVFMADD231SS,"xmm1,xmm2,xmm3/mem32","C4 RXB.02 0.src2.X.01 B9 /r");
		AddInstructionV(opVFMADDPD,"xmm1,xmm2,xmm3/mem128,xmm4","C4 RXB.03 0.src1.0.01 69 /r /is4");
		AddInstructionV(opVFMADDPD,"ymm1,ymm2,ymm3/mem256,ymm4","C4 RXB.03 0.src1.1.01 69 /r /is4");
		AddInstructionV(opVFMADDPD,"xmm1,xmm2,xmm3,xmm4/mem128","C4 RXB.03 1.src1.0.01 69 /r /is4");
		AddInstructionV(opVFMADDPD,"ymm1,ymm2,ymm3,ymm4/mem256","C4 RXB.03 1.src1.1.01 69 /r /is4");
		AddInstructionV(opVFMADDPS,"xmm1,xmm2,xmm3/mem128,xmm4","C4 RXB.03 0.src1.0.01 68 /r /is4");
		AddInstructionV(opVFMADDPS,"ymm1,ymm2,ymm3/mem256,ymm4","C4 RXB.03 0.src1.1.01 68 /r /is4");
		AddInstructionV(opVFMADDPS,"xmm1,xmm2,xmm3,xmm4/mem128","C4 RXB.03 1.src1.0.01 68 /r /is4");
		AddInstructionV(opVFMADDPS,"ymm1,ymm2,ymm3,ymm4/mem256","C4 RXB.03 1.src1.1.01 68 /r /is4");
		AddInstructionV(opVFMADDSD,"xmm1,xmm2,xmm3/mem64,xmm4","C4 RXB.03 0.src1.X.01 6B /r /is4");
		AddInstructionV(opVFMADDSD,"xmm1,xmm2,xmm3,xmm4/mem64","C4 RXB.03 1.src1.X.01 6B /r /is4");
		AddInstructionV(opVFMADDSS,"xmm1,xmm2,xmm3/mem32,xmm4","C4 RXB.03 0.src1.X.01 6A /r /is4");
		AddInstructionV(opVFMADDSS,"xmm1,xmm2,xmm3,xmm4/mem32","C4 RXB.03 1.src1.X.01 6A /r /is4");
		AddInstructionV(opVFMADDSUB132PD,"xmm1,xmm2,xmm3/mem128","C4 RXB.02 1.src2.0.01 96 /r");
		AddInstructionV(opVFMADDSUB132PD,"ymm1,ymm2,ymm3/mem256","C4 RXB.02 1.src2.1.01 96 /r");
		AddInstructionV(opVFMADDSUB132PS,"xmm1,xmm2,xmm3/mem128","C4 RXB.02 0.src2.0.01 96 /r");
		AddInstructionV(opVFMADDSUB132PS,"ymm1,ymm2,ymm3/mem256","C4 RXB.02 0.src2.1.01 96 /r");
		AddInstructionV(opVFMADDSUB213PD,"xmm1,xmm2,xmm3/mem128","C4 RXB.02 1.src2.0.01 A6 /r");
		AddInstructionV(opVFMADDSUB213PD,"ymm1,ymm2,ymm3/mem256","C4 RXB.02 1.src2.1.01 A6 /r");
		AddInstructionV(opVFMADDSUB213PS,"xmm1,xmm2,xmm3/mem128","C4 RXB.02 0.src2.0.01 A6 /r");
		AddInstructionV(opVFMADDSUB213PS,"ymm1,ymm2,ymm3/mem256","C4 RXB.02 0.src2.1.01 A6 /r");
		AddInstructionV(opVFMADDSUB231PD,"xmm1,xmm2,xmm3/mem128","C4 RXB.02 1.src2.0.01 B6 /r");
		AddInstructionV(opVFMADDSUB231PD,"ymm1,ymm2,ymm3/mem256","C4 RXB.02 1.src2.1.01 B6 /r");
		AddInstructionV(opVFMADDSUB231PS,"xmm1,xmm2,xmm3/mem128","C4 RXB.02 0.src2.0.01 B6 /r");
		AddInstructionV(opVFMADDSUB231PS,"ymm1,ymm2,ymm3/mem256","C4 RXB.02 0.src2.1.01 B6 /r");
		AddInstructionV(opVFMADDSUBPD,"xmm1,xmm2,xmm3/mem128,xmm4","C4 RXB.03 0.src1.0.01 5D /r /is4");
		AddInstructionV(opVFMADDSUBPD,"ymm1,ymm2,ymm3/mem256,ymm4","C4 RXB.03 0.src1.1.01 5D /r /is4");
		AddInstructionV(opVFMADDSUBPD,"xmm1,xmm2,xmm3,xmm4/mem128","C4 RXB.03 1.src1.0.01 5D /r /is4");
		AddInstructionV(opVFMADDSUBPD,"ymm1,ymm2,ymm3,ymm4/mem256","C4 RXB.03 1.src1.1.01 5D /r /is4");
		AddInstructionV(opVFMADDSUBPS,"xmm1,xmm2,xmm3/mem128,xmm4","C4 RXB.03 0.src1.0.01 5C /r /is4");
		AddInstructionV(opVFMADDSUBPS,"ymm1,ymm2,ymm3/mem256,ymm4","C4 RXB.03 0.src1.1.01 5C /r /is4");
		AddInstructionV(opVFMADDSUBPS,"xmm1,xmm2,xmm3,xmm4/mem128","C4 RXB.03 1.src1.0.01 5C /r /is4");
		AddInstructionV(opVFMADDSUBPS,"ymm1,ymm2,ymm3,ymm4/mem256","C4 RXB.03 1.src1.1.01 5C /r /is4");
		AddInstructionV(opVFMSUB132PD,"xmm1,xmm2,xmm3/mem128","C4 RXB.02 1.src2.0.01 9A /r");
		AddInstructionV(opVFMSUB132PD,"ymm1,ymm2,ymm3/mem256","C4 RXB.02 1.src2.1.01 9A /r");
		AddInstructionV(opVFMSUB132PS,"xmm1,xmm2,xmm3/mem128","C4 RXB.02 0.src2.0.01 9A /r");
		AddInstructionV(opVFMSUB132PS,"ymm1,ymm2,ymm3/mem256","C4 RXB.02 0.src2.1.01 9A /r");
		AddInstructionV(opVFMSUB132SD,"xmm1,xmm2,xmm3/mem64","C4 RXB.02 1.src2.X.01 9B /r");
		AddInstructionV(opVFMSUB132SS,"xmm1,xmm2,xmm3/mem32","C4 RXB.02 0.src2.X.01 9B /r");
		AddInstructionV(opVFMSUB213PD,"xmm1,xmm2,xmm3/mem128","C4 RXB.02 1.src2.0.01 AA /r");
		AddInstructionV(opVFMSUB213PD,"ymm1,ymm2,ymm3/mem256","C4 RXB.02 1.src2.1.01 AA /r");
		AddInstructionV(opVFMSUB213PS,"xmm1,xmm2,xmm3/mem128","C4 RXB.02 0.src2.0.01 AA /r");
		AddInstructionV(opVFMSUB213PS,"ymm1,ymm2,ymm3/mem256","C4 RXB.02 0.src2.1.01 AA /r");
		AddInstructionV(opVFMSUB213SD,"xmm1,xmm2,xmm3/mem64","C4 RXB.02 1.src2.X.01 AB /r");
		AddInstructionV(opVFMSUB213SS,"xmm1,xmm2,xmm3/mem32","C4 RXB.02 0.src2.X.01 AB /r");
		AddInstructionV(opVFMSUB231PD,"xmm1,xmm2,xmm3/mem128","C4 RXB.02 1.src2.0.01 BA /r");
		AddInstructionV(opVFMSUB231PD,"ymm1,ymm2,ymm3/mem256","C4 RXB.02 1.src2.1.01 BA /r");
		AddInstructionV(opVFMSUB231PS,"xmm1,xmm2,xmm3/mem128","C4 RXB.02 0.src2.0.01 BA /r");
		AddInstructionV(opVFMSUB231PS,"ymm1,ymm2,ymm3/mem256","C4 RXB.02 0.src2.1.01 BA /r");
		AddInstructionV(opVFMSUB231SD,"xmm1,xmm2,xmm3/mem64","C4 RXB.02 1.src2.X.01 BB /r");
		AddInstructionV(opVFMSUB231SS,"xmm1,xmm2,xmm3/mem32","C4 RXB.02 0.src2.X.01 BB /r");
		AddInstructionV(opVFMSUBADD132PD,"xmm1,xmm2,xmm3/mem128","C4 RXB.02 1.src2.0.01 97 /r");
		AddInstructionV(opVFMSUBADD132PD,"ymm1,ymm2,ymm3/mem256","C4 RXB.02 1.src2.1.01 97 /r");
		AddInstructionV(opVFMSUBADD132PS,"xmm1,xmm2,xmm3/mem128","C4 RXB.00010 0.src2.0.01 97 /r");
		AddInstructionV(opVFMSUBADD132PS,"ymm1,ymm2,ymm3/mem256","C4 RXB.00010 0.src2.1.01 97 /r");
		AddInstructionV(opVFMSUBADD213PD,"xmm1,xmm2,xmm3/mem128","C4 RXB.02 1.src2.0.01 A7 /r");
		AddInstructionV(opVFMSUBADD213PD,"ymm1,ymm2,ymm3/mem256","C4 RXB.02 1.src2.1.01 A7 /r");
		AddInstructionV(opVFMSUBADD213PS,"xmm1,xmm2,xmm3/mem128","C4 RXB.00010 0.src2.0.01 A7 /r");
		AddInstructionV(opVFMSUBADD213PS,"ymm1,ymm2,ymm3/mem256","C4 RXB.00010 0.src2.1.01 A7 /r");
		AddInstructionV(opVFMSUBADD231PD,"xmm1,xmm2,xmm3/mem128","C4 RXB.02 1.src2.0.01 B7 /r");
		AddInstructionV(opVFMSUBADD231PD,"ymm1,ymm2,ymm3/mem256","C4 RXB.02 1.src2.1.01 B7 /r");
		AddInstructionV(opVFMSUBADD231PS,"xmm1,xmm2,xmm3/mem128","C4 RXB.00010 0.src2.0.01 B7 /r");
		AddInstructionV(opVFMSUBADD231PS,"ymm1,ymm2,ymm3/mem256","C4 RXB.00010 0.src2.1.01 B7 /r");
		AddInstructionV(opVFMSUBADDPD,"xmm1,xmm2,xmm3/mem128,xmm4","C4 RXB.03 0.src1.0.01 5F /r /is4");
		AddInstructionV(opVFMSUBADDPD,"ymm1,ymm2,ymm3/mem256,ymm4","C4 RXB.03 0.src1.1.01 5F /r /is4");
		AddInstructionV(opVFMSUBADDPD,"xmm1,xmm2,xmm3,xmm4/mem128","C4 RXB.03 1.src1.0.01 5F /r /is4");
		AddInstructionV(opVFMSUBADDPD,"ymm1,ymm2,ymm3,ymm4/mem256","C4 RXB.03 1.src1.1.01 5F /r /is4");
		AddInstructionV(opVFMSUBADDPS,"xmm1,xmm2,xmm3/mem128,xmm4","C4 RXB.03 0.src1.0.01 5E /r /is4");
		AddInstructionV(opVFMSUBADDPS,"ymm1,ymm2,ymm3/mem256,ymm4","C4 RXB.03 0.src1.1.01 5E /r /is4");
		AddInstructionV(opVFMSUBADDPS,"xmm1,xmm2,xmm3,xmm4/mem128","C4 RXB.03 1.src1.0.01 5E /r /is4");
		AddInstructionV(opVFMSUBADDPS,"ymm1,ymm2,ymm3,ymm4/mem256","C4 RXB.03 1.src1.1.01 5E /r /is4");
		AddInstructionV(opVFMSUBPD,"xmm1,xmm2,xmm3/mem128,xmm4","C4 RXB.03 0.src1.0.01 6D /r /is4");
		AddInstructionV(opVFMSUBPD,"ymm1,ymm2,ymm3/mem256,ymm4","C4 RXB.03 0.src1.1.01 6D /r /is4");
		AddInstructionV(opVFMSUBPD,"xmm1,xmm2,xmm3,xmm4/mem128","C4 RXB.03 1.src1.0.01 6D /r /is4");
		AddInstructionV(opVFMSUBPD,"ymm1,ymm2,ymm3,ymm4/mem256","C4 RXB.03 1.src1.1.01 6D /r /is4");
		AddInstructionV(opVFMSUBPS,"xmm1,xmm2,xmm3/mem128,xmm4","C4 RXB.03 0.src1.0.01 6C /r /is4");
		AddInstructionV(opVFMSUBPS,"ymm1,ymm2,ymm3/mem256,ymm4","C4 RXB.03 0.src1.1.01 6C /r /is4");
		AddInstructionV(opVFMSUBPS,"xmm1,xmm2,xmm3,xmm4/mem128","C4 RXB.03 1.src1.0.01 6C /r /is4");
		AddInstructionV(opVFMSUBPS,"ymm1,ymm2,ymm3,ymm4/mem256","C4 RXB.03 1.src1.1.01 6C /r /is4");
		AddInstructionV(opVFMSUBSD,"xmm1,xmm2,xmm3/mem64,xmm4","C4 RXB.03 0.src1.X.01 6F /r /is4");
		AddInstructionV(opVFMSUBSD,"xmm1,xmm2,xmm3,xmm4/mem64","C4 RXB.03 1.src1.X.01 6F /r /is4");
		AddInstructionV(opVFMSUBSS,"xmm1,xmm2,xmm3/mem32,xmm4","C4 RXB.03 0.src1.X.01 6E /r /is4");
		AddInstructionV(opVFMSUBSS,"xmm1,xmm2,xmm3,xmm4/mem32","C4 RXB.03 1.src1.X.01 6E /r /is4");
		AddInstructionV(opVFNMADD132PD,"xmm1,xmm2,xmm3/mem128","C4 RXB.02 1.src2.0.01 9C /r");
		AddInstructionV(opVFNMADD132PD,"ymm1,ymm2,ymm3/mem256","C4 RXB.02 1.src2.1.01 9C /r");
		AddInstructionV(opVFNMADD132PS,"xmm1,xmm2,xmm3/mem128","C4 RXB.02 0.src2.0.01 9C /r");
		AddInstructionV(opVFNMADD132PS,"ymm1,ymm2,ymm3/mem256","C4 RXB.02 0.src2.1.01 9C /r");
		AddInstructionV(opVFNMADD132SD,"xmm1,xmm2,xmm3/mem64","C4 RXB.02 1.src2.X.01 9D /r");
		AddInstructionV(opVFNMADD132SS,"xmm1,xmm2,xmm3/mem32","C4 RXB.02 0.src2.X.01 9D /r");
		AddInstructionV(opVFNMADD213PD,"xmm1,xmm2,xmm3/mem128","C4 RXB.02 1.src2.0.01 AC /r");
		AddInstructionV(opVFNMADD213PD,"ymm1,ymm2,ymm3/mem256","C4 RXB.02 1.src2.1.01 AC /r");
		AddInstructionV(opVFNMADD213PS,"xmm1,xmm2,xmm3/mem128","C4 RXB.02 0.src2.0.01 AC /r");
		AddInstructionV(opVFNMADD213PS,"ymm1,ymm2,ymm3/mem256","C4 RXB.02 0.src2.1.01 AC /r");
		AddInstructionV(opVFNMADD213SD,"xmm1,xmm2,xmm3/mem64","C4 RXB.02 1.src2.X.01 AD /r");
		AddInstructionV(opVFNMADD213SS,"xmm1,xmm2,xmm3/mem32","C4 RXB.02 0.src2.X.01 AD /r");
		AddInstructionV(opVFNMADD231PD,"xmm1,xmm2,xmm3/mem128","C4 RXB.02 1.src2.0.01 BC /r");
		AddInstructionV(opVFNMADD231PD,"ymm1,ymm2,ymm3/mem256","C4 RXB.02 1.src2.1.01 BC /r");
		AddInstructionV(opVFNMADD231PS,"xmm1,xmm2,xmm3/mem128","C4 RXB.02 0.src2.0.01 BC /r");
		AddInstructionV(opVFNMADD231PS,"ymm1,ymm2,ymm3/mem256","C4 RXB.02 0.src2.1.01 BC /r");
		AddInstructionV(opVFNMADD231SD,"xmm1,xmm2,xmm3/mem64","C4 RXB.02 1.src2.X.01 BD /r");
		AddInstructionV(opVFNMADD231SS,"xmm1,xmm2,xmm3/mem32","C4 RXB.02 0.src2.X.01 BD /r");
		AddInstructionV(opVFNMADDPD,"xmm1,xmm2,xmm3/mem128,xmm4","C4 RXB.03 0.src1.0.01 79 /r /is4");
		AddInstructionV(opVFNMADDPD,"ymm1,ymm2,ymm3/mem256,ymm4","C4 RXB.03 0.src1.1.01 79 /r /is4");
		AddInstructionV(opVFNMADDPD,"xmm1,xmm2,xmm3,xmm4/mem128","C4 RXB.03 1.src1.0.01 79 /r /is4");
		AddInstructionV(opVFNMADDPD,"ymm1,ymm2,ymm3,ymm4/mem256","C4 RXB.03 1.src1.1.01 79 /r /is4");
		AddInstructionV(opVFNMADDPS,"xmm1,xmm2,xmm3/mem128,xmm4","C4 RXB.03 0.src1.0.01 78 /r /is4");
		AddInstructionV(opVFNMADDPS,"ymm1,ymm2,ymm3/mem256,ymm4","C4 RXB.03 0.src1.1.01 78 /r /is4");
		AddInstructionV(opVFNMADDPS,"xmm1,xmm2,xmm3,xmm4/mem128","C4 RXB.03 1.src1.0.01 78 /r /is4");
		AddInstructionV(opVFNMADDPS,"ymm1,ymm2,ymm3,ymm4/mem256","C4 RXB.03 1.src1.1.01 78 /r /is4");
		AddInstructionV(opVFNMADDSD,"xmm1,xmm2,xmm3/mem64,xmm4","C4 RXB.03 0.src1.X.01 7B /r /is4");
		AddInstructionV(opVFNMADDSD,"xmm1,xmm2,xmm3,xmm4/mem64","C4 RXB.03 1.src1.X.01 7B /r /is4");
		AddInstructionV(opVFNMADDSS,"xmm1,xmm2,xmm3/mem32,xmm4","C4 RXB.03 0.src1.X.01 7A /r /is4");
		AddInstructionV(opVFNMADDSS,"xmm1,xmm2,xmm3,xmm4/mem32","C4 RXB.03 1.src1.X.01 7A /r /is4");
		AddInstructionV(opVFNMSUB132PD,"xmm1,xmm2,xmm3/mem128","C4 RXB.02 1.src2.0.01 9E /r");
		AddInstructionV(opVFNMSUB132PD,"ymm1,ymm2,ymm3/mem256","C4 RXB.02 1.src2.1.01 9E /r");
		AddInstructionV(opVFNMSUB132PS,"xmm1,xmm2,xmm3/mem128","C4 RXB.02 0.src2.0.01 9E /r");
		AddInstructionV(opVFNMSUB132PS,"ymm1,ymm2,ymm3/mem256","C4 RXB.02 0.src2.1.01 9E /r");
		AddInstructionV(opVFNMSUB132SD,"xmm1,xmm2,xmm3/mem64","C4 RXB.02 1.src2.X.01 9F /r");
		AddInstructionV(opVFNMSUB132SS,"xmm1,xmm2,xmm3/mem32","C4 RXB.02 0.src2.X.01 9F /r");
		AddInstructionV(opVFNMSUB213PD,"xmm1,xmm2,xmm3/mem128","C4 RXB.02 1.src2.0.01 AE /r");
		AddInstructionV(opVFNMSUB213PD,"ymm1,ymm2,ymm3/mem256","C4 RXB.02 1.src2.1.01 AE /r");
		AddInstructionV(opVFNMSUB213PS,"xmm1,xmm2,xmm3/mem128","C4 RXB.02 0.src2.0.01 AE /r");
		AddInstructionV(opVFNMSUB213PS,"ymm1,ymm2,ymm3/mem256","C4 RXB.02 0.src2.1.01 AE /r");
		AddInstructionV(opVFNMSUB213SD,"xmm1,xmm2,xmm3/mem64","C4 RXB.02 1.src2.X.01 AF /r");
		AddInstructionV(opVFNMSUB213SS,"xmm1,xmm2,xmm3/mem32","C4 RXB.02 0.src2.X.01 AF /r");
		AddInstructionV(opVFNMSUB231PD,"xmm1,xmm2,xmm3/mem128","C4 RXB.02 1.src2.0.01 BE /r");
		AddInstructionV(opVFNMSUB231PD,"ymm1,ymm2,ymm3/mem256","C4 RXB.02 1.src2.1.01 BE /r");
		AddInstructionV(opVFNMSUB231PS,"xmm1,xmm2,xmm3/mem128","C4 RXB.02 0.src2.0.01 BE /r");
		AddInstructionV(opVFNMSUB231PS,"ymm1,ymm2,ymm3/mem256","C4 RXB.02 0.src2.1.01 BE /r");
		AddInstructionV(opVFNMSUB231SD,"xmm1,xmm2,xmm3/mem64","C4 RXB.02 1.src2.X.01 BF /r");
		AddInstructionV(opVFNMSUB231SS,"xmm1,xmm2,xmm3/mem32","C4 RXB.02 0.src2.X.01 BF /r");
		AddInstructionV(opVFNMSUBPD,"xmm1,xmm2,xmm3/mem128,xmm4","C4 RXB.03 0.src1.0.01 7D /r /is4");
		AddInstructionV(opVFNMSUBPD,"ymm1,ymm2,ymm3/mem256,ymm4","C4 RXB.03 0.src1.1.01 7D /r /is4");
		AddInstructionV(opVFNMSUBPD,"xmm1,xmm2,xmm3,xmm4/mem128","C4 RXB.03 1.src1.0.01 7D /r /is4");
		AddInstructionV(opVFNMSUBPD,"ymm1,ymm2,ymm3,ymm4/mem256","C4 RXB.03 1.src1.1.01 7D /r /is4");
		AddInstructionV(opVFNMSUBPS,"xmm1,xmm2,xmm3/mem128,xmm4","C4 RXB.03 0.src1.0.01 7C /r /is4");
		AddInstructionV(opVFNMSUBPS,"ymm1,ymm2,ymm3/mem256,ymm4","C4 RXB.03 0.src1.1.01 7C /r /is4");
		AddInstructionV(opVFNMSUBPS,"xmm1,xmm2,xmm3,xmm4/mem128","C4 RXB.03 1.src1.0.01 7C /r /is4");
		AddInstructionV(opVFNMSUBPS,"ymm1,ymm2,ymm3,ymm4/mem256","C4 RXB.03 1.src1.1.01 7C /r /is4");
		AddInstructionV(opVFNMSUBSD,"xmm1,xmm2,xmm3/mem64,xmm4","C4 RXB.03 0.src1.X.01 7F /r /is4");
		AddInstructionV(opVFNMSUBSD,"xmm1,xmm2,xmm3,xmm4/mem64","C4 RXB.03 1.src1.X.01 7F /r /is4");
		AddInstructionV(opVFNMSUBSS,"xmm1,xmm2,xmm3/mem32,xmm4","C4 RXB.03 0.src1.X.01 7E /r /is4");
		AddInstructionV(opVFNMSUBSS,"xmm1,xmm2,xmm3,xmm4/mem32","C4 RXB.03 1.src1.X.01 7E /r /is4");
		AddInstructionV(opVFRCZPD,"xmm1,xmm2/mem128","8F RXB.09 0.1111.0.00 81 /r");
		AddInstructionV(opVFRCZPD,"ymm1,ymm2/mem256","8F RXB.09 0.1111.1.00 81 /r");
		AddInstructionV(opVFRCZPS,"xmm1,xmm2/mem128","8F RXB.09 0.1111.0.00 80 /r");
		AddInstructionV(opVFRCZPS,"ymm1,ymm2/mem256","8F RXB.09 0.1111.1.00 80 /r");
		AddInstructionV(opVFRCZSD,"xmm1,xmm2/mem64","8F RXB.09 0.1111.0.00 83 /r");
		AddInstructionV(opVFRCZSS,"xmm1,xmm2/mem32","8F RXB.09 0.1111.0.00 82 /r");
		AddInstructionV(opVGATHERDPD,"xmm1,vm32x,xmm2","C4 RXB.02 1.src2.0.01 92 /r");
		AddInstructionV(opVGATHERDPD,"ymm1,vm32x,ymm2","C4 RXB.02 1.src2.1.01 92 /r");
		AddInstructionV(opVGATHERDPS,"xmm1,vm32x,xmm2","C4 RXB.02 0.src2.0.01 92 /r");
		AddInstructionV(opVGATHERDPS,"ymm1,vm32y,ymm2","C4 RXB.02 0.src2.1.01 92 /r");
		AddInstructionV(opVGATHERQPD,"xmm1,vm64x,xmm2","C4 RXB.02 1.src2.0.01 93 /r");
		AddInstructionV(opVGATHERQPD,"ymm1,vm64y,ymm2","C4 RXB.02 1.src2.1.01 93 /r");
		AddInstructionV(opVGATHERQPS,"xmm1,vm64x,xmm2","C4 RXB.02 0.src2.0.01 93 /r");
		AddInstructionV(opVGATHERQPS,"xmm1,vm64y,xmm2","C4 RXB.02 0.src2.1.01 93 /r");
		AddInstructionV(opVHADDPD,"xmm1,xmm2,xmm3/mem128","C4 RXB.00001 X.src.0.01 7C /r");
		AddInstructionV(opVHADDPD,"ymm1,ymm2,ymm3/mem256","C4 RXB.00001 X.src.1.01 7C /r");
		AddInstructionV(opVHADDPS,"xmm1,xmm2,xmm3/mem128","C4 RXB.00001 X.src.0.11 7C /r");
		AddInstructionV(opVHADDPS,"ymm1,ymm2,ymm3/mem256","C4 RXB.00001 X.src.1.11 7C /r");
		AddInstructionV(opVHSUBPD,"xmm1,xmm2,xmm3/mem128","C4 RXB.00001 X.src.0.01 7D /r");
		AddInstructionV(opVHSUBPD,"ymm1,ymm2,ymm3/mem256","C4 RXB.00001 X.src.1.01 7D /r");
		AddInstructionV(opVHSUBPS,"xmm1,xmm2,xmm3/mem128","C4 RXB.00001 X.src.0.11 7D /r");
		AddInstructionV(opVHSUBPS,"ymm1,ymm2,ymm3/mem256","C4 RXB.00001 X.src.1.11 7D /r");
		AddInstructionV(opVINSERTF128,"ymm1,ymm2,xmm3/mem128,imm8","C4 RXB.03 0.src.1.01 18 /r ib");
		AddInstructionV(opVINSERTI128,"ymm1,ymm2,xmm3/mem128,imm8","C4 RXB.03 0.src1.1.01 38 /r ib");
		AddInstructionV(opVINSERTPS,"xmm1,xmm2,xmm3/mem128,imm8","C4 RXB.00011 X.src.0.01 21 /r ib");
		AddInstructionV(opVLDDQU,"xmm1,mem128","C4 RXB.00001 X.1111.0.11 F0 /r");
		AddInstructionV(opVLDDQU,"ymm1,mem256","C4 RXB.00001 X.1111.1.11 F0 /r");
		AddInstructionV(opVLDMXCSR,"mem32","C4 RXB.00001 X.1111.0.00 AE /2");
		AddInstructionV(opVMASKMOVDQU,"xmm1,xmm2","C4 RXB.00001 X.1111.0.01 F7 /r");
		AddInstructionV(opVMASKMOVPD,"xmm1,xmm2,mem128","C4 RXB.02 0.src1.0.01 2D /r");
		AddInstructionV(opVMASKMOVPD,"ymm1,ymm2,mem256","C4 RXB.02 0.src1.1.01 2D /r");
		AddInstructionV(opVMASKMOVPD,"mem128,xmm1,xmm2","C4 RXB.02 0.src1.0.01 2F /r");
		AddInstructionV(opVMASKMOVPD,"mem256,ymm1,ymm2","C4 RXB.02 0.src1.1.01 2F /r");
		AddInstructionV(opVMASKMOVPS,"xmm1,xmm2,mem128","C4 RXB.02 0.src1.0.01 2C /r");
		AddInstructionV(opVMASKMOVPS,"ymm1,ymm2,mem256","C4 RXB.02 0.src1.1.01 2C /r");
		AddInstructionV(opVMASKMOVPS,"mem128,xmm1,xmm2","C4 RXB.02 0.src1.0.01 2E /r");
		AddInstructionV(opVMASKMOVPS,"mem256,ymm1,ymm2","C4 RXB.02 0.src1.1.01 2E /r");
		AddInstructionV(opVMAXPD,"xmm1,xmm2,xmm3/mem128","C4 RXB.00001 X.src.0.01 5F /r");
		AddInstructionV(opVMAXPD,"ymm1,ymm2,ymm3/mem256","C4 RXB.00001 X.src.1.01 5F /r");
		AddInstructionV(opVMAXPS,"xmm1,xmm2,xmm3/mem128","C4 RXB.00001 X.src.0.00 5F /r");
		AddInstructionV(opVMAXPS,"ymm1,ymm2,ymm3/mem256","C4 RXB.00001 X.src.1.00 5F /r");
		AddInstructionV(opVMAXSD,"xmm1,xmm2,xmm3/mem64","C4 RXB.00001 X.src.X.11 5F /r");
		AddInstructionV(opVMAXSS,"xmm1,xmm2,xmm3/mem32","C4 RXB.00001 X.src.X.10 5F /r");
		AddInstructionV(opVMINPD,"xmm1,xmm2,xmm3/mem128","C4 RXB.00001 X.src.0.01 5D /r");
		AddInstructionV(opVMINPD,"ymm1,ymm2,ymm3/mem256","C4 RXB.00001 X.src.1.01 5D /r");
		AddInstructionV(opVMINPS,"xmm1,xmm2,xmm3/mem128","C4 RXB.00001 X.src.0.00 5D /r");
		AddInstructionV(opVMINPS,"ymm1,ymm2,ymm3/mem256","C4 RXB.00001 X.src.1.00 5D /r");
		AddInstructionV(opVMINSD,"xmm1,xmm2,xmm3/mem64","C4 RXB.00001 X.src.X.11 5D /r");
		AddInstructionV(opVMINSS,"xmm1,xmm2,xmm3/mem32","C4 RXB.00001 X.src.X.10 5D /r");
		AddInstructionV(opVMOVAPD,"xmm1,xmm2/mem128","C4 RXB.00001 X.1111.0.01 28 /r");
		AddInstructionV(opVMOVAPD,"xmm1/mem128,xmm2","C4 RXB.00001 X.1111.0.01 29 /r");
		AddInstructionV(opVMOVAPD,"ymm1,ymm2/mem256","C4 RXB.00001 X.1111.1.01 28 /r");
		AddInstructionV(opVMOVAPD,"ymm1/mem256,ymm2","C4 RXB.00001 X.1111.1.01 29 /r");
		AddInstructionV(opVMOVAPS,"xmm1,xmm2/mem128","C4 RXB.00001 X.1111.0.00 28 /r");
		AddInstructionV(opVMOVAPS,"xmm1/mem128,xmm2","C4 RXB.00001 X.1111.0.00 29 /r");
		AddInstructionV(opVMOVAPS,"ymm1,ymm2/mem256","C4 RXB.00001 X.1111.1.00 28 /r");
		AddInstructionV(opVMOVAPS,"ymm1/mem256,ymm2","C4 RXB.00001 X.1111.1.00 29 /r");
		AddInstructionV(opVMOVD,"xmm,reg32/mem32","C4 RXB.00001 0.1111.0.01 6E /r");
		AddInstructionV(opVMOVD,"reg32/mem32,xmm","C4 RXB.00001 0.1111.0.01 7E /r");
		AddInstructionV(opVMOVDQA,"xmm1,xmm2/mem128","C4 RXB.00001 X.1111.0.01 6F /r");
		AddInstructionV(opVMOVDQA,"xmm1/mem128,xmm2","C4 RXB.00001 X.1111.0.01 6F /r");
		AddInstructionV(opVMOVDQA,"ymm1,xmm2/mem256","C4 RXB.00001 X.1111.1.01 7F /r");
		AddInstructionV(opVMOVDQA,"ymm1/mem256,ymm2","C4 RXB.00001 X.1111.1.01 7F /r");
		AddInstructionV(opVMOVDQU,"xmm1,xmm2/mem128","C4 RXB.00001 X.1111.0.10 6F /r");
		AddInstructionV(opVMOVDQU,"xmm1/mem128,xmm2","C4 RXB.00001 X.1111.0.10 6F /r");
		AddInstructionV(opVMOVDQU,"ymm1,xmm2/mem256","C4 RXB.00001 X.1111.1.10 7F /r");
		AddInstructionV(opVMOVDQU,"ymm1/mem256,ymm2","C4 RXB.00001 X.1111.1.10 7F /r");
		AddInstructionV(opVMOVHLPS,"xmm1,xmm2,xmm3","C4 RXB.00001 X.src.0.00 12 /r");
		AddInstructionV(opVMOVHPD,"xmm1,xmm2,mem64","C4 RXB.00001 X.src.0.01 16 /r");
		AddInstructionV(opVMOVHPD,"mem64,xmm1","C4 RXB.00001 X.1111.0.01 17 /r");
		AddInstructionV(opVMOVHPS,"xmm1,xmm2,mem64","C4 RXB.00001 X.src.0.00 16 /r");
		AddInstructionV(opVMOVHPS,"mem64,xmm1","C4 RXB.00001 X.1111.0.00 17 /r");
		AddInstructionV(opVMOVLHPS,"xmm1,xmm2,xmm3","C4 RXB.00001 X.src.0.00 16 /r");
		AddInstructionV(opVMOVLPD,"xmm1,xmm2,mem64","C4 RXB.00001 X.src.0.01 12 /r");
		AddInstructionV(opVMOVLPD,"mem64,xmm1","C4 RXB.00001 X.1111.0.01 13 /r");
		AddInstructionV(opVMOVLPS,"xmm1,xmm2,mem64","C4 RXB.00001 X.src.0.00 12 /r");
		AddInstructionV(opVMOVLPS,"mem64,xmm1","C4 RXB.00001 X.1111.0.00 13 /r");
		AddInstructionV(opVPMOVMSKB,"reg64,xmm1","C4 RXB.01 X.1111.0.01 D7 /r");
		AddInstructionV(opVPMOVMSKB,"reg64,ymm1","C4 RXB.01 X.1111.1.01 D7 /r");
		AddInstructionV(opVMOVMSKPD,"reg,xmm","C4 RXB.00001 X.1111.0.01 50 /r");
		AddInstructionV(opVMOVMSKPD,"reg,ymm","C4 RXB.00001 X.1111.1.01 50 /r");
		AddInstructionV(opVMOVMSKPS,"reg,xmm","C4 RXB.00001 X.1111.0.00 50 /r");
		AddInstructionV(opVMOVMSKPS,"reg,ymm","C4 RXB.00001 X.1111.1.00 50 /r");
		AddInstructionV(opVMOVNTDQ,"mem128,xmm","C4 RXB.00001 X.1111.0.01 E7 /r");
		AddInstructionV(opVMOVNTDQ,"mem256,ymm","C4 RXB.00001 X.1111.1.01 E7 /r");
		AddInstructionV(opVMOVNTDQA,"xmm,mem128","C4 RXB.02 X.1111.0.01 2A /r");
		AddInstructionV(opVMOVNTDQA,"ymm,mem256","C4 RXB.02 X.1111.1.01 2A /r");
		AddInstructionV(opVMOVNTPD,"mem128,xmm","C4 RXB.00001 X.1111.0.01 2B /r");
		AddInstructionV(opVMOVNTPD,"mem256,ymm","C4 RXB.00001 X.1111.1.01 2B /r");
		AddInstructionV(opVMOVNTPS,"mem128,xmm","C4 RXB.00001 X.1111.0.00 2B /r");
		AddInstructionV(opVMOVNTPS,"mem256,ymm","C4 RXB.00001 X.1111.1.00 2B /r");
		AddInstructionV(opVMOVQ,"xmm,reg64/mem64","C4 RXB.00001 1.1111.0.01 6E /r");
		AddInstructionV(opVMOVQ,"reg64/mem64,xmm","C4 RXB.00001 1.1111.0.01 7E /r");
		AddInstructionV(opVMOVQ,"xmm1,xmm2/mem64","C4 RXB.00001 X.1111.0.10 7E /r");
		AddInstructionV(opVMOVQ,"xmm1/mem64,xmm2","C4 RXB.00001 X.1111.0.01 D6 /r");
		AddInstructionV(opVMOVSD,"xmm1,mem64","C4 RXB.00001 X.1111.X.11 10 /r");
		AddInstructionV(opVMOVSD,"mem64,xmm1","C4 RXB.00001 X.1111.X.11 11 /r");
		AddInstructionV(opVMOVSD,"xmm1,xmm2,xmm3","C4 RXB.00001 X.src.X.11 10 /r");
		AddInstructionV(opVMOVSD,"xmm1,xmm2,xmm3","C4 RXB.00001 X.src.X.11 11 /r");
		AddInstructionV(opVMOVSHDUP,"xmm1,xmm2/mem128","C4 RXB.00001 X.1111.0.10 16 /r");
		AddInstructionV(opVMOVSHDUP,"ymm1,ymm2/mem256","C4 RXB.00001 X.1111.1.10 16 /r");
		AddInstructionV(opVMOVSLDUP,"xmm1,xmm2/mem128","C4 RXB.00001 X.1111.0.10 12 /r");
		AddInstructionV(opVMOVSLDUP,"ymm1,ymm2/mem256","C4 RXB.00001 X.1111.1.10 12 /r");
		AddInstructionV(opVMOVSS,"xmm1,mem32","C4 RXB.00001 X.1111.X.10 10 /r");
		AddInstructionV(opVMOVSS,"mem32,xmm1","C4 RXB.00001 X.1111.X.10 11 /r");
		AddInstructionV(opVMOVSS,"xmm1,xmm2,xmm3","C4 RXB.00001 X.src.X.10 10 /r");
		AddInstructionV(opVMOVSS,"xmm1,xmm2,xmm3","C4 RXB.00001 X.src.X.10 11 /r");
		AddInstructionV(opVMOVUPD,"xmm1,xmm2/mem128","C4 RXB.00001 X.1111.0.01 10 /r");
		AddInstructionV(opVMOVUPD,"xmm1/mem128,xmm2","C4 RXB.00001 X.1111.0.01 11 /r");
		AddInstructionV(opVMOVUPD,"ymm1,ymm2/mem256","C4 RXB.00001 X.1111.1.01 10 /r");
		AddInstructionV(opVMOVUPD,"ymm1/mem256,ymm2","C4 RXB.00001 X.1111.1.01 11 /r");
		AddInstructionV(opVMOVUPS,"xmm1,xmm2/mem128","C4 RXB.00001 X.1111.0.00 10 /r");
		AddInstructionV(opVMOVUPS,"xmm1/mem128,xmm2","C4 RXB.00001 X.1111.0.00 11 /r");
		AddInstructionV(opVMOVUPS,"ymm1,ymm2/mem256","C4 RXB.00001 X.1111.1.00 10 /r");
		AddInstructionV(opVMOVUPS,"ymm1/mem256,ymm2","C4 RXB.00001 X.1111.1.00 11 /r");
		AddInstructionV(opVMPSADBW,"xmm1,xmm2,xmm3/mem128,imm8","C4 RXB.03 X.src1.0.01 42 /r ib");
		AddInstructionV(opVMPSADBW,"ymm1,ymm2,ymm3/mem256,imm8","C4 RXB.03 X.src1.1.01 42 /r ib");
		AddInstructionV(opVMULPD,"xmm1,xmm2,xmm3/mem128","C4 RXB.01 X.src.0.01 59 /r");
		AddInstructionV(opVMULPD,"ymm1,ymm2,ymm3/mem256","C4 RXB.01 X.src.1.01 59 /r");
		AddInstructionV(opVMULPS,"xmm1,xmm2,xmm3/mem128","C4 RXB.01 X.src1.0.00 59 /r");
		AddInstructionV(opVMULPS,"ymm1,ymm2,ymm3/mem256","C4 RXB.01 X.src1.1.00 59 /r");
		AddInstructionV(opVMULSD,"xmm1,xmm2,xmm3/mem64","C4 RXB.01 X.src1.X.11 59 /r");
		AddInstructionV(opVMULSS,"xmm1,xmm2,xmm3/mem32","C4 RXB.01 X.src1.X.10 59 /r");
		AddInstructionV(opVORPD,"xmm1,xmm2,xmm3/mem128","C4 RXB.01 X.src1.0.01 56 /r");
		AddInstructionV(opVORPD,"ymm1,ymm2,ymm3/mem256","C4 RXB.01 X.src1.1.01 56 /r");
		AddInstructionV(opVORPS,"xmm1,xmm2,xmm3/mem128","C4 RXB.01 X.src1.0.00 56 /r");
		AddInstructionV(opVORPS,"ymm1,ymm2,ymm3/mem256","C4 RXB.01 X.src1.1.00 56 /r");
		AddInstructionV(opVPABSB,"xmm1,xmm2/mem128","C4 RXB.02 X.1111.0.01 1C /r");
		AddInstructionV(opVPABSB,"ymm1,ymm2/mem256","C4 RXB.02 X.1111.1.01 1C /r");
		AddInstructionV(opVPABSD,"xmm1,xmm2/mem128","C4 RXB.02 X.1111.0.01 1E /r");
		AddInstructionV(opVPABSD,"ymm1,ymm2/mem256","C4 RXB.02 X.1111.1.01 1E /r");
		AddInstructionV(opVPABSW,"xmm1,xmm2/mem128","C4 RXB.02 X.1111.0.01 1D /r");
		AddInstructionV(opVPABSW,"ymm1,ymm2/mem256","C4 RXB.02 X.1111.1.01 1D /r");
		AddInstructionV(opVPACKSSDW,"xmm1,xmm2,xmm3/mem128","C4 RXB.01 X.src1.0.01 6B /r");
		AddInstructionV(opVPACKSSDW,"ymm1,ymm2,ymm3/mem256","C4 RXB.01 X.src1.1.01 6B /r");
		AddInstructionV(opVPACKSSWB,"xmm1,xmm2,xmm3/mem128","C4 RXB.01 X.src1.0.01 63 /r");
		AddInstructionV(opVPACKSSWB,"ymm1,ymm2,ymm3/mem256","C4 RXB.01 X.src1.1.01 63 /r");
		AddInstructionV(opVPACKUSDW,"xmm1,xmm2,xmm3/mem128","C4 RXB.02 X.src1.0.01 2B /r");
		AddInstructionV(opVPACKUSDW,"ymm1,ymm2,ymm3/mem256","C4 RXB.02 X.src1.0.01 2B /r");
		AddInstructionV(opVPACKUSWB,"xmm1,xmm2,xmm3/mem128","C4 RXB.01 X.src1.0.01 67 /r");
		AddInstructionV(opVPACKUSWB,"ymm1,ymm2,ymm3/mem256","C4 RXB.01 X.src1.1.01 67 /r");
		AddInstructionV(opVPADDB,"xmm1,xmm2,xmm3/mem128","C4 RXB.01 X.src1.0.01 FC /r");
		AddInstructionV(opVPADDB,"ymm1,ymm2,ymm3/mem256","C4 RXB.01 X.src1.1.01 FC /r");
		AddInstructionV(opVPADDD,"xmm1,xmm2,xmm3/mem128","C4 RXB.01 X.src1.0.01 FE /r");
		AddInstructionV(opVPADDD,"ymm1,ymm2,ymm3/mem256","C4 RXB.01 X.src1.1.01 FE /r");
		AddInstructionV(opVPADDQ,"xmm1,xmm2,xmm3/mem128","C4 RXB.00001 X.src1.0.01 D4 /r");
		AddInstructionV(opVPADDQ,"ymm1,ymm2,ymm3/mem256","C4 RXB.00001 X.src1.1.01 D4 /r");
		AddInstructionV(opVPADDSB,"xmm1,xmm2,xmm3/mem128","C4 RXB.01 X.src1.0.01 EC /r");
		AddInstructionV(opVPADDSB,"ymm1,ymm2,ymm3/mem256","C4 RXB.01 X.src1.1.01 EC /r");
		AddInstructionV(opVPADDSW,"xmm1,xmm2,xmm3/mem128","C4 RXB.00001 X.src1.0.01 ED /r");
		AddInstructionV(opVPADDSW,"ymm1,ymm2,ymm3/mem256","C4 RXB.00001 X.src1.1.01 ED /r");
		AddInstructionV(opVPADDUSB,"xmm1,xmm2,xmm3/mem128","C4 RXB.01 X.src1.0.01 DC /r");
		AddInstructionV(opVPADDUSB,"ymm1,ymm2,ymm3/mem256","C4 RXB.01 X.src1.1.01 DC /r");
		AddInstructionV(opVPADDUSW,"xmm1,xmm2,xmm3/mem128","C4 RXB.01 X.src1.0.01 DD /r");
		AddInstructionV(opVPADDUSW,"ymm1,ymm2,ymm3/mem256","C4 RXB.01 X.src1.1.01 DD /r");
		AddInstructionV(opVPADDW,"xmm1,xmm2,xmm3/mem128","C4 RXB.01 X.src1.0.01 FD /r");
		AddInstructionV(opVPADDW,"ymm1,ymm2,ymm3/mem256","C4 RXB.01 X.src1.1.01 FD /r");
		AddInstructionV(opVPALIGNR,"xmm1,xmm2,xmm3/mem128,imm8","C4 RXB.03 X.src1.0.01 0F /r ib");
		AddInstructionV(opVPALIGNR,"ymm1,ymm2,ymm3/mem256,imm8","C4 RXB.03 X.src1.1.01 0F /r ib");
		AddInstructionV(opVPAND,"xmm1,xmm2,xmm3/mem128","C4 RXB.01 X.src1.0.01 DB /r");
		AddInstructionV(opVPAND,"ymm1,ymm2,ymm3/mem256","C4 RXB.01 X.src1.1.01 DB /r");
		AddInstructionV(opVPANDN,"xmm1,xmm2,xmm3/mem128","C4 RXB.01 X.src.0.01 DF /r");
		AddInstructionV(opVPANDN,"ymm1,ymm2,ymm3/mem256","C4 RXB.01 X.src.1.01 DF /r");
		AddInstructionV(opVPAVGB,"xmm1,xmm2,xmm3/mem128","C4 RXB.01 X.src1.0.01 E0 /r");
		AddInstructionV(opVPAVGB,"ymm1,ymm2,ymm3/mem256","C4 RXB.01 X.src1.1.01 E0 /r");
		AddInstructionV(opVPAVGW,"xmm1,xmm2,xmm3/mem128","C4 RXB.01 X.src1.0.01 E3 /r");
		AddInstructionV(opVPAVGW,"ymm1,ymm2,ymm3/mem256","C4 RXB.01 X.src1.1.01 E3 /r");
		AddInstructionV(opVPBLENDD,"xmm1,xmm2,xmm3/mem128,imm8","C4 RXB.03 0.src1.0.01 02 /r /ib");
		AddInstructionV(opVPBLENDD,"ymm1,ymm2,ymm3/mem256,imm8","C4 RXB.03 0.src1.1.01 02 /r /ib");
		AddInstructionV(opVPBLENDVB,"xmm1,xmm2,xmm3/mem128,xmm4","C4 RXB.03 0.src1.0.01 4C /r is4");
		AddInstructionV(opVPBLENDVB,"ymm1,ymm2,ymm3/mem256,ymm4","C4 RXB.03 0.src1.1.01 4C /r is4");
		AddInstructionV(opVPBLENDW,"xmm1,xmm2,xmm3/mem128,imm8","C4 RXB.03 X.src1.0.01 0E /r /ib");
		AddInstructionV(opVPBLENDW,"ymm1,ymm2,ymm3/mem256,imm8","C4 RXB.03 X.src1.1.01 0E /r /ib");
		AddInstructionV(opVPBROADCASTB,"xmm1,xmm2/mem8","C4 RXB.02 0.1111.0.01 78 /r");
		AddInstructionV(opVPBROADCASTB,"ymm1,xmm2/mem8","C4 RXB.02 0.1111.1.01 78 /r");
		AddInstructionV(opVPBROADCASTD,"xmm1,xmm2/mem32","C4 RXB.02 0.1111.0.01 58 /r");
		AddInstructionV(opVPBROADCASTD,"ymm1,xmm2/mem32","C4 RXB.02 0.1111.1.01 58 /r");
		AddInstructionV(opVPBROADCASTQ,"xmm1,xmm2/mem64","C4 RXB.02 0.1111.0.01 59 /r");
		AddInstructionV(opVPBROADCASTQ,"ymm1,xmm2/mem64","C4 RXB.02 0.1111.1.01 59 /r");
		AddInstructionV(opVPBROADCASTW,"xmm1,xmm2/mem16","C4 RXB.02 0.1111.0.01 79 /r");
		AddInstructionV(opVPBROADCASTW,"ymm1,xmm2/mem16","C4 RXB.02 0.1111.1.01 79 /r");
		AddInstructionV(opVPCLMULQDQ,"xmm1,xmm2,xmm3/mem128,imm8","C4 RXB.00011 X.src.0.01 44 /r ib");
		AddInstructionV(opVPCMOV,"xmm1,xmm2,xmm3/mem128,xmm4","8F RXB.08 0.src1.0.00 A2 /r ib");
		AddInstructionV(opVPCMOV,"ymm1,ymm2,ymm3/mem256,ymm4","8F RXB.08 0.src1.1.00 A2 /r ib");
		AddInstructionV(opVPCMOV,"xmm1,xmm2,xmm3,xmm4/mem128","8F RXB.08 1.src1.0.00 A2 /r ib");
		AddInstructionV(opVPCMOV,"ymm1,ymm2,ymm3,ymm4/mem256","8F RXB.08 1.src1.1.00 A2 /r ib");
		AddInstructionV(opVPCMPEQB,"xmm1,xmm2,xmm3/mem128","C4 RXB.01 X.src1.0.01 74 /r");
		AddInstructionV(opVPCMPEQB,"ymm1,ymm2,ymm3/mem256","C4 RXB.01 X.src1.1.01 74 /r");
		AddInstructionV(opVPCMPEQD,"xmm1,xmm2,xmm3/mem128","C4 RXB.01 X.src1.0.01 76 /r");
		AddInstructionV(opVPCMPEQD,"ymm1,ymm2,ymm3/mem256","C4 RXB.01 X.src1.1.01 76 /r");
		AddInstructionV(opVPCMPEQQ,"xmm1,xmm2,xmm3/mem128","C4 RXB.02 X.src1.0.01 29 /r");
		AddInstructionV(opVPCMPEQQ,"ymm1,ymm2,ymm3/mem256","C4 RXB.02 X.src1.1.01 29 /r");
		AddInstructionV(opVPCMPEQW,"xmm1,xmm2,xmm3/mem128","C4 RXB.01 X.src1.0.01 75 /r");
		AddInstructionV(opVPCMPEQW,"ymm1,ymm2,ymm3/mem256","C4 RXB.01 X.src1.1.01 75 /r");
		AddInstructionV(opVPCMPESTRI,"xmm1,xmm2/mem128,imm8","C4 RXB.00011 X.1111.0.01 61 /r ib");
		AddInstructionV(opVPCMPESTRM,"xmm1,xmm2/mem128,imm8","C4 RXB.00011 X.1111.0.01 60 /r ib");
		AddInstructionV(opVPCMPGTB,"xmm1,xmm2,xmm3/mem128","C4 RXB.01 X.src1.0.01 64 /r");
		AddInstructionV(opVPCMPGTB,"ymm1,ymm2,ymm3/mem256","C4 RXB.01 X.src1.1.01 64 /r");
		AddInstructionV(opVPCMPGTD,"xmm1,xmm2,xmm3/mem128","C4 RXB.01 X.src1.0.01 66 /r");
		AddInstructionV(opVPCMPGTD,"ymm1,ymm2,ymm3/mem256","C4 RXB.01 X.src1.1.01 66 /r");
		AddInstructionV(opVPCMPGTQ,"xmm1,xmm2,xmm3/mem128","C4 RXB.02 X.src1.0.01 37 /r");
		AddInstructionV(opVPCMPGTQ,"ymm1,ymm2,ymm3/mem256","C4 RXB.02 X.src1.1.01 37 /r");
		AddInstructionV(opVPCMPGTW,"xmm1,xmm2,xmm3/mem128","C4 RXB.01 X.src1.0.01 65 /r");
		AddInstructionV(opVPCMPGTW,"ymm1,ymm2,ymm3/mem256","C4 RXB.01 X.src1.1.01 65 /r");
		AddInstructionV(opVPCMPISTRI,"xmm1,xmm2/mem128,imm8","C4 RXB.03 X.1111.0.01 63 /r ib");
		AddInstructionV(opVPCMPISTRM,"xmm1,xmm2/mem128,imm8","C4 RXB.03 X.1111.0.01 62 /r ib");
		AddInstructionV(opVPCOMB,"xmm1,xmm2,xmm3/mem128,imm8","8F RXB.08 0.src1.0.00 CC /r ib");
		AddInstructionV(opVPCOMD,"xmm1,xmm2,xmm3/mem128,imm8","8F RXB.08 0.src1.0.00 CE /r ib");
		AddInstructionV(opVPCOMQ,"xmm1,xmm2,xmm3/mem128,imm8","8F RXB.08 0.src1.0.00 CF /r ib");
		AddInstructionV(opVPCOMUB,"xmm1,xmm2,xmm3/mem128,imm8","8F RXB.08 0.src1.0.00 EC /r ib");
		AddInstructionV(opVPCOMUD,"xmm1,xmm2,xmm3/mem128,imm8","8F RXB.08 0.src1.0.00 EE /r ib");
		AddInstructionV(opVPCOMUQ,"xmm1,xmm2,xmm3/mem128,imm8","8F RXB.08 0.src1.0.00 EF /r ib");
		AddInstructionV(opVPCOMUW,"xmm1,xmm2,xmm3/mem128,imm8","8F RXB.08 0.src1.0.00 ED /r ib");
		AddInstructionV(opVPCOMW,"xmm1,xmm2,xmm3/mem128,imm8","8F RXB.08 0.src1.0.00 CD /r ib");
		AddInstructionV(opVPERM2F128,"ymm1,ymm2,ymm3/mem256,imm8","C4 RXB.03 0.src1.1.01 06 /r ib");
		AddInstructionV(opVPERM2I128,"ymm1,ymm2,ymm3/mem256,imm8","C4 RXB.03 0.src1.1.01 46 /r ib");
		AddInstructionV(opVPERMD,"ymm1,ymm2,ymm3/mem256","C4 RXB.02 0.src1.1.01 36 /r");
		AddInstructionV(opVPERMIL2PD,"xmm1,xmm2,xmm3/mem128,xmm4,m2z","C4 RXB.03 0.src1.0.01 49 /r is5");
		AddInstructionV(opVPERMIL2PD,"xmm1,xmm2,xmm3,xmm4/mem128,m2z","C4 RXB.03 1.src1.0.01 49 /r is5");
		AddInstructionV(opVPERMIL2PD,"ymm1,ymm2,ymm3/mem256,ymm4,m2z","C4 RXB.03 0.src1.1.01 49 /r is5");
		AddInstructionV(opVPERMIL2PD,"ymm1,ymm2,ymm3,ymm4/mem256,m2z","C4 RXB.03 1.src1.1.01 49 /r is5");
		AddInstructionV(opVPERMIL2PS,"xmm1,xmm2,xmm3/mem128,xmm4,m2z","C4 RXB.03 0.src1.0.01 48 /r is5");
		AddInstructionV(opVPERMIL2PS,"xmm1,xmm2,xmm3,xmm4/mem128,m2z","C4 RXB.03 1.src1.0.01 48 /r is5");
		AddInstructionV(opVPERMIL2PS,"ymm1,ymm2,ymm3/mem256,ymm4,m2z","C4 RXB.03 0.src1.1.01 48 /r is5");
		AddInstructionV(opVPERMIL2PS,"ymm1,ymm2,ymm3,ymm4/mem256,m2z","C4 RXB.03 1.src1.1.01 48 /r is5");
		AddInstructionV(opVPERMILPD,"xmm1,xmm2,xmm3/mem128","C4 RXB.02 0.src1.0.01 0D /r");
		AddInstructionV(opVPERMILPD,"ymm1,ymm2,ymm3/mem256","C4 RXB.02 0.src1.1.01 0D /r");
		AddInstructionV(opVPERMILPD,"xmm1,xmm2/mem128,imm8","C4 RXB.03 0.1111.0.01 05 /r ib");
		AddInstructionV(opVPERMILPD,"ymm1,ymm2/mem256,imm8","C4 RXB.03 0.1111.1.01 05 /r ib");
		AddInstructionV(opVPERMILPS,"xmm1,xmm2,xmm3/mem128","C4 RXB.02 0.src1.0.01 0C /r");
		AddInstructionV(opVPERMILPS,"ymm1,ymm2,ymm3/mem256","C4 RXB.02 0.src1.1.01 0C /r");
		AddInstructionV(opVPERMILPS,"xmm1,xmm2/mem128,imm8","C4 RXB.03 0.1111.0.01 04 /r ib");
		AddInstructionV(opVPERMILPS,"ymm1,ymm2/mem256,imm8","C4 RXB.03 0.1111.1.01 04 /r ib");
		AddInstructionV(opVPERMPD,"ymm1,ymm2/mem256,imm8","C4 RXB.03 1.1111.1.01 01 /r ib");
		AddInstructionV(opVPERMPS,"ymm1,ymm2,ymm3/mem256","C4 RXB.02 0.src1.1.01 16 /r");
		AddInstructionV(opVPERMQ,"ymm1,ymm2/mem256,imm8","C4 RXB.03 1.1111.1.01 00 /r ib");
		AddInstructionV(opVPEXTRB,"reg/mem8,xmm,imm8","C4 RXB.03 X.1111.0.01 14 /r ib");
		AddInstructionV(opVPEXTRD,"reg32/mem32,xmm,imm8","C4 RXB.03 0.1111.0.01 16 /r ib");
		AddInstructionV(opVPEXTRQ,"reg64/mem64,xmm,imm8","C4 RXB.03 1.1111.0.01 16 /r ib");
		AddInstructionV(opVPEXTRW,"reg,xmm,imm8","C4 RXB.01 X.1111.0.01 C5 /r ib");
		AddInstructionV(opVPEXTRW,"reg/mem16,xmm,imm8","C4 RXB.03 X.1111.0.01 15 /r ib");
		AddInstructionV(opVPGATHERDD,"xmm1,vm32x,xmm2","C4 RXB.02 0.src2.0.01 90 /r");
		AddInstructionV(opVPGATHERDD,"ymm1,vm32y,ymm2","C4 RXB.02 0.src2.1.01 90 /r");
		AddInstructionV(opVPGATHERDQ,"xmm1,vm32x,xmm2","C4 RXB.02 1.src2.0.01 90 /r");
		AddInstructionV(opVPGATHERDQ,"ymm1,vm32x,ymm2","C4 RXB.02 1.src2.1.01 90 /r");
		AddInstructionV(opVPGATHERQD,"xmm1,vm64x,xmm2","C4 RXB.02 0.src2.0.01 91 /r");
		AddInstructionV(opVPGATHERQD,"xmm1,vm64y,xmm2","C4 RXB.02 0.src2.1.01 91 /r");
		AddInstructionV(opVPGATHERQQ,"xmm1,vm64x,xmm2","C4 RXB.02 1.src2.0.01 91 /r");
		AddInstructionV(opVPGATHERQQ,"ymm1,vm64y,ymm2","C4 RXB.02 1.src2.1.01 91 /r");
		AddInstructionV(opVPHADDBD,"xmm1,xmm2/mem128","8F RXB.09 0.1111.0.00 C2 /r");
		AddInstructionV(opVPHADDBQ,"xmm1,xmm2/mem128","8F RXB.09 0.1111.0.00 C3 /r");
		AddInstructionV(opVPHADDBW,"xmm1,xmm2/mem128","8F RXB.09 0.1111.0.00 C1 /r");
		AddInstructionV(opVPHADDD,"xmm1,xmm2,xmm3/mem128","C4 RXB.02 X.src1.0.01 02 /r");
		AddInstructionV(opVPHADDD,"ymm1,ymm2,ymm3/mem256","C4 RXB.02 X.src1.1.01 02 /r");
		AddInstructionV(opVPHADDDQ,"xmm1,xmm2/mem128","8F RXB.09 0.1111.0.00 CB /r");
		AddInstructionV(opVPHADDSW,"xmm1,xmm2,xmm3/mem128","C4 RXB.02 X.src1.0.01 03 /r");
		AddInstructionV(opVPHADDSW,"ymm1,ymm2,ymm3/mem256","C4 RXB.02 X.src1.1.01 03 /r");
		AddInstructionV(opVPHADDUBD,"xmm1,xmm2/mem128","8F RXB.09 0.1111.0.00 D2 /r");
		AddInstructionV(opVPHADDUBQ,"xmm1,xmm2/mem128","8F RXB.09 0.1111.0.00 D3 /r");
		AddInstructionV(opVPHADDUBW,"xmm1,xmm2/mem128","8F RXB.09 0.1111.0.00 D1 /r");
		AddInstructionV(opVPHADDUDQ,"xmm1,xmm2/mem128","8F RXB.09 0.1111.0.00 DB /r");
		AddInstructionV(opVPHADDUWD,"xmm1,xmm2/mem128","8F RXB.09 0.1111.0.00 D6 /r");
		AddInstructionV(opVPHADDUWQ,"xmm1,xmm2/mem128","8F RXB.09 0.1111.0.00 D7 /r");
		AddInstructionV(opVPHADDW,"xmm1,xmm2,xmm3/mem128","C4 RXB.02 X.src1.0.01 01 /r");
		AddInstructionV(opVPHADDW,"ymm1,ymm2,ymm3/mem256","C4 RXB.02 X.src1.1.01 01 /r");
		AddInstructionV(opVPHADDWD,"xmm1,xmm2/mem128","8F RXB.09 0.1111.0.00 C6 /r");
		AddInstructionV(opVPHADDWQ,"xmm1,xmm2/mem128","8F RXB.09 0.1111.0.00 C7 /r");
		AddInstructionV(opVPHMINPOSUW,"xmm1,xmm2/mem128","C4 RXB.02 X.1111.0.01 41 /r");
		AddInstructionV(opVPHSUBBW,"xmm1,xmm2/mem128","8F RXB.09 0.1111.0.00 E1 /r");
		AddInstructionV(opVPHSUBD,"xmm1,xmm2,xmm3/mem128","C4 RXB.02 X.src1.0.01 06 /r");
		AddInstructionV(opVPHSUBD,"ymm1,ymm2,ymm3/mem256","C4 RXB.02 X.src1.1.01 06 /r");
		AddInstructionV(opVPHSUBDQ,"xmm1,xmm2/mem128","8F RXB.09 0.1111.0.00 E3 /r");
		AddInstructionV(opVPHSUBSW,"xmm1,xmm2,xmm3/mem128","C4 RXB.02 X.src1.0.01 07 /r");
		AddInstructionV(opVPHSUBSW,"ymm1,ymm2,ymm3/mem256","C4 RXB.02 X.src1.1.01 07 /r");
		AddInstructionV(opVPHSUBW,"xmm1,xmm2,xmm3/mem128","C4 RXB.02 X.src1.0.01 05 /r");
		AddInstructionV(opVPHSUBW,"ymm1,ymm2,ymm3/mem256","C4 RXB.02 X.src1.1.01 05 /r");
		AddInstructionV(opVPHSUBWD,"xmm1,xmm2/mem128","8F RXB.09 0.1111.0.00 E2 /r");
		AddInstructionV(opVPINSRB,"xmm,reg/mem8,xmm,imm8","C4 RXB.03 X.1111.0.01 20 /r ib");
		AddInstructionV(opVPINSRD,"xmm,reg32/mem32,xmm,imm8","C4 RXB.03 0.1111.0.01 22 /r ib");
		AddInstructionV(opVPINSRQ,"xmm,reg64/mem64,xmm,imm8","C4 RXB.03 1.1111.0.01 22 /r ib");
		AddInstructionV(opVPINSRW,"xmm,reg32/mem16,xmm,imm8","C4 RXB.01 X.1111.0.01 C4 /r ib");
		AddInstructionV(opVPMACSDD,"xmm1,xmm2,xmm3/mem128,xmm4","8F RXB.08 0.src1.0.00 9E /r ib");
		AddInstructionV(opVPMACSDQH,"xmm1,xmm2,xmm3/mem128,xmm4","8F RXB.01000 0.src1.0.00 9F /r ib");
		AddInstructionV(opVPMACSDQL,"xmm1,xmm2,xmm3/mem128,xmm4","8F RXB.08 0.src1.0.00 97 /r ib");
		AddInstructionV(opVPMACSSDD,"xmm1,xmm2,xmm3/mem128,xmm4","8F RXB.08 X.src1.0.00 8E /r ib");
		AddInstructionV(opVPMACSSDQH,"xmm1,xmm2,xmm3/mem128,xmm4","8F RXB.08 0.src1.0.00 8F /r ib");
		AddInstructionV(opVPMACSSDQL,"xmm1,xmm2,xmm3/mem128,xmm4","8F RXB.08 0.src1.0.00 87 /r ib");
		AddInstructionV(opVPMACSSWD,"xmm1,xmm2,xmm3/mem128,xmm4","8F RXB.08 0.src1.0.00 86 /r ib");
		AddInstructionV(opVPMACSSWW,"xmm1,xmm2,xmm3/mem128,xmm4","8F RXB.08 X.src1.0.00 85 /r ib");
		AddInstructionV(opVPMACSWD,"xmm1,xmm2,xmm3/mem128,xmm4","8F RXB.08 0.src1.0.00 96 /r ib");
		AddInstructionV(opVPMACSWW,"xmm1,xmm2,xmm3/mem128,xmm4","8F RXB.08 0.src1.0.00 95 /r ib");
		AddInstructionV(opVPMADCSSWD,"xmm1,xmm2,xmm3/mem128,xmm4","8F RXB.08 0.src1.0.00 A6 /r ib");
		AddInstructionV(opVPMADDUBSW,"xmm1,xmm2,xmm3/mem128","C4 RXB.02 X.src1.0.01 04 /r");
		AddInstructionV(opVPMADDUBSW,"ymm1,ymm2,ymm3/mem256","C4 RXB.02 X.src1.1.01 04 /r");
		AddInstructionV(opVPMADDWD,"xmm1,xmm2,xmm3/mem128","C4 RXB.01 X.src1.0.01 F5 /r");
		AddInstructionV(opVPMADDWD,"ymm1,ymm2,ymm3/mem256","C4 RXB.01 X.src1.1.01 F5 /r");
		AddInstructionV(opVPMASKMOVD,"xmm1,xmm2,mem128","C4 RXB.02 0.src1.0.01 8C /r");
		AddInstructionV(opVPMASKMOVD,"ymm1,ymm2,mem256","C4 RXB.02 0.src1.1.01 8C /r");
		AddInstructionV(opVPMASKMOVD,"mem128,xmm1,xmm2","C4 RXB.02 0.src1.0.01 8E /r");
		AddInstructionV(opVPMASKMOVD,"mem256,ymm1,ymm2","C4 RXB.02 0.src1.1.01 8E /r");
		AddInstructionV(opVPMASKMOVQ,"xmm1,xmm2,mem128","C4 RXB.02 1.src1.0.01 8C /r");
		AddInstructionV(opVPMASKMOVQ,"ymm1,ymm2,mem256","C4 RXB.02 1.src1.1.01 8C /r");
		AddInstructionV(opVPMASKMOVQ,"mem128,xmm1,xmm2","C4 RXB.02 1.src1.0.01 8E /r");
		AddInstructionV(opVPMASKMOVQ,"mem256,ymm1,ymm2","C4 RXB.02 1.src1.1.01 8E /r");
		AddInstructionV(opVPMAXSB,"xmm1,xmm2,xmm3/mem128","C4 RXB.02 X.src1.0.01 3C /r");
		AddInstructionV(opVPMAXSB,"ymm1,ymm2,ymm3/mem256","C4 RXB.02 X.src1.1.01 3C /r");
		AddInstructionV(opVPMAXSD,"xmm1,xmm2,xmm3/mem128","C4 RXB.02 X.src1.0.01 3D /r");
		AddInstructionV(opVPMAXSD,"ymm1,ymm2,ymm3/mem256","C4 RXB.02 X.src1.1.01 3D /r");
		AddInstructionV(opVPMAXSW,"xmm1,xmm2,xmm3/mem128","C4 RXB.01 X.src1.0.01 EE /r");
		AddInstructionV(opVPMAXSW,"ymm1,ymm2,ymm3/mem256","C4 RXB.01 X.src1.1.01 EE /r");
		AddInstructionV(opVPMAXUB,"xmm1,xmm2,xmm3/mem128","C4 RXB.01 X.src1.0.01 DE /r");
		AddInstructionV(opVPMAXUB,"ymm1,ymm2,ymm3/mem256","C4 RXB.01 X.src1.1.01 DE /r");
		AddInstructionV(opVPMAXUD,"xmm1,xmm2,xmm3/mem128","C4 RXB.02 X.src1.0.01 3F /r");
		AddInstructionV(opVPMAXUD,"ymm1,ymm2,ymm3/mem256","C4 RXB.02 X.src1.1.01 3F /r");
		AddInstructionV(opVPMAXUW,"xmm1,xmm2,xmm3/mem128","C4 RXB.02 X.src1.0.01 3E /r");
		AddInstructionV(opVPMAXUW,"ymm1,ymm2,ymm3/mem256","C4 RXB.02 X.src1.1.01 3E /r");
		AddInstructionV(opVPMINSB,"xmm1,xmm2,xmm3/mem128","C4 RXB.02 X.src1.0.01 38 /r");
		AddInstructionV(opVPMINSB,"ymm1,ymm2,ymm3/mem256","C4 RXB.02 X.src1.1.01 38 /r");
		AddInstructionV(opVPMINSD,"xmm1,xmm2,xmm3/mem128","C4 RXB.02 X.src1.0.01 39 /r");
		AddInstructionV(opVPMINSD,"ymm1,ymm2,ymm3/mem256","C4 RXB.02 X.src1.1.01 39 /r");
		AddInstructionV(opVPMINSW,"xmm1,xmm2,xmm3/mem128","C4 RXB.01 X.src1.0.01 EA /r");
		AddInstructionV(opVPMINSW,"ymm1,ymm2,ymm3/mem256","C4 RXB.01 X.src1.1.01 EA /r");
		AddInstructionV(opVPMINUB,"xmm1,xmm2,xmm3/mem128","C4 RXB.01 X.src1.0.01 DA /r");
		AddInstructionV(opVPMINUB,"ymm1,ymm2,ymm3/mem256","C4 RXB.01 X.src1.1.01 DA /r");
		AddInstructionV(opVPMINUD,"xmm1,xmm2,xmm3/mem128","C4 RXB.02 X.src1.0.01 3B /r");
		AddInstructionV(opVPMINUD,"ymm1,ymm2,ymm3/mem256","C4 RXB.02 X.src1.1.01 3B /r");
		AddInstructionV(opVPMINUW,"xmm1,xmm2,xmm3/mem128","C4 RXB.02 X.src1.0.01 3A /r");
		AddInstructionV(opVPMINUW,"ymm1,ymm2,ymm3/mem256","C4 RXB.02 X.src1.1.01 3A /r");
		AddInstructionV(opVPMOVSXBD,"xmm1,xmm2/mem32","C4 RXB.02 X.1111.0.01 21 /r");
		AddInstructionV(opVPMOVSXBD,"ymm1,xmm2/mem64","C4 RXB.02 X.1111.1.01 21 /r");
		AddInstructionV(opVPMOVSXBQ,"xmm1,xmm2/mem16","C4 RXB.02 X.1111.0.01 22 /r");
		AddInstructionV(opVPMOVSXBQ,"ymm1,xmm2/mem32","C4 RXB.02 X.1111.1.01 22 /r");
		AddInstructionV(opVPMOVSXBW,"xmm1,xmm2/mem64","C4 RXB.02 X.1111.0.01 20 /r");
		AddInstructionV(opVPMOVSXBW,"ymm1,xmm2/mem128","C4 RXB.02 X.1111.1.01 20 /r");
		AddInstructionV(opVPMOVSXDQ,"xmm1,xmm2/mem64","C4 RXB.02 X.1111.0.01 25 /r");
		AddInstructionV(opVPMOVSXDQ,"ymm1,xmm2/mem128","C4 RXB.02 X.1111.1.01 25 /r");
		AddInstructionV(opVPMOVSXWD,"xmm1,xmm2/mem64","C4 RXB.02 X.1111.0.01 23 /r");
		AddInstructionV(opVPMOVSXWD,"ymm1,xmm2/mem128","C4 RXB.02 X.1111.1.01 23 /r");
		AddInstructionV(opVPMOVSXWQ,"xmm1,xmm2/mem32","C4 RXB.02 X.1111.0.01 24 /r");
		AddInstructionV(opVPMOVSXWQ,"ymm1,xmm2/mem64","C4 RXB.02 X.1111.1.01 24 /r");
		AddInstructionV(opVPMOVZXBD,"xmm1,xmm2/mem32","C4 RXB.02 X.1111.0.01 31 /r");
		AddInstructionV(opVPMOVZXBD,"ymm1,xmm2/mem64","C4 RXB.02 X.1111.1.01 31 /r");
		AddInstructionV(opVPMOVZXBQ,"xmm1,xmm2/mem16","C4 RXB.02 X.1111.0.01 32 /r");
		AddInstructionV(opVPMOVZXBQ,"ymm1,xmm2/mem32","C4 RXB.02 X.1111.1.01 32 /r");
		AddInstructionV(opVPMOVZXBW,"xmm1,xmm2/mem64","C4 RXB.02 X.1111.0.01 30 /r");
		AddInstructionV(opVPMOVZXBW,"ymm1,xmm2/mem128","C4 RXB.02 X.1111.1.01 30 /r");
		AddInstructionV(opVPMOVZXDQ,"xmm1,xmm2/mem64","C4 RXB.02 X.1111.0.01 35 /r");
		AddInstructionV(opVPMOVZXDQ,"ymm1,xmm2/mem128","C4 RXB.02 X.1111.1.01 35 /r");
		AddInstructionV(opVPMOVZXWD,"xmm1,xmm2/mem64","C4 RXB.02 X.1111.0.01 33 /r");
		AddInstructionV(opVPMOVZXWD,"ymm1,xmm2/mem128","C4 RXB.02 X.1111.1.01 33 /r");
		AddInstructionV(opVPMOVZXWQ,"xmm1,xmm2/mem32","C4 RXB.02 X.1111.0.01 34 /r");
		AddInstructionV(opVPMOVZXWQ,"ymm1,xmm2/mem64","C4 RXB.02 X.1111.1.01 34 /r");
		AddInstructionV(opVPMULDQ,"xmm1,xmm2,xmm3/mem128","C4 RXB.02 X.src1.0.01 28 /r");
		AddInstructionV(opVPMULDQ,"ymm1,ymm2,ymm3/mem256","C4 RXB.02 X.src1.1.01 28 /r");
		AddInstructionV(opVPMULHRSW,"xmm1,xmm2,xmm3/mem128","C4 RXB.2 X.src1.0.01 0B /r");
		AddInstructionV(opVPMULHRSW,"ymm1,ymm2,ymm3/mem256","C4 RXB.2 X.src1.1.01 0B /r");
		AddInstructionV(opVPMULHUW,"xmm1,xmm2,xmm3/mem128","C4 RXB.01 X.src1.0.01 E4 /r");
		AddInstructionV(opVPMULHUW,"ymm1,ymm2,ymm3/mem256","C4 RXB.01 X.src1.1.01 E4 /r");
		AddInstructionV(opVPMULHW,"xmm1,xmm2,xmm3/mem128","C4 RXB.01 X.src1.0.01 E5 /r");
		AddInstructionV(opVPMULHW,"ymm1,ymm2,ymm3/mem256","C4 RXB.01 X.src1.1.01 E5 /r");
		AddInstructionV(opVPMULLD,"xmm1,xmm2,xmm3/mem128","C4 RXB.02 X.src1.0.01 40 /r");
		AddInstructionV(opVPMULLD,"ymm1,ymm2,ymm3/mem256","C4 RXB.02 X.src1.1.01 40 /r");
		AddInstructionV(opVPMULLW,"xmm1,xmm2,xmm3/mem128","C4 RXB.01 X.src1.0.01 D5 /r");
		AddInstructionV(opVPMULLW,"ymm1,ymm2,ymm3/mem256","C4 RXB.01 X.src1.1.01 D5 /r");
		AddInstructionV(opVPMULUDQ,"xmm1,xmm2,xmm3/mem128","C4 RXB.01 X.src1.0.01 F4 /r");
		AddInstructionV(opVPMULUDQ,"ymm1,ymm2,ymm3/mem256","C4 RXB.01 X.src1.1.01 F4 /r");
		AddInstructionV(opVPOR,"xmm1,xmm2,xmm3/mem128","C4 RXB.01 X.src1.0.01 EB /r");
		AddInstructionV(opVPOR,"ymm1,ymm2,ymm3/mem256","C4 RXB.01 X.src1.1.01 EB /r");
		AddInstructionV(opVPPERM,"xmm1,xmm2,xmm3/mem128,xmm4","8F RXB.08 0.src1.0.00 A3 /r ib");
		AddInstructionV(opVPPERM,"xmm1,xmm2,xmm3,xmm4/mem128","8F RXB.08 1.src1.0.00 A3 /r ib");
		AddInstructionV(opVPROTB,"xmm1,xmm2/mem128,xmm3","8F RXB.09 0.count.0.00 90 /r");
		AddInstructionV(opVPROTB,"xmm1,xmm2,xmm3/mem128","8F RXB.09 1.src.0.00 90 /r");
		AddInstructionV(opVPROTB,"xmm1,xmm2/mem128,imm8","8F RXB.08 0.1111.0.00 C0 /r ib");
		AddInstructionV(opVPROTD,"xmm1,xmm2/mem128,xmm3","8F RXB.09 0.count.0.00 92 /r");
		AddInstructionV(opVPROTD,"xmm1,xmm2,xmm3/mem128","8F RXB.09 1.src.0.00 92 /r");
		AddInstructionV(opVPROTD,"xmm1,xmm2/mem128,imm8","8F RXB.08 0.1111.0.00 C2 /r ib");
		AddInstructionV(opVPROTQ,"xmm1,xmm2/mem128,xmm3","8F RXB.09 0.count.0.00 93 /r");
		AddInstructionV(opVPROTQ,"xmm1,xmm2,xmm3/mem128","8F RXB.09 1.src.0.00 93 /r");
		AddInstructionV(opVPROTQ,"xmm1,xmm2/mem128,imm8","8F RXB.08 0.1111.0.00 C3 /r ib");
		AddInstructionV(opVPROTW,"xmm1,xmm2/mem128,xmm3","8F RXB.09 0.count.0.00 91 /r");
		AddInstructionV(opVPROTW,"xmm1,xmm2,xmm3/mem128","8F RXB.09 1.src.0.00 91 /r");
		AddInstructionV(opVPROTW,"xmm1,xmm2/mem128,imm8","8F RXB.08 0.1111.0.00 C1 /r ib");
		AddInstructionV(opVPSADBW,"xmm1,xmm2,xmm3/mem128","C4 RXB.01 X.src1.0.01 F6 /r");
		AddInstructionV(opVPSADBW,"ymm1,ymm2,ymm3/mem256","C4 RXB.01 X.src1.1.01 F6 /r");
		AddInstructionV(opVPSHAB,"xmm1,xmm2/mem128,xmm3","8F RXB.09 0.count.0.00 98 /r");
		AddInstructionV(opVPSHAB,"xmm1,xmm2,xmm3/mem128","8F RXB.09 1.src.0.00 98 /r");
		AddInstructionV(opVPSHAD,"xmm1,xmm2/mem128,xmm3","8F RXB.09 0.count.0.00 9A /r");
		AddInstructionV(opVPSHAD,"xmm1,xmm2,xmm3/mem128","8F RXB.09 1.src.0.00 9A /r");
		AddInstructionV(opVPSHAQ,"xmm1,xmm2/mem128,xmm3","8F RXB.09 0.count.0.00 9B /r");
		AddInstructionV(opVPSHAQ,"xmm1,xmm2,xmm3/mem128","8F RXB.09 1.src.0.00 9B /r");
		AddInstructionV(opVPSHAW,"xmm1,xmm2/mem128,xmm3","8F RXB.09 0.count.0.00 99 /r");
		AddInstructionV(opVPSHAW,"xmm1,xmm2,xmm3/mem128","8F RXB.09 1.src.0.00 99 /r");
		AddInstructionV(opVPSHLB,"xmm1,xmm2/mem128,xmm3","8F RXB.09 0.count.0.00 94 /r");
		AddInstructionV(opVPSHLB,"xmm1,xmm2,xmm3/mem128","8F RXB.09 1.src.0.00 94 /r");
		AddInstructionV(opVPSHLD,"xmm1,xmm3/mem128,xmm2","8F RXB.09 0.count.0.00 96 /r");
		AddInstructionV(opVPSHLD,"xmm1,xmm2,xmm3/mem128","8F RXB.09 1.src.0.00 96 /r");
		AddInstructionV(opVPSHLQ,"xmm1,xmm3/mem128,xmm2","8F RXB.09 0.count.0.00 97 /r");
		AddInstructionV(opVPSHLQ,"xmm1,xmm2,xmm3/mem128","8F RXB.09 1.src.0.00 97 /r");
		AddInstructionV(opVPSHLW,"xmm1,xmm3/mem128,xmm2","8F RXB.09 0.count.0.00 95 /r");
		AddInstructionV(opVPSHLW,"xmm1,xmm2,xmm3/mem128","8F RXB.09 1.src.0.00 95 /r");
		AddInstructionV(opVPSHUFB,"xmm1,xmm2,xmm3/mem128","C4 RXB.02 X.src1.0.01 00 /r");
		AddInstructionV(opVPSHUFB,"ymm1,ymm2,ymm3/mem256","C4 RXB.02 X.src1.1.01 00 /r");
		AddInstructionV(opVPSHUFD,"xmm1,xmm2/mem128,imm8","C4 RXB.01 X.1111.0.01 70 /r ib");
		AddInstructionV(opVPSHUFD,"ymm1,ymm2/mem256,imm8","C4 RXB.01 X.1111.1.01 70 /r ib");
		AddInstructionV(opVPSHUFHW,"xmm1,xmm2/mem128,imm8","C4 RXB.01 X.1111.0.10 70 /r ib");
		AddInstructionV(opVPSHUFHW,"ymm1,ymm2/mem256,imm8","C4 RXB.01 X.1111.1.10 70 /r ib");
		AddInstructionV(opVPSHUFLW,"xmm1,xmm2/mem128,imm8","C4 RXB.01 X.1111.0.11 70 /r ib");
		AddInstructionV(opVPSHUFLW,"ymm1,ymm2/mem256,imm8","C4 RXB.01 X.1111.1.11 70 /r ib");
		AddInstructionV(opVPSIGNB,"xmm1,xmm2,xmm2/mem128","C4 RXB.02 X.src1.0.01 08 /r");
		AddInstructionV(opVPSIGNB,"ymm1,ymm2,ymm2/mem256","C4 RXB.02 X.src1.1.01 08 /r");
		AddInstructionV(opVPSIGND,"xmm1,xmm2,xmm3/mem128","C4 RXB.02 X.src1.0.01 0A /r");
		AddInstructionV(opVPSIGND,"ymm1,ymm2,ymm3/mem256","C4 RXB.02 X.src1.1.01 0A /r");
		AddInstructionV(opVPSIGNW,"xmm1,xmm2,xmm3/mem128","C4 RXB.02 X.src1.0.01 09 /r");
		AddInstructionV(opVPSIGNW,"ymm1,ymm2,ymm3/mem256","C4 RXB.02 X.src1.1.01 09 /r");
		AddInstructionV(opVPSLLD,"xmm1,xmm2,xmm3/mem128","C4 RXB.01 X.src1.0.01 F2 /r");
		AddInstructionV(opVPSLLD,"xmm1,xmm2,imm8","C4 RXB.01 X.dest.0.01 72 /6 ib");
		AddInstructionV(opVPSLLD,"ymm1,ymm2,xmm3/mem128","C4 RXB.01 X.src1.1.01 F2 /r");
		AddInstructionV(opVPSLLD,"ymm1,ymm2,imm8","C4 RXB.01 X.dest.1.01 72 /6 ib");
		AddInstructionV(opVPSLLDQ,"xmm1,xmm2,imm8","C4 RXB.01 0.dest.0.01 73 /7 ib");
		AddInstructionV(opVPSLLDQ,"ymm1,ymm2,imm8","C4 RXB.01 0.dest.1.01 73 /7 ib");
		AddInstructionV(opVPSLLQ,"xmm1,xmm2,xmm3/mem128","C4 RXB.01 X.src1.0.01 F3 /r");
		AddInstructionV(opVPSLLQ,"xmm1,xmm2,imm8","C4 RXB.01 X.dest.0.01 73 /6 ib");
		AddInstructionV(opVPSLLQ,"ymm1,ymm2,xmm3/mem128","C4 RXB.01 X.src1.1.01 F3 /r");
		AddInstructionV(opVPSLLQ,"ymm1,ymm2,imm8","C4 RXB.01 X.dest.1.01 73 /6 ib");
		AddInstructionV(opVPSLLVD,"xmm1,xmm2,xmm3/mem128","C4 RXB.02 0.src1.0.01 47 /r");
		AddInstructionV(opVPSLLVD,"ymm1,ymm2,ymm3/mem256","C4 RXB.02 0.src1.1.01 47 /r");
		AddInstructionV(opVPSLLVQ,"xmm1,xmm2,xmm3/mem128","C4 RXB.02 1.src1.0.01 47 /r");
		AddInstructionV(opVPSLLVQ,"ymm1,ymm2,ymm3/mem256","C4 RXB.02 1.src1.1.01 47 /r");
		AddInstructionV(opVPSLLW,"xmm1,xmm2,xmm3/mem128","C4 RXB.01 X.src1.0.01 F1 /r");
		AddInstructionV(opVPSLLW,"xmm1,xmm2,imm8","C4 RXB.01 X.dest.0.01 71 /6 ib");
		AddInstructionV(opVPSLLW,"ymm1,ymm2,xmm3/mem128","C4 RXB.01 X.src1.1.01 F1 /r");
		AddInstructionV(opVPSLLW,"ymm1,ymm2,imm8","C4 RXB.01 X.dest.1.01 71 /6 ib");
		AddInstructionV(opVPSRAD,"xmm1,xmm2,xmm3/mem128","C4 RXB.01 X.src1.0.01 E2 /r");
		AddInstructionV(opVPSRAD,"xmm1,xmm2,imm8","C4 RXB.01 X.dest.0.01 72 /4 ib");
		AddInstructionV(opVPSRAD,"ymm1,ymm2,xmm3/mem128","C4 RXB.01 X.src1.1.01 E2 /r");
		AddInstructionV(opVPSRAD,"ymm1,ymm2,imm8","C4 RXB.01 X.dest.1.01 72 /4 ib");
		AddInstructionV(opVPSRAVD,"xmm1,xmm2,xmm3/mem128","C4 RXB.02 0.src1.0.01 46 /r");
		AddInstructionV(opVPSRAVD,"ymm1,ymm2,ymm3/mem256","C4 RXB.02 0.src1.1.01 46 /r");
		AddInstructionV(opVPSRAW,"xmm1,xmm2,xmm3/mem128","C4 RXB.01 X.src1.0.01 E1 /r");
		AddInstructionV(opVPSRAW,"xmm1,xmm2,imm8","C4 RXB.01 X.dest.0.01 71 /4 ib");
		AddInstructionV(opVPSRAW,"ymm1,ymm2,xmm3/mem128","C4 RXB.01 X.src1.1.01 E1 /r");
		AddInstructionV(opVPSRAW,"ymm1,ymm2,imm8","C4 RXB.01 X.dest.1.01 71 /4 ib");
		AddInstructionV(opVPSRLD,"xmm1,xmm2,xmm3/mem128","C4 RXB.01 X.src1.0.01 D2 /r");
		AddInstructionV(opVPSRLD,"xmm1,xmm2,imm8","C4 RXB.01 X.dest.0.01 72 /2 ib");
		AddInstructionV(opVPSRLD,"ymm1,ymm2,xmm3/mem128","C4 RXB.01 X.src1.1.01 D2 /r");
		AddInstructionV(opVPSRLD,"ymm1,ymm2,imm8","C4 RXB.01 X.dest.1.01 72 /2 ib");
		AddInstructionV(opVPSRLDQ,"xmm1,xmm2,imm8","C4 RXB.01 X.dest.0.01 73 /3 ib");
		AddInstructionV(opVPSRLDQ,"ymm1,ymm2,imm8","C4 RXB.01 X.dest.1.01 73 /3 ib");
		AddInstructionV(opVPSRLQ,"xmm1,xmm2,xmm3/mem128","C4 RXB.01 X.src1.0.01 D3 /r");
		AddInstructionV(opVPSRLQ,"xmm1,xmm2,imm8","C4 RXB.01 X.dest.0.01 73 /2 ib");
		AddInstructionV(opVPSRLQ,"ymm1,ymm2,xmm3/mem128","C4 RXB.01 X.src1.1.01 D3 /r");
		AddInstructionV(opVPSRLQ,"ymm1,ymm2,imm8","C4 RXB.01 X.dest.1.01 73 /2 ib");
		AddInstructionV(opVPSRLVD,"xmm1,xmm2,xmm3/mem128","C4 RXB.02 0.src1.0.01 45 /r");
		AddInstructionV(opVPSRLVD,"ymm1,ymm2,ymm3/mem256","C4 RXB.02 0.src1.1.01 45 /r");
		AddInstructionV(opVPSRLVQ,"xmm1,xmm2,xmm3/mem128","C4 RXB.02 1.src1.0.01 45 /r");
		AddInstructionV(opVPSRLVQ,"ymm1,ymm2,ymm3/mem256","C4 RXB.02 1.src1.1.01 45 /r");
		AddInstructionV(opVPSRLW,"xmm1,xmm2,xmm3/mem128","C4 RXB.01 X.src1.0.01 D1 /r");
		AddInstructionV(opVPSRLW,"xmm1,xmm2,imm8","C4 RXB.01 X.dest.0.01 71 /2 ib");
		AddInstructionV(opVPSRLW,"ymm1,ymm2,xmm3/mem128","C4 RXB.01 X.src1.1.01 D1 /r");
		AddInstructionV(opVPSRLW,"ymm1,ymm2,imm8","C4 RXB.01 X.dest.1.01 71 /2 ib");
		AddInstructionV(opVPSUBB,"xmm1,xmm2,xmm3/mem128","C4 RXB.01 X.src1.0.01 F8 /r");
		AddInstructionV(opVPSUBB,"ymm1,ymm2,ymm3/mem256","C4 RXB.01 X.src1.1.01 F8 /r");
		AddInstructionV(opVPSUBD,"xmm1,xmm2,xmm3/mem128","C4 RXB.01 X.src1.0.01 FA /r");
		AddInstructionV(opVPSUBD,"ymm1,ymm2,ymm3/mem256","C4 RXB.01 X.src1.1.01 FA /r");
		AddInstructionV(opVPSUBQ,"xmm1,xmm2,xmm3/mem128","C4 RXB.01 X.src1.0.01 FB /r");
		AddInstructionV(opVPSUBQ,"ymm1,ymm2,ymm3/mem256","C4 RXB.01 X.src1.1.01 FB /r");
		AddInstructionV(opVPSUBSB,"xmm1,xmm2,xmm3/mem128","C4 RXB.01 X.src1.0.01 E8 /r");
		AddInstructionV(opVPSUBSB,"ymm1,ymm2,ymm3/mem256","C4 RXB.01 X.src1.1.01 E8 /r");
		AddInstructionV(opVPSUBSW,"xmm1,xmm2,xmm3/mem128","C4 RXB.01 X.src1.0.01 E9 /r");
		AddInstructionV(opVPSUBSW,"ymm1,ymm2,ymm3/mem256","C4 RXB.01 X.src1.1.01 E9 /r");
		AddInstructionV(opVPSUBUSB,"xmm1,xmm2,xmm3/mem128","C4 RXB.01 X.src1.0.01 D8 /r");
		AddInstructionV(opVPSUBUSB,"ymm1,ymm2,ymm3/mem256","C4 RXB.01 X.src1.1.01 D8 /r");
		AddInstructionV(opVPSUBUSW,"xmm1,xmm2,xmm3/mem128","C4 RXB.01 X.src1.0.01 D9 /r");
		AddInstructionV(opVPSUBUSW,"ymm1,ymm2,ymm3/mem256","C4 RXB.01 X.src1.1.01 D9 /r");
		AddInstructionV(opVPSUBW,"xmm1,xmm2,xmm3/mem128","C4 RXB.01 X.src1.0.01 F9 /r");
		AddInstructionV(opVPSUBW,"ymm1,ymm2,ymm3/mem256","C4 RXB.01 X.src1.1.01 F9 /r");
		AddInstructionV(opVPTEST,"xmm1,xmm2/mem128","C4 RXB.00010 X.1111.0.01 17 /r");
		AddInstructionV(opVPTEST,"ymm1,ymm2/mem256","C4 RXB.00010 X.1111.1.01 17 /r");
		AddInstructionV(opVPUNPCKHBW,"xmm1,xmm2,xmm3/mem128","C4 RXB.01 X.src1.0.01 68 /r");
		AddInstructionV(opVPUNPCKHBW,"ymm1,ymm2,ymm3/mem256","C4 RXB.01 X.src1.1.01 68 /r");
		AddInstructionV(opVPUNPCKHDQ,"xmm1,xmm2,xmm3/mem128","C4 RXB.01 X.src1.0.01 6A /r");
		AddInstructionV(opVPUNPCKHDQ,"ymm1,ymm2,ymm3/mem256","C4 RXB.01 X.src1.1.01 6A /r");
		AddInstructionV(opVPUNPCKHQDQ,"xmm1,xmm2,xmm3/mem128","C4 RXB.01 X.src1.0.01 6D /r");
		AddInstructionV(opVPUNPCKHQDQ,"ymm1,ymm2,ymm3/mem256","C4 RXB.01 X.src1.1.01 6D /r");
		AddInstructionV(opVPUNPCKHWD,"xmm1,xmm2,xmm3/mem128","C4 RXB.01 X.src1.0.01 69 /r");
		AddInstructionV(opVPUNPCKHWD,"ymm1,ymm2,ymm3/mem256","C4 RXB.01 X.src1.1.01 69 /r");
		AddInstructionV(opVPUNPCKLBW,"xmm1,xmm2,xmm3/mem128","C4 RXB.01 X.src1.0.01 60 /r");
		AddInstructionV(opVPUNPCKLBW,"ymm1,ymm2,ymm3/mem256","C4 RXB.01 X.src1.1.01 60 /r");
		AddInstructionV(opVPUNPCKLDQ,"xmm1,xmm2,xmm3/mem128","C4 RXB.01 X.src1.0.01 62 /r");
		AddInstructionV(opVPUNPCKLDQ,"ymm1,ymm2,ymm3/mem256","C4 RXB.01 X.src1.1.01 62 /r");
		AddInstructionV(opVPUNPCKLQDQ,"xmm1,xmm2,xmm3/mem128","C4 RXB.01 X.src1.0.01 6C /r");
		AddInstructionV(opVPUNPCKLQDQ,"ymm1,ymm2,ymm3/mem256","C4 RXB.01 X.src1.1.01 6C /r");
		AddInstructionV(opVPUNPCKLWD,"xmm1,xmm2,xmm3/mem128","C4 RXB.01 X.src1.0.01 61 /r");
		AddInstructionV(opVPUNPCKLWD,"ymm1,ymm2,ymm3/mem256","C4 RXB.01 X.src1.1.01 61 /r");
		AddInstructionV(opVPXOR,"xmm1,xmm2,xmm3/mem128","C4 RXB.01 X.src1.0.01 EF /r");
		AddInstructionV(opVPXOR,"ymm1,ymm2,ymm3/mem256","C4 RXB.01 X.src1.1.01 EF /r");
		AddInstructionV(opVRCPPS,"xmm1,xmm2/mem128","C4 RXB.01 X.1111.0.00 53 /r");
		AddInstructionV(opVRCPPS,"ymm1,ymm2/mem256","C4 RXB.01 X.1111.1.00 53 /r");
		AddInstructionV(opVRCPSS,"xmm1,xmm2,xmm3/mem128","C4 RXB.01 X.src1.X.10 53 /r");
		AddInstructionV(opVROUNDPD,"xmm1,xmm2/mem128,imm8","C4 RXB.03 X.1111.0.01 09 /r ib");
		AddInstructionV(opVROUNDPD,"ymm1,ymm2/mem256,imm8","C4 RXB.03 X.1111.1.01 09 /r ib");
		AddInstructionV(opVROUNDPS,"xmm1,xmm2/mem128,imm8","C4 RXB.03 X.1111.0.01 08 /r ib");
		AddInstructionV(opVROUNDPS,"ymm1,ymm2/mem256,imm8","C4 RXB.03 X.1111.1.01 08 /r ib");
		AddInstructionV(opVROUNDSD,"xmm1,xmm2,xmm3/mem64,imm8","C4 RXB.03 X.src1.X.01 0B /r ib");
		AddInstructionV(opVROUNDSS,"xmm1,xmm2,xmm3/mem32,imm8","C4 RXB.03 X.src1.X.01 0A /r ib");
		AddInstructionV(opVRSQRTPS,"xmm1,xmm2/mem128","C4 RXB.01 X.1111.0.00 52 /r");
		AddInstructionV(opVRSQRTPS,"ymm1,ymm2/mem256","C4 RXB.01 X.1111.1.00 52 /r");
		AddInstructionV(opVRSQRTSS,"xmm1,xmm2,xmm3/mem32","C4 RXB.01 X.src1.X.10 52 /r");
		AddInstructionV(opVSHUFPD,"xmm1,xmm2,xmm3/mem128,imm8","C4 RXB.01 X.src1.0.01 C6 /r ib");
		AddInstructionV(opVSHUFPD,"ymm1,ymm2,ymm3/mem256,imm8","C4 RXB.01 X.src1.1.01 C6 /r ib");
		AddInstructionV(opVSHUFPS,"xmm1,xmm2,xmm3/mem128,imm8","C4 RXB.01 X.src1.0.00 C6 /r ib");
		AddInstructionV(opVSHUFPS,"ymm1,ymm2,ymm3/mem256,imm8","C4 RXB.01 X.src1.1.00 C6 /r ib");
		AddInstructionV(opVSQRTPD,"xmm1,xmm2/mem128","C4 RXB.01 X.1111.0.01 51 /r");
		AddInstructionV(opVSQRTPD,"ymm1,ymm2/mem256","C4 RXB.01 X.1111.1.01 51 /r");
		AddInstructionV(opVSQRTPS,"xmm1,xmm2/mem128","C4 RXB.01 X.1111.0.00 51 /r");
		AddInstructionV(opVSQRTPS,"ymm1,ymm2/mem256","C4 RXB.01 X.1111.1.00 51 /r");
		AddInstructionV(opVSQRTSD,"xmm1,xmm2,xmm3/mem64","C4 RXB.01 X.src1.X.11 51 /r");
		AddInstructionV(opVSQRTSS,"xmm1,xmm2,xmm3/mem32","C4 RXB.01 X.src1.X.10 51 /r");
		AddInstructionV(opVSTMXCSR,"mem32","C4 RXB.01 X.1111.0.00 AE /3");
		AddInstructionV(opVSUBPD,"xmm1,xmm2,xmm3/mem128","C4 RXB.01 X.src1.0.01 5C /r");
		AddInstructionV(opVSUBPD,"ymm1,ymm2,ymm3/mem256","C4 RXB.01 X.src1.1.01 5C /r");
		AddInstructionV(opVSUBPS,"xmm1,xmm2,xmm3/mem128","C4 RXB.00001 X.src.0.00 5C /r");
		AddInstructionV(opVSUBPS,"ymm1,ymm2,ymm3/mem256","C4 RXB.00001 X.src.1.00 5C /r");
		AddInstructionV(opVSUBSD,"xmm1,xmm2,xmm3/mem64","C4 RXB.01 X.src1.X.11 5C /r");
		AddInstructionV(opVSUBSS,"xmm1,xmm2,xmm3/mem32","C4 RXB.01 X.src1.X.10 5C /r");
		AddInstructionV(opVTESTPD,"xmm1,xmm2/mem128","C4 RXB.02 0.1111.0.01 0F /r");
		AddInstructionV(opVTESTPD,"ymm1,ymm2/mem256","C4 RXB.02 0.1111.1.01 0F /r");
		AddInstructionV(opVTESTPS,"xmm1,xmm2/mem128","C4 RXB.02 0.1111.0.01 0E /r");
		AddInstructionV(opVTESTPS,"ymm1,ymm2/mem256","C4 RXB.02 0.1111.1.01 0E /r");
		AddInstructionV(opVUCOMISD,"xmm1,xmm2/mem64","C4 RXB.00001 X.1111.X.01 2E /r");
		AddInstructionV(opVUCOMISS,"xmm1,xmm2/mem32","C4 RXB.01 X.1111.X.00 2E /r");
		AddInstructionV(opVUNPCKHPD,"xmm1,xmm2,xmm3/mem128","C4 RXB.01 X.src1.0.01 15 /r");
		AddInstructionV(opVUNPCKHPD,"ymm1,ymm2,ymm3/mem256","C4 RXB.01 X.src1.1.01 15 /r");
		AddInstructionV(opVUNPCKHPS,"xmm1,xmm2,xmm3/mem128","C4 RXB.01 X.src1.0.00 15 /r");
		AddInstructionV(opVUNPCKHPS,"ymm1,ymm2,ymm3/mem256","C4 RXB.01 X.src1.1.00 15 /r");
		AddInstructionV(opVUNPCKLPD,"xmm1,xmm2,xmm3/mem128","C4 RXB.01 X.src1.0.01 14 /r");
		AddInstructionV(opVUNPCKLPD,"ymm1,ymm2,ymm3/mem256","C4 RXB.01 X.src1.1.01 14 /r");
		AddInstructionV(opVUNPCKLPS,"xmm1,xmm2,xmm3/mem128","C4 RXB.01 X.src1.0.00 14 /r");
		AddInstructionV(opVUNPCKLPS,"ymm1,ymm2,ymm3/mem256","C4 RXB.01 X.src1.1.00 14 /r");
		AddInstructionV(opVXORPD,"xmm1,xmm2,xmm3/mem128","C4 RXB.01 X.src1.0.01 57 /r");
		AddInstructionV(opVXORPD,"ymm1,ymm2,ymm3/mem256","C4 RXB.01 X.src1.1.01 57 /r");
		AddInstructionV(opVXORPS,"xmm1,xmm2,xmm3/mem128","C4 RXB.01 X.src1.0.00 57 /r");
		AddInstructionV(opVXORPS,"ymm1,ymm2,ymm3/mem256","C4 RXB.01 X.src1.1.00 57 /r");
		AddInstructionV(opVZEROALL,"","C4 RXB.01 X.1111.1.00 77");
		AddInstructionV(opVZEROUPPER,"","C4 RXB.01 X.1111.0.00 77");
	END InitInstructions;

	PROCEDURE IsImmediate8*(operandType: OperandType): BOOLEAN;
	BEGIN RETURN (operandType = imm8) OR (operandType = simm8) OR (operandType = uimm8)
	END IsImmediate8;

	PROCEDURE IsImmediate16*(operandType: OperandType): BOOLEAN;
	BEGIN RETURN (operandType = imm16) OR (operandType = simm16) OR (operandType = uimm16)
	END IsImmediate16;

	PROCEDURE IsImmediate32*(operandType: OperandType): BOOLEAN;
	BEGIN RETURN (operandType = imm32) OR (operandType = simm32) OR (operandType = uimm32)
	END IsImmediate32;

	PROCEDURE IsImmediate64*(operandType: OperandType): BOOLEAN;
	BEGIN RETURN (operandType = imm64)
	END IsImmediate64;

	(** setup register tables **)
	PROCEDURE InitRegisters;
		(* insert an new register *)
		PROCEDURE AddRegister (number: LONGINT; CONST name: ARRAY OF CHAR; type: OperandType; sizeInBytes: SHORTINT; index: SHORTINT);
		BEGIN
			COPY (name, registers[number].name);
			registers[number].type := type;
			registers[number].index := index;
			registers[number].sizeInBytes := sizeInBytes;
			registersByClass[type,index] := number;
		END AddRegister;

		PROCEDURE InitRegisters;
		VAR i,j: LONGINT;
		BEGIN
			FOR i := 0 TO LEN(registersByClass)-1 DO
				FOR j := 0 TO LEN(registersByClass[i])-1 DO
					registersByClass[i,j] := none;
				END;
			END;
		END InitRegisters;

	BEGIN
		InitRegisters;

		AddRegister (regAL,"AL", reg8, bits8, 0);
		AddRegister (regCL,"CL", reg8, bits8,1);
		AddRegister (regDL,"DL", reg8, bits8,2);
		AddRegister (regBL,"BL", reg8, bits8,3);
		AddRegister (regAH,"AH", reg8, bits8,4);
		AddRegister (regCH,"CH", reg8, bits8,5);
		AddRegister (regDH,"DH", reg8, bits8,6);
		AddRegister (regBH,"BH", reg8, bits8,7);
		AddRegister (regSPL,"SPL", reg8, bits8, 4);
		AddRegister (regBPL,"BPL", reg8, bits8,5);
		AddRegister (regSIL,"SIL", reg8, bits8,6);
		AddRegister (regDIL,"DIL", reg8, bits8,7);
		AddRegister (regR8B,"R8B", reg8, bits8,8);
		AddRegister (regR9B,"R9B", reg8, bits8,9);
		AddRegister (regR10B,"R10B", reg8, bits8,10);
		AddRegister (regR11B,"R11B", reg8, bits8,11);
		AddRegister (regR12B,"R12B", reg8, bits8,12);
		AddRegister (regR13B,"R13B", reg8, bits8,13);
		AddRegister (regR14B,"R14B", reg8, bits8,14);
		AddRegister (regR15B,"R15B", reg8, bits8,15);

		AddRegister (regAX,"AX", reg16, bits16, 0);
		AddRegister (regCX,"CX", reg16, bits16, 1);
		AddRegister (regDX,"DX", reg16, bits16, 2);
		AddRegister (regBX,"BX", reg16, bits16, 3);
		AddRegister (regSP,"SP", reg16, bits16, 4);
		AddRegister (regBP,"BP", reg16, bits16, 5);
		AddRegister (regSI,"SI", reg16, bits16, 6);
		AddRegister (regDI,"DI", reg16, bits16, 7);
		AddRegister (regR8W,"R8W", reg16, bits16, 8);
		AddRegister (regR9W,"R9W", reg16, bits16, 9);
		AddRegister (regR10W,"R10W", reg16, bits16, 10);
		AddRegister (regR11W,"R11W", reg16, bits16, 11);
		AddRegister (regR12W,"R12W", reg16, bits16, 12);
		AddRegister (regR13W,"R13W", reg16, bits16, 13);
		AddRegister (regR14W,"R14W", reg16, bits16, 14);
		AddRegister (regR15W,"R15W", reg16, bits16, 15);

		AddRegister (regEAX,"EAX", reg32, bits32, 0);
		AddRegister (regECX,"ECX", reg32, bits32, 1);
		AddRegister (regEDX,"EDX", reg32, bits32, 2);
		AddRegister (regEBX,"EBX", reg32, bits32, 3);
		AddRegister (regESP,"ESP", reg32, bits32, 4);
		AddRegister (regEBP,"EBP", reg32, bits32, 5);
		AddRegister (regESI,"ESI", reg32, bits32, 6);
		AddRegister (regEDI,"EDI", reg32, bits32, 7);
		AddRegister (regR8D,"R8D", reg32, bits32, 8);
		AddRegister (regR9D,"R9D", reg32, bits32, 9);
		AddRegister (regR10D,"R10D", reg32, bits32, 10);
		AddRegister (regR11D,"R11D", reg32, bits32, 11);
		AddRegister (regR12D,"R12D", reg32, bits32, 12);
		AddRegister (regR13D,"R13D", reg32, bits32, 13);
		AddRegister (regR14D,"R14D", reg32, bits32, 14);
		AddRegister (regR15D,"R15D", reg32, bits32, 15);

		AddRegister (regRAX,"RAX", reg64, bits64, 0);
		AddRegister (regRCX,"RCX", reg64, bits64, 1);
		AddRegister (regRDX,"RDX", reg64, bits64, 2);
		AddRegister (regRBX,"RBX", reg64, bits64, 3);
		AddRegister (regRSP,"RSP", reg64, bits64, 4);
		AddRegister (regRBP,"RBP", reg64, bits64, 5);
		AddRegister (regRSI, "RSI", reg64,bits64,  6);
		AddRegister (regRDI,"RDI", reg64, bits64, 7);
		AddRegister (regR8,"R8", reg64, bits64, 8);
		AddRegister (regR9,"R9", reg64, bits64, 9);
		AddRegister (regR10,"R10", reg64, bits64, 10);
		AddRegister (regR11,"R11", reg64, bits64, 11);
		AddRegister (regR12,"R12", reg64, bits64, 12);
		AddRegister (regR13,"R13", reg64, bits64, 13);
		AddRegister (regR14,"R14", reg64, bits64, 14);
		AddRegister (regR15,"R15", reg64, bits64, 15);
		AddRegister (regRIP,"RIP", reg64, bits64, 16);

		AddRegister (regES,"ES", segReg, bitsDefault, 0);
		AddRegister (regCS,"CS", segReg,  bitsDefault, 1);
		AddRegister (regSS,"SS", segReg,  bitsDefault, 2);
		AddRegister (regDS,"DS", segReg,  bitsDefault, 3);
		AddRegister (regFS,"FS", segReg,  bitsDefault, 4);
		AddRegister (regGS,"GS", segReg,  bitsDefault, 5);

		AddRegister (regCR0,"CR0", CRn, bitsDefault, 0);
		AddRegister (regCR1,"CR1", CRn, bitsDefault, 1);
		AddRegister (regCR2,"CR2", CRn, bitsDefault, 2);
		AddRegister (regCR3,"CR3", CRn, bitsDefault, 3);
		AddRegister (regCR4,"CR4", CRn, bitsDefault, 4);
		AddRegister (regCR5,"CR5", CRn, bitsDefault, 5);
		AddRegister (regCR6,"CR6", CRn, bitsDefault, 6);
		AddRegister (regCR7,"CR7", CRn, bitsDefault, 7);
		AddRegister (regCR8,"CR8", CRn, bitsDefault, 8);
		AddRegister (regCR9,"CR9", CRn, bitsDefault, 9);
		AddRegister (regCR10,"CR10", CRn, bitsDefault, 10);
		AddRegister (regCR11,"CR11", CRn, bitsDefault, 11);
		AddRegister (regCR12,"CR12", CRn, bitsDefault, 12);
		AddRegister (regCR13,"CR13", CRn, bitsDefault, 13);
		AddRegister (regCR14,"CR14", CRn, bitsDefault, 14);
		AddRegister (regCR15,"CR15", CRn, bitsDefault, 15);

		AddRegister (regDR0,"DR0", DRn, bitsDefault, 0);
		AddRegister (regDR1,"DR1", DRn, bitsDefault, 1);
		AddRegister (regDR2,"DR2", DRn, bitsDefault, 2);
		AddRegister (regDR3,"DR3", DRn, bitsDefault, 3);
		AddRegister (regDR4,"DR4", DRn, bitsDefault, 4);
		AddRegister (regDR5,"DR5", DRn, bitsDefault, 5);
		AddRegister (regDR6,"DR6", DRn, bitsDefault, 6);
		AddRegister (regDR7,"DR7", DRn, bitsDefault, 7);
		AddRegister (regDR8,"DR8", DRn, bitsDefault, 8);
		AddRegister (regDR9,"DR9", DRn, bitsDefault, 9);
		AddRegister (regDR10,"DR10", DRn, bitsDefault, 10);
		AddRegister (regDR11,"DR11", DRn, bitsDefault, 11);
		AddRegister (regDR12,"DR12", DRn, bitsDefault, 12);
		AddRegister (regDR13,"DR13", DRn, bitsDefault, 13);
		AddRegister (regDR14,"DR14", DRn, bitsDefault, 14);
		AddRegister (regDR15,"DR15", DRn, bitsDefault, 15);

		AddRegister (regST0,"ST0", sti, bitsDefault, 0);
		AddRegister (regST1,"ST1", sti, bitsDefault, 1);
		AddRegister (regST2,"ST2", sti, bitsDefault, 2);
		AddRegister (regST3,"ST3", sti, bitsDefault, 3);
		AddRegister (regST4,"ST4", sti, bitsDefault, 4);
		AddRegister (regST5,"ST5", sti, bitsDefault, 5);
		AddRegister (regST6,"ST6", sti, bitsDefault, 6);
		AddRegister (regST7,"ST7", sti, bitsDefault, 7);

		AddRegister (regXMM0,"XMM0", xmm, bits64, 0);
		AddRegister (regXMM1,"XMM1", xmm, bits64, 1);
		AddRegister (regXMM2,"XMM2", xmm, bits64, 2);
		AddRegister (regXMM3,"XMM3", xmm, bits64, 3);
		AddRegister (regXMM4,"XMM4", xmm, bits64, 4);
		AddRegister (regXMM5,"XMM5", xmm, bits64, 5);
		AddRegister (regXMM6,"XMM6", xmm, bits64, 6);
		AddRegister (regXMM7,"XMM7", xmm, bits64, 7);
		AddRegister (regXMM8,"XMM8", xmm, bits64, 8);
		AddRegister (regXMM9,"XMM9", xmm, bits64, 9);
		AddRegister (regXMM10,"XMM10", xmm, bits64, 10);
		AddRegister (regXMM11,"XMM11", xmm, bits64, 11);
		AddRegister (regXMM12,"XMM12", xmm, bits64, 12);
		AddRegister (regXMM13,"XMM13", xmm, bits64, 13);
		AddRegister (regXMM14,"XMM14", xmm, bits64, 14);
		AddRegister (regXMM15,"XMM15", xmm, bits64, 15);

		AddRegister (regYMM0,"YMM0", ymm, bits64, 0);
		AddRegister (regYMM1,"YMM1", ymm, bits64, 1);
		AddRegister (regYMM2,"YMM2", ymm, bits64, 2);
		AddRegister (regYMM3,"YMM3", ymm, bits64, 3);
		AddRegister (regYMM4,"YMM4", ymm, bits64, 4);
		AddRegister (regYMM5,"YMM5", ymm, bits64, 5);
		AddRegister (regYMM6,"YMM6", ymm, bits64, 6);
		AddRegister (regYMM7,"YMM7", ymm, bits64, 7);
		AddRegister (regYMM8,"YMM8", ymm, bits64, 8);
		AddRegister (regYMM9,"YMM9", ymm, bits64, 9);
		AddRegister (regYMM10,"YMM10", ymm, bits64, 10);
		AddRegister (regYMM11,"YMM11", ymm, bits64, 11);
		AddRegister (regYMM12,"YMM12", ymm, bits64, 12);
		AddRegister (regYMM13,"YMM13", ymm, bits64, 13);
		AddRegister (regYMM14,"YMM14", ymm, bits64, 14);
		AddRegister (regYMM15,"YMM15", ymm, bits64, 15);

		AddRegister (regMMX0,"MMX0", mmx, bits128, 0);
		AddRegister (regMMX1,"MMX1", mmx, bits128, 1);
		AddRegister (regMMX2,"MMX2", mmx, bits128, 2);
		AddRegister (regMMX3,"MMX3", mmx, bits128, 3);
		AddRegister (regMMX4,"MMX4", mmx, bits128, 4);
		AddRegister (regMMX5,"MMX5", mmx, bits128, 5);
		AddRegister (regMMX6,"MMX6", mmx, bits128, 6);
		AddRegister (regMMX7,"MMX7", mmx, bits128, 7);

	END InitRegisters;

	(** setup CPU tables **)
	PROCEDURE InitCPUs;
		(* insert a new cpu type *)
		PROCEDURE AddCpu (CONST name: ARRAY OF CHAR; cpuoptions: SET);
		BEGIN
			COPY (name, cpus[cpuCount].name);
			cpus[cpuCount].cpuOptions := cpuoptions;
			INC (cpuCount);
		END AddCpu;
	BEGIN
		cpuCount := 0;
		AddCpu ("8086", {cpu8086});
		AddCpu ("186", {cpu8086, cpu186});
		AddCpu ("286", {cpu8086 .. cpu286});
		AddCpu ("386", {cpu8086 .. cpu386});
		AddCpu ("I386", {cpu8086 .. cpu386});
		AddCpu ("486", {cpu8086 .. cpu486});
		AddCpu ("I486", {cpu8086 .. cpu486});
		AddCpu ("586", {cpu8086 .. cpuPentium});
		AddCpu ("PENTIUM", {cpu8086 .. cpuPentium});
		AddCpu ("686", {cpu8086 .. cpuP6});
		AddCpu ("PPRO", {cpu8086 .. cpuP6});
		AddCpu ("PENTIUMPRO", {cpu8086 .. cpuP6});
		AddCpu ("P2", {cpu8086 .. cpuP6});
		AddCpu ("P3", {cpu8086 .. cpuKatmai});
		AddCpu ("KATMAI", {cpu8086 .. cpuKatmai});
		AddCpu ("P4", {cpu8086 .. cpuWillamette});
		AddCpu ("WILLAMETTE", {cpu8086 .. cpuWillamette});
		AddCpu ("PRESCOTT", {cpu8086 .. cpuPrescott});
		AddCpu ("AMD64", {cpu8086 .. cpuAMD64, cpuSSE, cpuSSE2, cpuSSE3, cpu3DNow, cpuMMX});

		AddCpu ("PRIVILEGED", {cpuPrivileged});
		AddCpu ("PROTECTED", {cpuProtected});
		AddCpu ("SSE", {cpuSSE});
		AddCpu ("SSE2", {cpuSSE2,cpuSSE});
		AddCpu ("SSE3", {cpuSSE3,cpuSSE2,cpuSSE});
		AddCpu ("3DNOW", {cpu3DNow});
		AddCpu ("MMX", {cpuMMX});
		AddCpu ("FPU", {cpuFPU});
	END InitCPUs;

	PROCEDURE Trace*;
	VAR instr,mnem: LONGINT; i: LONGINT;
	BEGIN
		FOR mnem := 0 TO numberMnemonics-1 DO
			KernelLog.String(mnemonics[mnem].name); KernelLog.Ln;
			FOR instr := mnemonics[mnem].firstInstruction TO mnemonics[mnem].lastInstruction DO
				KernelLog.Int(instr,5);
				KernelLog.String(" ");
				FOR i := 0 TO maxCodeLength-1 DO
					KernelLog.Hex(ORD(instructions[instr].code[i]),-2); KernelLog.String(" ");
				END;
				FOR i := 0 TO maxNumberOperands-1 DO
					KernelLog.Int(instructions[instr].operands[i],1); KernelLog.String(" ");
				END;
				KernelLog.Ln;
			END;
		END;
	END Trace;

BEGIN
	InitInstructions;
	InitRegisters;
	InitCPUs;
END FoxAMD64InstructionSet.

FoxAMD64InstructionSet.Trace

System.Free FoxAMD64InstructionSet ~

	(** Instruction Format, cf. [AMD:3], chapter 1
		[LegacyPrefix] ; Operand-Size Override / modify opcode of media instructions
		[LegacyPrefix] ; Address-Size Override
		[LegacyPrefix] ; Segment Override
		[LegacyPrefix] ; LOCK Prefix
		[LegacyPrefix] ; Repeat Prefixes
		[REXPrefix]; 7-4: 0100 3:W 2:R 1:X 0:B register modification (W) and extension bits (R-register X-index B-base)
		Opcode
		[Opcode]
		[Opcode]
		[ModRM]; 7:6:mod 5:3:reg  2:0:r/m (op code modifier, register, memory)
		[SIB]; 7:6 scale 5:3:index 2:0:base (scale, index, base)
		[Displacement]
		[Displacement]
		[Displacement]
		[Displacement]
		is a 64bit displacement possible ?
		[Immediate]
		[Immediate]
		[Immediate]
		[Immediate]
		[Immediate]; only for MOV instruction
		[Immediate]; only for MOV instruction
		[Immediate]; only for MOV instruction
		[Immediate]; only for MOV instruction

			Instruction = RECORD
		cpuoptions-: CnUOptions; (* necessary CPU options for the instruction to be available *)

		prefixFlags-: SET;
		numerLegacyPrefixes-: SHORTINT;
		legacyPrefixes-: ARRAY MaxLegacyPrefixes OF CHAR; (* legacy prefixes *)

		usedREXPrefix-:BOOLEAN;
		REXPrefix-:CHAR; (* REX prefix *)

		opcodeFlags-: SET;
		numberOpcodes-: SHORTINT; (* 1..MaxOpCodes *)
		opcode-: ARRAY MaxOpCodes OF CHAR;
		usedModRM-: BOOLEAN;
		ModRM: CHAR; (* mode-register-memory *)
		usedSIB_: BOOLEAN;
		SIB-: CHAR; (* scale-index-base *)

		numberOperands-: SHORTINT; (* 0.. MaxOperands *)
		operand-: ARRAY MaxOperands OF Operand;
	END;

	**)