A2OS/source/FoxAMD64InstructionSet.Mod

MODULE FoxAMD64InstructionSet; (**  AUTHOR "fof & fn"; PURPOSE "Oberon Compiler:AMD 64 Instruction Set";  **)
(* (c) fof ETH Zürich, 2008 *)

(** This module has been written with inspiration from
	-module CCIx86A.Mod : Component Compiler, Intel x86 Backend Assembler, 2005-2007, by Luc Bläser and
	-module AsmAMD64.Mod: AMD64 instruction set repository, 2006,  by Florian Negele
	The instruction set reference generator  is built by parsing the file InstructionSetAMD64.txt  also written by Florian Negele
	Parser for parsing the file is contained in FoxProgTools.Mod
**)

(** referenced literature
	[AMD:3] AMD64 Architecture Programmer's Manual Volume 3:General-Purpose and System Instructions

			Revision 3.14 September 2007
	[AMD:4] AMD64 Architecture Programmer's Manual Volume 4: 128-Bit Media Instructions
			Revision 3.14 September 2007
	[AMD:5] AMD64 Architecture Programmer's Manual Volume 5: 64-Bit Media and x87 Floating-Point Instructions
			Revision 3.14 September 2007
	[AMD:SSE5] AMD64 Technology 128-Bit SSE5 Instruction Set
			Revision 3.01 August 2007

	[INTEL:2A] Intel 64 and IA-32 Architectures Software Developer's Manual Volume 2A: Instruction Set Reference, A-M
			September 2008
	[INTEL:2B] Intel 64 and IA-32 Architectures Software Developer's Manual Volume 2B: Instruction Set Reference, N-Z
			September 2008
**)

IMPORT KernelLog (* debugging *);

CONST
	maxCPUs* = 30;
	maxNumberOperands*=3; (* maximal two source and one destination operand *)

	(* numbers generated by the instruction set parser *)
	maxNumberMnemonics = 586;
	maxNumberInstructions = 1380;
	maxMnemonicNameLength =12;
	maxCodeLength* =10;
	none* = -1;

	bitsDefault*=0;
	bits8*=1;
	bits16*=2;
	bits32*=4;
	bits64*=8;
	bits128*=16;

	(** cpu options **)
	cpu8086* = 0;
	cpu186* = 1;
	cpu286* = 2;
	cpu386* = 3;
	cpu486* = 4;
	cpuPentium* = 5;
	cpuP6* = 6;
	cpuKatmai* = 7;
	cpuWillamette* = 8;
	cpuPrescott* = 9;
	cpuAMD64* = 10;


	(** options selectable with CODE {SYSTEM.....} **)
	cpuPrivileged* = 20;
	cpuProtected* = 21;
	cpuSSE* = 22;
	cpuSSE2* = 23;
	cpuSSE3* = 24;
	cpu3DNow* = 25;
	cpuMMX* = 26;
	cpuFPU* = 27;

	cpuOptions* = {cpuPrivileged .. cpuFPU};

	(** instruction options **)
	optO16* = 0;	(* default 16bit operand size *)
	optO32* = 1;	(* default 32bit operand size *)
	optO64* = 2;	(* default 64bit operand size *)
	optD64* = 3;	(* default 64bit operand size in 64bit mode *)
	optNot64* = 4;		(* instruction invalid in 64bit mode *)
	optA16* = 5;	(* default 16bit address size *)
	optA32* = 6;	(* default 32bit address size *)

	optPOP* = 7;		(* an operand size override prefix must preceed the instruction *)
	optPLOCK* = 8;		(* a lock prefix must preceed the instruction *)
	optPREP* = 9;		(* a repeat prefix must preceed the instruction *)
	optPREPN* = 10;	(* a repeat prefix must preceed the instruction *)


	(*
		OCProgTools.Enum -l=1 -e
		(** operand types, numbers assigned to the types do not have a special meaning **)
		(* register classes first *)
		 reg8 reg16 reg32 reg64 CRn DRn segReg mmx xmm sti
		 (* other classes *)
		 mem imm ioffset pntr1616 pntr1632
		(* special registers *)
		 AL  AX  CL  CR8   CS   DS  DX  EAX  ECX  ES  FS  GS  RAX  SS rAX st0
		 (* immediates and memory locations *)
		 imm16  imm32  imm64  imm8
		 uimm16  uimm32  uimm8
		 simm16  simm32  simm8
		 mem128  mem16  mem32  mem64  mem8
		 moffset16  moffset32  moffset64  moffset8
		 rel16off  rel32off  rel8off
		(* ambivalent operand types *)
		 regmem16  regmem32  regmem64  regmem8
		 mmxmem32  mmxmem64
		 xmmmem128  xmmmem32  xmmmem64
		(* miscellaneous *)
		 one three
		 ~
	*)
	(** operand types, numbers assigned to the types do not have a special meaning **)
	(* register classes first *)
	reg8*= 0; (* GPR 8 *)
	reg16*= 1; (* GPR 16 *)
	reg32*= 2; (* GPR 32 *)
	reg64*= 3; (* GPR 64 *)
	CRn*= 4; (* counter registers *)
	DRn*= 5; (* debug registers *)
	segReg*= 6; (* segment registers *)
	mmx*= 7; (* 64bit mmx registers *)
	xmm*= 8; (* 128bit sse registers *)
	sti*= 9; (* floating point registers *)
	(* other classes *)
	mem*= 10; (* memory operands *)
	imm*= 11; (* immediate operands *)
	ioffset*= 12; (* used for MOV AL/AX/EAX/RAX   *)
	pntr1616*= 13;  (* used for far jumps and calls*)
	pntr1632*= 14;  (* used for far jumps and calls *)
	(* special registers *)
	AL*= 15;
	AX*= 16;
	CL*= 17;
	CR8*= 18;
	CS*= 19;
	DS*= 20;
	DX*= 21;
	EAX*= 22;
	ECX*= 23;
	ES*= 24;
	FS*= 25;
	GS*= 26;
	RAX*= 27;
	SS*= 28;
	rAX*= 29;
	st0*= 30;
	(* immediates and memory locations *)
	imm16*= 31;
	imm32*= 32;
	imm64*= 33;
	imm8*= 34;
	uimm16*= 35;
	uimm32*= 36;
	uimm8*= 37;
	simm16*= 38;
	simm32*= 39;
	simm8*= 40;
	mem128*= 41;
	mem16*= 42;
	mem32*= 43;
	mem64*= 44;
	mem8*= 45;
	moffset16*= 46;
	moffset32*= 47;
	moffset64*= 48;
	moffset8*= 49;
	rel16off*= 50;
	rel32off*= 51;
	rel8off*= 52;
	(* ambivalent operand types *)
	regmem16*= 53;
	regmem32*= 54;
	regmem64*= 55;
	regmem8*= 56;
	mmxmem32*= 57;
	mmxmem64*= 58;
	xmmmem128*= 59;
	xmmmem32*= 60;
	xmmmem64*= 61;
	(* miscellaneous *)
	one*= 62;
	three*= 63;

	(** prefixes **)
	prfOP* = 066H;
	prfADR* = 067H;
	prfCS* = 02EH;		(* ignored in 64bit mode *)
	prfDS* = 03EH;		(* ignored in 64bit mode *)
	prfES* = 026H;		(* ignored in 64bit mode *)
	prfFS* = 064H;
	prfGS* = 065H;
	prfSS* = 036H;		(* ignored in 64bit mode *)
	prfLOCK* = 0F0H;
	prfREP* = 0F3H;
	prfREPE* = 0F3H;
	prfREPZ* = 0F3H;
	prfREPNE* = 0F2H;
	prfREPNZ* = 0F2H;


	(* registers
		FoxProgTools.Enum -e -l=8 -s=0
		(** 8 bit general purpose registers **)
		regAL regCL regDL regBL  regAH regCH regDH regBH
		regSPL regBPL regSIL regDIL
		~
		FoxProgTools.Enum -e -l=16 -s=16
		regR8B regR9B regR10B regR11B regR12B regR13B regR14B regR15B
		~
		FoxProgTools.Enum -l=8 -e -s=32
		(** 16 bit general purpose registers **)
		regAX regCX regDX regBX regSP regBP regSI regDI
		regR8W regR9W regR10W regR11W regR12W regR13W regR14W regR15W
		~
		FoxProgTools.Enum -l=8 -e -s=64
		(** 32 bit general purpose registers **)
		regEAX regECX regEDX regEBX regESP regEBP regESI regEDI
		regR8D regR9D regR10D regR11D regR12D regR13D regR14D regR15D
		~
		FoxProgTools.Enum -l=8 -e -s=96
		(** 64 bit general purpose registers **)
		regRAX regRCX regRDX regRBX regRSP regRBP regRSI  regRDI
		regR8 regR9 regR10 regR11 regR12 regR13 regR14 regR15 regRIP
		~
		FoxProgTools.Enum -l=8 -e -s=128
		regES regCS regSS regDS regFS regGS
		regCR0 regCR1 regCR2 regCR3 regCR4 regCR5 regCR6 regCR7
		regCR8 regCR9 regCR10 regCR11 regCR12 regCR13 regCR14 regCR15
		regDR0 regDR1 regDR2 regDR3 regDR4 regDR5 regDR6 regDR7
		regDR8 regDR9 regDR10 regDR11 regDR12 regDR13 regDR14 regDR15
		regST0 regST1 regST2 regST3 regST4 regST5 regST6 regST7
		regXMM0 regXMM1 regXMM2 regXMM3 regXMM4 regXMM5 regXMM6 regXMM7
		regXMM8 regXMM9 regXMM10 regXMM11 regXMM12 regXMM13 regXMM14 regXMM15
		regMMX0 regMMX1 regMMX2 regMMX3 regMMX4 regMMX5 regMMX6 regMMX7
		regYMM0 regYMM1 regYMM2 regYMM3 regYMM4 regYMM5 regYMM6 regYMM7
		regYMM8 regYMM9 regYMM10 regYMM11 regYMM12 regYMM13 regYMM14 regYMM15

		numberRegisters
		~
	*)

		(*
			regNumber = S*32 + N

		N\S		0		1		2		3
		0			AL		AX		EAX	RAX
		1			CL		CX		ECX	RCX
		2			DL		DX		EDX	RDX
		3			BL		BX		EBX	RBX
		4			SPL		SP		ESP		RSP
		5			BPL		BP		EBP	RBP
		6			SIL		SI		ESI		RSI
		7			DIL		DI		EDI		RDI
		8			R8B	R8W	R8D	R8
		9			R9B	R9W	R9D	R9
		10			R10B	R10W	R10D	R10
		11			R11B	R11W	R11D	R11
		12			R12B	R12W	R12D	R12
		13			R13B	R13W	R13D	R13
		14			R14B	R14W	R14D	R14
		15			R15B	R15W	R15D	R15
		16			AH
		17			CH
		18			BH
		19			DH


		*)

	(** register indices, the order is arbitrary and has no meaning for instruction encoding,
	it nevertheless should not be changed as the numbers are important on in the code generator !  **)
	(** 8 bit general purpose registers : index DIV 32 = 0**)
	regAL*= 0; regCL*= 1; regDL*= 2; regBL*= 3; regSPL*= 4; regBPL*= 5; regSIL*= 6; regDIL*= 7;
	regAH*= 16; regCH*= 17; regDH*= 18; regBH*= 19;
	regR8B*= 8; regR9B*= 9; regR10B*= 10; regR11B*= 11; regR12B*= 12; regR13B*= 13; regR14B*= 14; regR15B*= 15;
	(** 16 bit general purpose registers : index DIV 32 = 1**)
	regAX*= 32; regCX*= 33; regDX*= 34; regBX*= 35; regSP*= 36; regBP*= 37; regSI*= 38; regDI*= 39;
	regR8W*= 40; regR9W*= 41; regR10W*= 42; regR11W*= 43; regR12W*= 44; regR13W*= 45; regR14W*= 46; regR15W*= 47;
	(** 32 bit general purpose registers: index DIV 32 = 2 **)
	regEAX*= 64; regECX*= 65; regEDX*= 66; regEBX*= 67; regESP*= 68; regEBP*= 69; regESI*= 70; regEDI*= 71;
	regR8D*= 72; regR9D*= 73; regR10D*= 74; regR11D*= 75; regR12D*= 76; regR13D*= 77; regR14D*= 78; regR15D*= 79;
	(** 64 bit general purpose registers : index DIV 32 = 3 (except for regRIP) **)
	regRAX*= 96; regRCX*= 97; regRDX*= 98; regRBX*= 99; regRSP*= 100; regRBP*= 101; regRSI*= 102; regRDI*= 103;
	regR8*= 104; regR9*= 105; regR10*= 106; regR11*= 107; regR12*= 108; regR13*= 109; regR14*= 110; regR15*= 111;
	regRIP*= 112;
	(** other registers **)
	regES*= 128; regCS*= 129; regSS*= 130; regDS*= 131; regFS*= 132; regGS*= 133; regCR0*= 134; regCR1*= 135;
	regCR2*= 136; regCR3*= 137; regCR4*= 138; regCR5*= 139; regCR6*= 140; regCR7*= 141; regCR8*= 142; regCR9*= 143;
	regCR10*= 144; regCR11*= 145; regCR12*= 146; regCR13*= 147; regCR14*= 148; regCR15*= 149; regDR0*= 150; regDR1*= 151;
	regDR2*= 152; regDR3*= 153; regDR4*= 154; regDR5*= 155; regDR6*= 156; regDR7*= 157; regDR8*= 158; regDR9*= 159;
	regDR10*= 160; regDR11*= 161; regDR12*= 162; regDR13*= 163; regDR14*= 164; regDR15*= 165; regST0*= 166; regST1*= 167;
	regST2*= 168; regST3*= 169; regST4*= 170; regST5*= 171; regST6*= 172; regST7*= 173; regXMM0*= 174; regXMM1*= 175;
	regXMM2*= 176; regXMM3*= 177; regXMM4*= 178; regXMM5*= 179; regXMM6*= 180; regXMM7*= 181; regXMM8*= 182; regXMM9*= 183;
	regXMM10*= 184; regXMM11*= 185; regXMM12*= 186; regXMM13*= 187; regXMM14*= 188; regXMM15*= 189; regMMX0*= 190; regMMX1*= 191;
	regMMX2*= 192; regMMX3*= 193; regMMX4*= 194; regMMX5*= 195; regMMX6*= 196; regMMX7*= 197; numberRegisters*= 198;

VAR 
	opAAA*,
	opAAD*,
	opAAM*,
	opAAS*,
	opADC*,
	opADD*,
	opADDPD*,
	opADDPS*,
	opADDSD*,
	opADDSS*,
	opADDSUBPD*,
	opADDSUBPS*,
	opAND*,
	opANDNPD*,
	opANDNPS*,
	opANDPD*,
	opANDPS*,
	opARPL*,
	opBOUND*,
	opBSF*,
	opBSR*,
	opBSWAP*,
	opBT*,
	opBTC*,
	opBTR*,
	opBTS*,
	opCALL*,
	opCALLFAR*,
	opCBW*,
	opCDQ*,
	opCDQE*,
	opCLC*,
	opCLD*,
	opCLFLUSH*,
	opCLGI*,
	opCLI*,
	opCLTS*,
	opCMC*,
	opCMOVA*,
	opCMOVAE*,
	opCMOVB*,
	opCMOVBE*,
	opCMOVC*,
	opCMOVE*,
	opCMOVG*,
	opCMOVGE*,
	opCMOVL*,
	opCMOVLE*,
	opCMOVNA*,
	opCMOVNAE*,
	opCMOVNB*,
	opCMOVNBE*,
	opCMOVNC*,
	opCMOVNE*,
	opCMOVNG*,
	opCMOVNGE*,
	opCMOVNL*,
	opCMOVNLE*,
	opCMOVNO*,
	opCMOVNP*,
	opCMOVNS*,
	opCMOVNZ*,
	opCMOVO*,
	opCMOVP*,
	opCMOVPE*,
	opCMOVPO*,
	opCMOVS*,
	opCMOVZ*,
	opCMP*,
	opCMPPD*,
	opCMPPS*,
	opCMPS*,
	opCMPSB*,
	opCMPSD*,
	opCMPSQ*,
	opCMPSS*,
	opCMPSW*,
	opCMPXCHG*,
	opCMPXCHG16B*,
	opCMPXCHG8B*,
	opCOMISD*,
	opCOMISS*,
	opCPUID*,
	opCQO*,
	opCVTDQ2PD*,
	opCVTDQ2PS*,
	opCVTPD2DQ*,
	opCVTPD2PI*,
	opCVTPD2PS*,
	opCVTPI2PD*,
	opCVTPI2PS*,
	opCVTPS2DQ*,
	opCVTPS2PD*,
	opCVTPS2PI*,
	opCVTSD2SI*,
	opCVTSD2SS*,
	opCVTSI2SD*,
	opCVTSI2SS*,
	opCVTSS2SD*,
	opCVTSS2SI*,
	opCVTTPD2DQ*,
	opCVTTPD2PI*,
	opCVTTPS2DQ*,
	opCVTTPS2PI*,
	opCVTTSD2SI*,
	opCVTTSS2SI*,
	opCWD*,
	opCWDE*,
	opDAA*,
	opDAS*,
	opDEC*,
	opDIV*,
	opDIVPD*,
	opDIVPS*,
	opDIVSD*,
	opDIVSS*,
	opEMMS*,
	opENTER*,
	opF2XM1*,
	opFABS*,
	opFADD*,
	opFADDP*,
	opFBLD*,
	opFBSTP*,
	opFCHS*,
	opFCLEX*,
	opFCMOVB*,
	opFCMOVBE*,
	opFCMOVE*,
	opFCMOVNB*,
	opFCMOVNBE*,
	opFCMOVNE*,
	opFCMOVNU*,
	opFCMOVU*,
	opFCOM*,
	opFCOMI*,
	opFCOMIP*,
	opFCOMP*,
	opFCOMPP*,
	opFCOS*,
	opFDECSTP*,
	opFDIV*,
	opFDIVP*,
	opFDIVR*,
	opFDIVRP*,
	opFEMMS*,
	opFFREE*,
	opFIADD*,
	opFICOM*,
	opFICOMP*,
	opFIDIV*,
	opFIDIVR*,
	opFILD*,
	opFIMUL*,
	opFINCSTP*,
	opFINIT*,
	opFIST*,
	opFISTP*,
	opFISTTP*,
	opFISUB*,
	opFISUBR*,
	opFLD*,
	opFLD1*,
	opFLDCW*,
	opFLDENV*,
	opFLDL2E*,
	opFLDL2T*,
	opFLDLG2*,
	opFLDLN2*,
	opFLDPI*,
	opFLDZ*,
	opFMUL*,
	opFMULP*,
	opFNCLEX*,
	opFNINIT*,
	opFNOP*,
	opFNSAVE*,
	opFNSTCW*,
	opFNSTENV*,
	opFNSTSW*,
	opFPATAN*,
	opFPREM*,
	opFPREM1*,
	opFPTAN*,
	opFRNDINT*,
	opFRSTOR*,
	opFSAVE*,
	opFSCALE*,
	opFSIN*,
	opFSINCOS*,
	opFSQRT*,
	opFST*,
	opFSTCW*,
	opFSTENV*,
	opFSTP*,
	opFSTSW*,
	opFSUB*,
	opFSUBP*,
	opFSUBR*,
	opFSUBRP*,
	opFTST*,
	opFUCOM*,
	opFUCOMI*,
	opFUCOMIP*,
	opFUCOMP*,
	opFUCOMPP*,
	opFWAIT*,
	opFXAM*,
	opFXCH*,
	opFXRSTOR*,
	opFXSAVE*,
	opFXTRACT*,
	opFYL2X*,
	opFYL2XP1*,
	opHADDPD*,
	opHADDPS*,
	opHLT*,
	opHSUBPD*,
	opHSUBPS*,
	opIDIV*,
	opIMUL*,
	opIN*,
	opINC*,
	opINS*,
	opINSB*,
	opINSD*,
	opINSW*,
	opINT*,
	opINT3*,
	opINTO*,
	opINVD*,
	opINVLPG*,
	opINVLPGA*,
	opIRET*,
	opIRETD*,
	opIRETQ*,
	opJA*,
	opJAE*,
	opJB*,
	opJBE*,
	opJC*,
	opJCXZ*,
	opJE*,
	opJECXZ*,
	opJG*,
	opJGE*,
	opJL*,
	opJLE*,
	opJMP*,
	opJMPFAR*,
	opJNA*,
	opJNAE*,
	opJNB*,
	opJNBE*,
	opJNC*,
	opJNE*,
	opJNG*,
	opJNGE*,
	opJNL*,
	opJNLE*,
	opJNO*,
	opJNP*,
	opJNS*,
	opJNZ*,
	opJO*,
	opJP*,
	opJPE*,
	opJPO*,
	opJRCXZ*,
	opJS*,
	opJZ*,
	opLAHF*,
	opLAR*,
	opLDDQU*,
	opLDMXCSR*,
	opLDS*,
	opLEA*,
	opLEAVE*,
	opLES*,
	opLFENCE*,
	opLFS*,
	opLGDT*,
	opLGS*,
	opLIDT*,
	opLLDT*,
	opLMSW*,
	opLODS*,
	opLODSB*,
	opLODSD*,
	opLODSQ*,
	opLODSW*,
	opLOOP*,
	opLOOPE*,
	opLOOPNE*,
	opLOOPNZ*,
	opLOOPZ*,
	opLSL*,
	opLSS*,
	opLTR*,
	opMASKMOVDQU*,
	opMASKMOVQ*,
	opMAXPD*,
	opMAXPS*,
	opMAXSD*,
	opMAXSS*,
	opMFENCE*,
	opMINPD*,
	opMINPS*,
	opMINSD*,
	opMINSS*,
	opMOV*,
	opMOVAPD*,
	opMOVAPS*,
	opMOVD*,
	opMOVDDUP*,
	opMOVDQ2Q*,
	opMOVDQA*,
	opMOVDQU*,
	opMOVHLPS*,
	opMOVHPD*,
	opMOVHPS*,
	opMOVLHPS*,
	opMOVLPD*,
	opMOVLPS*,
	opMOVMSKPD*,
	opMOVMSKPS*,
	opMOVNTDQ*,
	opMOVNTI*,
	opMOVNTPD*,
	opMOVNTPS*,
	opMOVNTQ*,
	opMOVQ*,
	opMOVQ2DQ*,
	opMOVS*,
	opMOVSB*,
	opMOVSD*,
	opMOVSHDUP*,
	opMOVSLDUP*,
	opMOVSQ*,
	opMOVSS*,
	opMOVSW*,
	opMOVSX*,
	opMOVSXD*,
	opMOVUPD*,
	opMOVUPS*,
	opMOVZX*,
	opMUL*,
	opMULPD*,
	opMULPS*,
	opMULSD*,
	opMULSS*,
	opNEG*,
	opNOP*,
	opNOT*,
	opOR*,
	opORPD*,
	opORPS*,
	opOUT*,
	opOUTS*,
	opOUTSB*,
	opOUTSD*,
	opOUTSW*,
	opPACKSSDW*,
	opPACKSSWB*,
	opPACKUSWB*,
	opPADDB*,
	opPADDD*,
	opPADDQ*,
	opPADDSB*,
	opPADDSW*,
	opPADDUSB*,
	opPADDUSW*,
	opPADDW*,
	opPAND*,
	opPANDN*,
	opPAUSE*,
	opPAVGB*,
	opPAVGUSB*,
	opPAVGW*,
	opPCMPEQB*,
	opPCMPEQD*,
	opPCMPEQW*,
	opPCMPGTB*,
	opPCMPGTD*,
	opPCMPGTW*,
	opPEXTRW*,
	opPF2ID*,
	opPF2IW*,
	opPFACC*,
	opPFADD*,
	opPFCMPEQ*,
	opPFCMPGE*,
	opPFCMPGT*,
	opPFMAX*,
	opPFMIN*,
	opPFMUL*,
	opPFNACC*,
	opPFPNACC*,
	opPFRCP*,
	opPFRCPIT1*,
	opPFRCPIT2*,
	opPFRSQIT1*,
	opPFRSQRT*,
	opPFSUB*,
	opPFSUBR*,
	opPI2FD*,
	opPI2FW*,
	opPINSRW*,
	opPMADDWD*,
	opPMAXSW*,
	opPMAXUB*,
	opPMINSW*,
	opPMINUB*,
	opPMOVMSKB*,
	opPMULHRW*,
	opPMULHUW*,
	opPMULHW*,
	opPMULLW*,
	opPMULUDQ*,
	opPOP*,
	opPOPA*,
	opPOPAD*,
	opPOPAW*,
	opPOPF*,
	opPOPFD*,
	opPOPFQ*,
	opPOR*,
	opPREFETCH*,
	opPREFETCHNTA*,
	opPREFETCHT0*,
	opPREFETCHT1*,
	opPREFETCHT2*,
	opPREFETCHW*,
	opPSADBW*,
	opPSHUFD*,
	opPSHUFHW*,
	opPSHUFLW*,
	opPSHUFW*,
	opPSLLD*,
	opPSLLDQ*,
	opPSLLQ*,
	opPSLLW*,
	opPSRAD*,
	opPSRAW*,
	opPSRLD*,
	opPSRLDQ*,
	opPSRLQ*,
	opPSRLW*,
	opPSUBB*,
	opPSUBD*,
	opPSUBQ*,
	opPSUBSB*,
	opPSUBSW*,
	opPSUBUSB*,
	opPSUBUSW*,
	opPSUBW*,
	opPSWAPD*,
	opPUNPCKHBW*,
	opPUNPCKHDQ*,
	opPUNPCKHQDQ*,
	opPUNPCKHWD*,
	opPUNPCKLBW*,
	opPUNPCKLDQ*,
	opPUNPCKLQDQ*,
	opPUNPCKLWD*,
	opPUSH*,
	opPUSHA*,
	opPUSHAD*,
	opPUSHF*,
	opPUSHFD*,
	opPUSHFQ*,
	opPXOR*,
	opRCL*,
	opRCPPS*,
	opRCPSS*,
	opRCR*,
	opRDMSR*,
	opRDPMC*,
	opRDTSC*,
	opRDTSCP*,
	opRET*,
	opRETF*,
	opROL*,
	opROR*,
	opRSM*,
	opRSQRTPS*,
	opRSQRTSS*,
	opSAHF*,
	opSAL*,
	opSAR*,
	opSBB*,
	opSCAS*,
	opSCASB*,
	opSCASD*,
	opSCASQ*,
	opSCASW*,
	opSETA*,
	opSETAE*,
	opSETB*,
	opSETBE*,
	opSETC*,
	opSETE*,
	opSETG*,
	opSETGE*,
	opSETL*,
	opSETLE*,
	opSETNA*,
	opSETNAE*,
	opSETNB*,
	opSETNBE*,
	opSETNC*,
	opSETNE*,
	opSETNG*,
	opSETNGE*,
	opSETNL*,
	opSETNLE*,
	opSETNO*,
	opSETNP*,
	opSETNS*,
	opSETNZ*,
	opSETO*,
	opSETP*,
	opSETPE*,
	opSETPO*,
	opSETS*,
	opSETZ*,
	opSFENCE*,
	opSGDT*,
	opSHL*,
	opSHLD*,
	opSHR*,
	opSHRD*,
	opSHUFPD*,
	opSHUFPS*,
	opSIDT*,
	opSKINIT*,
	opSLDT*,
	opSMSW*,
	opSQRTPD*,
	opSQRTPS*,
	opSQRTSD*,
	opSQRTSS*,
	opSTC*,
	opSTD*,
	opSTGI*,
	opSTI*,
	opSTMXCSR*,
	opSTOS*,
	opSTOSB*,
	opSTOSD*,
	opSTOSQ*,
	opSTOSW*,
	opSTR*,
	opSUB*,
	opSUBPD*,
	opSUBPS*,
	opSUBSD*,
	opSUBSS*,
	opSWAPGS*,
	opSYSCALL*,
	opSYSENTER*,
	opSYSEXIT*,
	opSYSRET*,
	opTEST*,
	opUCOMISD*,
	opUCOMISS*,
	opUD2*,
	opUNPCKHPD*,
	opUNPCKHPS*,
	opUNPCKLPD*,
	opUNPCKLPS*,
	opVERR*,
	opVERW*,
	opVMLOAD*,
	opVMMCALL*,
	opVMRUN*,
	opVMSAVE*,
	opWBINVD*,
	opWRMSR*,
	opXADD*,
	opXCHG*,
	opXLAT*,
	opXLATB*,
	opXOR*,
	opXORPD*,
	opXORPS*: LONGINT

	(*
		FoxProgTools.Enum -l=8 -e
			opCode
			modRMExtension
			modRMBoth
			cb cw cd cp
			ib iw id iq
			rb rw rd rq
			mem64Operand mem128Operand
			fpStackOperand
			directMemoryOffset
		~
	*)
CONST
	(* opcode flags, cf [AMD:3], pp. 39-40 *)
	opCode*= 0; modRMExtension*= 1; modRMBoth*= 2; cb*= 3; cw*= 4; cd*= 5; cp*= 6; ib*= 7;
	iw*= 8; id*= 9; iq*= 10; rb*= 11; rw*= 12; rd*= 13; rq*= 14; mem64Operand*= 15;
	mem128Operand*= 16; fpStackOperand*= 17; directMemoryOffset*= 18;

TYPE
	Name = ARRAY 20 OF CHAR;
	OperandType* = SHORTINT;
	CPUOptions*= SET;
	Code*=CHAR; (* should be unsigned -- for emitter *)

	Instruction* = RECORD
		code-: ARRAY maxCodeLength OF Code; (* for the encoding cd. InitInstructions.Encode *)

		operands-: ARRAY maxNumberOperands OF OperandType;

		bitwidthOptions-: SET;
		cpuOptions-: SET;
	END;

	Mnemonic* = RECORD
		name-: ARRAY maxMnemonicNameLength OF CHAR;
		firstInstruction-, lastInstruction-: LONGINT;
	END;

	CPUType* = RECORD
		name-: Name;
		cpuOptions-: SET;
	END;

	Register*  = RECORD
		name-: Name; (* name for debug output and for an assembler *)
		type-: OperandType; (* can be one of reg8, reg16, reg32, reg64, CRn, DRn, segReg, mmx, xmm, sti
								the particular value of reg8 ... sti does not have a meaning *)
		index-: SHORTINT; (* this index has a meaning for instruction encoding, it is the register index used in the instruction *)
		sizeInBytes-: SHORTINT; (* size in bytes *)
	END;

VAR
	(* repository *)
	mnemonics-: ARRAY maxNumberMnemonics OF Mnemonic;
	numberMnemonics: LONGINT;
	
	instructions-: ARRAY maxNumberInstructions OF Instruction;
	numberInstructions: LONGINT; 
	
	registers-: ARRAY numberRegisters OF Register;
	registersByClass-: ARRAY sti+1 OF ARRAY 17 OF LONGINT;

	cpus-: ARRAY maxCPUs OF CPUType;
	cpuCount: LONGINT;


	(* perform a binary search for the index of the specified mnemonic *)
	PROCEDURE FindMnemonic* (CONST mnem: ARRAY OF CHAR): LONGINT;
	VAR l, r, m: LONGINT;
	BEGIN
		l := 0;
		r := numberMnemonics;
		WHILE l # r DO
			m := (l + r) DIV 2;
			IF mnem < mnemonics[m].name THEN r := m;
			ELSIF mnem > mnemonics[m].name THEN l := m + 1;
			ELSE RETURN m;
			END
		END;
		RETURN none;
	END FindMnemonic;

	(* search for the register name and return it's index *)
	PROCEDURE FindRegister* (CONST reg: ARRAY OF CHAR): LONGINT;
	VAR i: LONGINT;
	BEGIN
		FOR i := 0 TO numberRegisters - 1 DO
			IF registers[i].name = reg THEN RETURN i END;
		END;
		RETURN none;
	END FindRegister;

	PROCEDURE RegisterType*(regNumber: LONGINT): OperandType;
	BEGIN IF regNumber = none THEN RETURN none ELSE RETURN registers[regNumber].type END
	END RegisterType;

	PROCEDURE RegisterIndex*(regNumber: LONGINT): SHORTINT;
	BEGIN IF regNumber = none THEN RETURN none ELSE RETURN registers[regNumber].index END
	END RegisterIndex;

	(* search for the CPU name and return it's index *)
	PROCEDURE FindCPU* (CONST cpu: ARRAY OF CHAR): LONGINT;
	VAR i: LONGINT;
	BEGIN
		FOR i := 0 TO cpuCount - 1 DO
			IF cpus[i].name = cpu THEN RETURN i END;
		END;
		RETURN none;
	END FindCPU;

	(** setup instruction and mnemonic tables **)
	PROCEDURE InitInstructions;
	VAR 

		PROCEDURE StartMnemonic(VAR op: LONGINT; CONST name: ARRAY OF CHAR);
		BEGIN
			op := numberMnemonics;
			INC(numberMnemonics);
			COPY (name, mnemonics[op].name);
			mnemonics[op].firstInstruction := numberInstructions;
		END StartMnemonic;

		PROCEDURE HexOrd (ch: CHAR): INTEGER;
		BEGIN
			IF ch <= "9" THEN RETURN ORD (ch) - ORD ("0")
			ELSE RETURN ORD (CAP (ch)) - ORD ("A") + 10
			END
		END HexOrd;

		PROCEDURE Encode(CONST charcode: ARRAY OF CHAR; VAR code: ARRAY OF Code);
		(* simple encoding:
			code =
			{
			opCode number
			|modRMBoth
			|modRMExtension number
			|cb|cw|cd|cp
			|ib|iw|id|iq
			|m6|m1
			|+i|+o
			|rb|rw|rd|rq
			}
			none
			{
			none
			}

			all symbols 8 bit wide, numbers also 8 bits wide
		*)
		VAR i,k,length: SHORTINT; ch1,ch2: CHAR;
		BEGIN
			i := 0; k := 0;
			WHILE(charcode[2*i] # 0X) DO
				ch1 := charcode[2*i];
				ch2 := charcode[2*i+1];
				CASE ch1 OF
					'0'..'9','A'..'F':
						CASE ch2 OF '0'..'9','A'..'F':
							code[k] := CHR(opCode);INC(k);
							code[k] := CHR(HexOrd(ch1)*10H+HexOrd(ch2)); INC(k);
						ELSE HALT(100)
						END;
					|'/':
						CASE ch2 OF
							'r': code[k] := CHR(modRMBoth); INC(k);
							|'0'..'7': code[k] := CHR(modRMExtension); INC(k); code[k] := CHR(HexOrd(ch2)); INC(k);
						ELSE HALT(100)
						END;
					|'c':
						CASE ch2 OF
							'b': code[k] := CHR(cb); INC(k);
							|'w': code[k] := CHR(cw); INC(k);
							|'d': code[k] := CHR(cd); INC(k);
							|'p': code[k] := CHR(cp); INC(k);
						ELSE HALT(100)
						END;
					|'i':
						CASE ch2 OF
							'b': code[k] := CHR(ib); INC(k);
							|'w': code[k] := CHR(iw); INC(k);
							|'d': code[k] := CHR(id); INC(k);
							|'q': code[k] := CHR(iq); INC(k);
						ELSE HALT(100)
						END;
					|'m':
						CASE ch2 OF
							'6': code[k] := CHR(mem64Operand); INC(k);
							|'1': code[k] := CHR(mem128Operand); INC(k);
						ELSE HALT(100)
						END;
					|'+':
						CASE ch2 OF
							'i': code[k] := CHR(fpStackOperand); INC(k);
							|'o': code[k] := CHR(directMemoryOffset); INC(k);
						ELSE HALT(100)
						END;
					|'r':
						CASE ch2 OF
							'b': code[k] := CHR(rb); INC(k);
							|'w': code[k] := CHR(rw); INC(k);
							|'d': code[k] := CHR(rd); INC(k);
							|'q': code[k] := CHR(rq); INC(k);
						ELSE HALT(100)
						END;
					ELSE HALT(100)
					END;
				INC(i);
			END;
			length := k;
			WHILE(k < LEN(code)) DO
				code[k] := CHR(none);
				INC(k);
			END;
		END Encode;


		PROCEDURE AddInstruction(CONST op,code: ARRAY OF CHAR; bitwidthOptions, cpuOptions: SET);
		VAR i: SHORTINT; at: LONGINT;
		
			PROCEDURE StringToOperand(CONST name: ARRAY OF CHAR): SHORTINT;
			BEGIN
				IF name = "" THEN RETURN none
				ELSIF name = "1" THEN RETURN one;
				ELSIF name = "3" THEN RETURN three;
				ELSIF name = "reg8" THEN RETURN reg8;
				ELSIF name = "reg16" THEN RETURN reg16;
				ELSIF name = "reg32" THEN RETURN reg32;
				ELSIF name = "reg64" THEN RETURN reg64;
				ELSIF name = "CRn" THEN RETURN CRn
				ELSIF name = "DRn" THEN RETURN DRn
				ELSIF name = "segReg" THEN RETURN segReg
				ELSIF name = "mmx" THEN RETURN mmx
				ELSIF name = "xmm" THEN RETURN xmm
				ELSIF name = "mem" THEN RETURN mem
				ELSIF name = "imm" THEN RETURN imm
				ELSIF name = "ioffset" THEN RETURN ioffset
				ELSIF name = "pntr1616" THEN RETURN pntr1616
				ELSIF name = "pntr1632" THEN RETURN pntr1632
				ELSIF name = "AL" THEN RETURN AL;
				ELSIF name = "AX" THEN RETURN AX;
				ELSIF name = "CL" THEN RETURN CL;
				ELSIF name = "CR8" THEN RETURN CR8;
				ELSIF name = "CS" THEN RETURN CS;
				ELSIF name = "DS" THEN RETURN DS;
				ELSIF name = "DX" THEN RETURN DX;
				ELSIF name = "EAX" THEN RETURN EAX;
				ELSIF name = "ECX" THEN RETURN ECX;
				ELSIF name = "ES" THEN RETURN ES;
				ELSIF name = "FS" THEN RETURN FS;
				ELSIF name = "GS" THEN RETURN GS;
				ELSIF name = "RAX" THEN RETURN RAX;
				ELSIF name = "SS" THEN RETURN SS;
				ELSIF name = "rAX" THEN RETURN rAX;
				ELSIF name = "ST(0)" THEN RETURN st0;
				ELSIF name = "ST(i)" THEN RETURN sti;
				ELSIF name = "imm16" THEN RETURN imm16
				ELSIF name = "imm32" THEN RETURN imm32;
				ELSIF name = "imm64" THEN RETURN imm64
				ELSIF name = "imm8" THEN RETURN imm8
				ELSIF name = "uimm16" THEN RETURN uimm16
				ELSIF name = "uimm32" THEN RETURN uimm32
				ELSIF name = "uimm8" THEN RETURN uimm8
				ELSIF name = "simm16" THEN RETURN simm16
				ELSIF name = "simm32" THEN RETURN simm32
				ELSIF name = "simm8" THEN RETURN simm8
				ELSIF name = "mem128" THEN RETURN mem128
				ELSIF name = "mem16" THEN RETURN mem16
				ELSIF name = "mem32" THEN RETURN mem32
				ELSIF name = "mem64" THEN RETURN mem64
				ELSIF name = "mem8" THEN RETURN mem8
				ELSIF name = "moffset16" THEN RETURN moffset16
				ELSIF name = "moffset32" THEN RETURN moffset32
				ELSIF name = "moffset64" THEN RETURN moffset64
				ELSIF name = "moffset8" THEN RETURN moffset8
				ELSIF name = "rel16off" THEN RETURN rel16off
				ELSIF name = "rel32off" THEN RETURN rel32off
				ELSIF name = "rel8off" THEN RETURN rel8off
				ELSIF name = "reg/mem8" THEN RETURN regmem8;
				ELSIF name = "reg/mem16" THEN RETURN regmem16;
				ELSIF name = "reg/mem32" THEN RETURN regmem32;
				ELSIF name = "reg/mem64" THEN RETURN regmem64;
				ELSIF name = "mem14/28env" THEN RETURN mem;
				ELSIF name = "mem16&mem16" THEN RETURN mem;
				ELSIF name = "mem32&mem32" THEN RETURN mem;
				ELSIF name = "mem16:16" THEN RETURN mem;
				ELSIF name = "mem16:32" THEN RETURN mem;
				ELSIF name = "mem16:64" THEN RETURN mem;
				ELSIF name = "mem512env" THEN RETURN mem;
				ELSIF name = "mem80dec" THEN RETURN mem;
				ELSIF name = "mem80real" THEN RETURN mem;
				ELSIF name = "mem94/108env" THEN RETURN mem;
				ELSIF name = "mem2env" THEN RETURN mem16;
				ELSIF name = "xmm1" THEN RETURN xmm;
				ELSIF name = "xmm2" THEN RETURN xmm;
				ELSIF name = "xmm/mem32" THEN RETURN xmmmem32;
				ELSIF name = "xmm/mem64" THEN RETURN xmmmem64;
				ELSIF name = "xmm/mem128" THEN RETURN xmmmem128;
				ELSIF name = "xmm1/mem32" THEN RETURN xmmmem32;
				ELSIF name = "xmm1/mem64" THEN RETURN xmmmem64;
				ELSIF name = "xmm1/mem128" THEN RETURN xmmmem128;
				ELSIF name = "xmm2/mem32" THEN RETURN xmmmem32;
				ELSIF name = "xmm2/mem64" THEN RETURN xmmmem64;
				ELSIF name = "xmm2/mem128" THEN RETURN xmmmem128;
				ELSIF name = "mmx/mem64" THEN RETURN mmxmem64;
				ELSIF name = "mmx1" THEN RETURN mmx;
				ELSIF name = "mmx2" THEN RETURN mmx;
				ELSIF name = "mmx1/mem64" THEN RETURN mmxmem64;
				ELSIF name = "mmx2/mem32" THEN RETURN mmxmem32;
				ELSIF name = "mmx2/mem64" THEN RETURN mmxmem64;
				ELSIF name = "pntr16:16" THEN RETURN pntr1616;
				ELSIF name = "pntr16:32" THEN RETURN pntr1632;
				ELSIF name = "mem16int" THEN RETURN mem16;
				ELSIF name = "mem32int" THEN RETURN mem32;
				ELSIF name = "mem32real" THEN RETURN mem32;
				ELSIF name = "mem64int" THEN RETURN mem64;
				ELSIF name = "mem64real" THEN RETURN mem64;
				ELSE HALT(200) 
				END;
			END StringToOperand;
		
			PROCEDURE ParseOperand(CONST op: ARRAY OF CHAR; VAR at: LONGINT): SHORTINT;
			VAR name: ARRAY 32 OF CHAR; i: LONGINT;
			BEGIN
				i := 0; 
				WHILE(op[at] # 0X) & (op[at] # ",") DO
					name[i] := op[at];
					INC(i); INC(at); 
				END;
				name[i] := 0X;
				IF op[at] = "," THEN INC(at) END;
				RETURN StringToOperand(name); 
			END ParseOperand;
			
		BEGIN
			i := 0; at := 0;
			WHILE (i<maxNumberOperands) DO
				instructions[numberInstructions].operands[i] := ParseOperand(op,at);
				INC(i);
			END;
			Encode(code,instructions[numberInstructions].code);

			instructions[numberInstructions].bitwidthOptions := bitwidthOptions;
			instructions[numberInstructions].cpuOptions := cpuOptions;

			mnemonics[numberMnemonics-1].lastInstruction := numberInstructions;
			
			INC(numberInstructions);
		END AddInstruction;


	(* the following has been generated with
		FoxProgTools.ParseAMDInstructionSet FoxInstructionSetAMD64TabSeperated.txt ~

		Do not change or re-order. The alphabetical order is of importance
	*)


	BEGIN
		numberMnemonics := 0; 
		numberInstructions := 0; 

		StartMnemonic(opAAA, "AAA");
		AddInstruction("", "37", {optNot64}, {cpu8086});

		StartMnemonic(opAAD, "AAD");
		AddInstruction("", "D50A", {optNot64}, {cpu8086});
		AddInstruction("", "D5ib", {optNot64}, {cpu8086});

		StartMnemonic(opAAM, "AAM");
		AddInstruction("", "D40A", {optNot64}, {cpu8086});
		AddInstruction("", "D4ib", {optNot64}, {cpu8086});

		StartMnemonic(opAAS, "AAS");
		AddInstruction("", "3F", {optNot64}, {cpu8086});

		StartMnemonic(opADC, "ADC");
		AddInstruction("reg/mem8,reg8", "10/r", {}, {cpu8086});
		AddInstruction("reg/mem16,reg16", "11/r", {optO16}, {cpu8086});
		AddInstruction("reg/mem32,reg32", "11/r", {optO32}, {cpu386});
		AddInstruction("reg/mem64,reg64", "11/r", {}, {cpuAMD64});
		AddInstruction("reg8,reg/mem8", "12/r", {}, {cpu8086});
		AddInstruction("reg16,reg/mem16", "13/r", {optO16}, {cpu8086});
		AddInstruction("reg32,reg/mem32", "13/r", {optO32}, {cpu386});
		AddInstruction("reg64,reg/mem64", "13/r", {}, {cpuAMD64});
		AddInstruction("AL,imm8", "14ib", {}, {cpu8086});
		AddInstruction("AX,imm16", "15iw", {optO16}, {cpu8086});
		AddInstruction("EAX,imm32", "15id", {optO32}, {cpu386});
		AddInstruction("RAX,simm32", "15id", {}, {cpuAMD64});
		AddInstruction("reg/mem8,imm8", "80/2ib", {}, {cpu8086});
		AddInstruction("reg/mem16,imm16", "81/2iw", {optO16}, {cpu8086});
		AddInstruction("reg/mem32,imm32", "81/2id", {optO32}, {cpu386});
		AddInstruction("reg/mem64,simm32", "81/2id", {}, {cpuAMD64});
		AddInstruction("reg/mem16,simm8", "83/2ib", {optO16}, {cpu8086});
		AddInstruction("reg/mem32,simm8", "83/2ib", {optO32}, {cpu386});
		AddInstruction("reg/mem64,simm8", "83/2ib", {}, {cpuAMD64});

		StartMnemonic(opADD, "ADD");
		AddInstruction("reg/mem8,reg8", "00/r", {}, {cpu8086});
		AddInstruction("reg/mem16,reg16", "01/r", {optO16}, {cpu8086});
		AddInstruction("reg/mem32,reg32", "01/r", {optO32}, {cpu386});
		AddInstruction("reg/mem64,reg64", "01/r", {}, {cpuAMD64});
		AddInstruction("reg8,reg/mem8", "02/r", {}, {cpu8086});
		AddInstruction("reg16,reg/mem16", "03/r", {optO16}, {cpu8086});
		AddInstruction("reg32,reg/mem32", "03/r", {optO32}, {cpu386});
		AddInstruction("reg64,reg/mem64", "03/r", {}, {cpuAMD64});
		AddInstruction("AL,imm8", "04ib", {}, {cpu8086});
		AddInstruction("AX,imm16", "05iw", {optO16}, {cpu8086});
		AddInstruction("EAX,imm32", "05id", {optO32}, {cpu386});
		AddInstruction("RAX,simm32", "05id", {}, {cpuAMD64});
		AddInstruction("reg/mem8,imm8", "80/0ib", {}, {cpu8086});
		AddInstruction("reg/mem16,imm16", "81/0iw", {optO16}, {cpu8086});
		AddInstruction("reg/mem32,imm32", "81/0id", {optO32}, {cpu386});
		AddInstruction("reg/mem64,simm32", "81/0id", {}, {cpuAMD64});
		AddInstruction("reg/mem16,simm8", "83/0ib", {optO16}, {cpu8086});
		AddInstruction("reg/mem32,simm8", "83/0ib", {optO32}, {cpu386});
		AddInstruction("reg/mem64,simm8", "83/0ib", {}, {cpuAMD64});

		StartMnemonic(opADDPD, "ADDPD");
		AddInstruction("xmm1,xmm2/mem128", "660F58/r", {}, {cpuSSE2});

		StartMnemonic(opADDPS, "ADDPS");
		AddInstruction("xmm1,xmm2/mem128", "0F58/r", {}, {cpuSSE});

		StartMnemonic(opADDSD, "ADDSD");
		AddInstruction("xmm1,xmm2/mem64", "F20F58/r", {}, {cpuSSE2});

		StartMnemonic(opADDSS, "ADDSS");
		AddInstruction("xmm1,xmm2/mem32", "F30F58/r", {}, {cpuSSE});

		StartMnemonic(opADDSUBPD, "ADDSUBPD");
		AddInstruction("xmm1,xmm2/mem128", "660FD0/r", {}, {cpuSSE3});

		StartMnemonic(opADDSUBPS, "ADDSUBPS");
		AddInstruction("xmm1,xmm2/mem128", "F20FD0/r", {}, {cpuSSE3});

		StartMnemonic(opAND, "AND");
		AddInstruction("reg/mem8,reg8", "20/r", {}, {cpu8086});
		AddInstruction("reg/mem16,reg16", "21/r", {optO16}, {cpu8086});
		AddInstruction("reg/mem32,reg32", "21/r", {optO32}, {cpu386});
		AddInstruction("reg/mem64,reg64", "21/r", {}, {cpuAMD64});
		AddInstruction("reg8,reg/mem8", "22/r", {}, {cpu8086});
		AddInstruction("reg16,reg/mem16", "23/r", {optO16}, {cpu8086});
		AddInstruction("reg32,reg/mem32", "23/r", {optO32}, {cpu386});
		AddInstruction("reg64,reg/mem64", "23/r", {}, {cpuAMD64});
		AddInstruction("AL,imm8", "24ib", {}, {cpu8086});
		AddInstruction("AX,imm16", "25iw", {optO16}, {cpu8086});
		AddInstruction("EAX,imm32", "25id", {optO32}, {cpu386});
		AddInstruction("RAX,simm32", "25id", {}, {cpuAMD64});
		AddInstruction("reg/mem8,imm8", "80/4ib", {}, {cpu8086});
		AddInstruction("reg/mem16,imm16", "81/4iw", {optO16}, {cpu8086});
		AddInstruction("reg/mem32,imm32", "81/4id", {optO32}, {cpu386});
		AddInstruction("reg/mem64,simm32", "81/4id", {}, {cpuAMD64});
		AddInstruction("reg/mem16,simm8", "83/4ib", {optO16}, {cpu8086});
		AddInstruction("reg/mem32,simm8", "83/4ib", {optO32}, {cpu386});
		AddInstruction("reg/mem64,simm8", "83/4ib", {}, {cpuAMD64});

		StartMnemonic(opANDNPD, "ANDNPD");
		AddInstruction("xmm1,xmm2/mem128", "660F55/r", {}, {cpuSSE2});

		StartMnemonic(opANDNPS, "ANDNPS");
		AddInstruction("xmm1,xmm2/mem128", "0F55/r", {}, {cpuSSE});

		StartMnemonic(opANDPD, "ANDPD");
		AddInstruction("xmm1,xmm2/mem128", "660F54/r", {}, {cpuSSE2});

		StartMnemonic(opANDPS, "ANDPS");
		AddInstruction("xmm1,xmm2/mem128", "0F54/r", {}, {cpuSSE});

		StartMnemonic(opARPL, "ARPL");
		AddInstruction("reg/mem16,reg16", "63/r", {}, {cpu286,cpuPrivileged});

		StartMnemonic(opBOUND, "BOUND");
		AddInstruction("reg16,mem16&mem16", "62/r", {optO16,optNot64}, {cpu186});
		AddInstruction("reg32,mem32&mem32", "62/r", {optO32,optNot64}, {cpu386});

		StartMnemonic(opBSF, "BSF");
		AddInstruction("reg16,reg/mem16", "0FBC/r", {optO16}, {cpu386});
		AddInstruction("reg32,reg/mem32", "0FBC/r", {optO32}, {cpu386});
		AddInstruction("reg64,reg/mem64", "0FBC/r", {}, {cpuAMD64});

		StartMnemonic(opBSR, "BSR");
		AddInstruction("reg16,reg/mem16", "0FBD/r", {optO16}, {cpu386});
		AddInstruction("reg32,reg/mem32", "0FBD/r", {optO32}, {cpu386});
		AddInstruction("reg64,reg/mem64", "0FBD/r", {}, {cpuAMD64});

		StartMnemonic(opBSWAP, "BSWAP");
		AddInstruction("reg32", "0FC8rd", {optO32}, {cpu486});
		AddInstruction("reg64", "0FC8rq", {}, {cpuAMD64});

		StartMnemonic(opBT, "BT");
		AddInstruction("reg/mem16,reg16", "0FA3/r", {optO16}, {cpu386});
		AddInstruction("reg/mem32,reg32", "0FA3/r", {optO32}, {cpu386});
		AddInstruction("reg/mem64,reg64", "0FA3/r", {}, {cpuAMD64});
		AddInstruction("reg/mem16,uimm8", "0FBA/4ib", {optO16}, {cpu386});
		AddInstruction("reg/mem32,uimm8", "0FBA/4ib", {optO32}, {cpu386});
		AddInstruction("reg/mem64,uimm8", "0FBA/4ib", {}, {cpuAMD64});

		StartMnemonic(opBTC, "BTC");
		AddInstruction("reg/mem16,reg16", "0FBB/r", {optO16}, {cpu386});
		AddInstruction("reg/mem32,reg32", "0FBB/r", {optO32}, {cpu386});
		AddInstruction("reg/mem64,reg64", "0FBB/r", {}, {cpuAMD64});
		AddInstruction("reg/mem16,uimm8", "0FBA/7ib", {optO16}, {cpu386});
		AddInstruction("reg/mem32,uimm8", "0FBA/7ib", {optO32}, {cpu386});
		AddInstruction("reg/mem64,uimm8", "0FBA/7ib", {}, {cpuAMD64});

		StartMnemonic(opBTR, "BTR");
		AddInstruction("reg/mem16,reg16", "0FB3/r", {optO16}, {cpu386});
		AddInstruction("reg/mem32,reg32", "0FB3/r", {optO32}, {cpu386});
		AddInstruction("reg/mem64,reg64", "0FB3/r", {}, {cpuAMD64});
		AddInstruction("reg/mem16,uimm8", "0FBA/6ib", {optO16}, {cpu386});
		AddInstruction("reg/mem32,uimm8", "0FBA/6ib", {optO32}, {cpu386});
		AddInstruction("reg/mem64,uimm8", "0FBA/6ib", {}, {cpuAMD64});

		StartMnemonic(opBTS, "BTS");
		AddInstruction("reg/mem16,reg16", "0FAB/r", {optO16}, {cpu386});
		AddInstruction("reg/mem32,reg32", "0FAB/r", {optO32}, {cpu386});
		AddInstruction("reg/mem64,reg64", "0FAB/r", {}, {cpuAMD64});
		AddInstruction("reg/mem16,uimm8", "0FBA/5ib", {optO16}, {cpu386});
		AddInstruction("reg/mem32,uimm8", "0FBA/5ib", {optO32}, {cpu386});
		AddInstruction("reg/mem64,uimm8", "0FBA/5ib", {}, {cpuAMD64});

		StartMnemonic(opCALL, "CALL");
		AddInstruction("rel16off", "E8iw", {optO16}, {cpu8086});
		AddInstruction("rel32off", "E8id", {optO32}, {cpu8086});
		AddInstruction("reg/mem16", "FF/2", {optO16}, {cpu8086});
		AddInstruction("reg/mem32", "FF/2", {optO32}, {cpu386});
		AddInstruction("reg/mem64", "FF/2", {optO64}, {cpuAMD64});

		StartMnemonic(opCALLFAR, "CALLFAR");
		AddInstruction("pntr16:16", "9Acd", {optNot64}, {cpu8086});
		AddInstruction("pntr16:32", "9Acp", {optNot64}, {cpu386});
		AddInstruction("mem16:16", "FF/3", {optO16,optNot64}, {cpu8086});
		AddInstruction("mem16:32", "FF/3", {optO32,optNot64}, {cpu386});

		StartMnemonic(opCBW, "CBW");
		AddInstruction("", "98", {optO16}, {cpu8086});

		StartMnemonic(opCDQ, "CDQ");
		AddInstruction("", "99", {optO32}, {cpu386});

		StartMnemonic(opCDQE, "CDQE");
		AddInstruction("", "98", {}, {cpuAMD64});

		StartMnemonic(opCLC, "CLC");
		AddInstruction("", "F8", {}, {cpu8086});

		StartMnemonic(opCLD, "CLD");
		AddInstruction("", "FC", {}, {cpu8086});

		StartMnemonic(opCLFLUSH, "CLFLUSH");
		AddInstruction("mem8", "0FAE/7", {}, {cpuSSE2});

		StartMnemonic(opCLGI, "CLGI");
		AddInstruction("", "0F01DD", {}, {cpuAMD64});

		StartMnemonic(opCLI, "CLI");
		AddInstruction("", "FA", {}, {cpu8086});

		StartMnemonic(opCLTS, "CLTS");
		AddInstruction("", "0F06", {}, {cpu286,cpuPrivileged});

		StartMnemonic(opCMC, "CMC");
		AddInstruction("", "F5", {}, {cpu8086});

		StartMnemonic(opCMOVA, "CMOVA");
		AddInstruction("reg16,reg/mem16", "0F47/r", {optO16}, {cpuP6});
		AddInstruction("reg32,reg/mem32", "0F47/r", {optO32}, {cpuP6});
		AddInstruction("reg64,reg/mem64", "0F47/r", {}, {cpuAMD64});

		StartMnemonic(opCMOVAE, "CMOVAE");
		AddInstruction("reg16,reg/mem16", "0F43/r", {optO16}, {cpuP6});
		AddInstruction("reg32,reg/mem32", "0F43/r", {optO32}, {cpuP6});
		AddInstruction("reg64,reg/mem64", "0F43/r", {}, {cpuAMD64});

		StartMnemonic(opCMOVB, "CMOVB");
		AddInstruction("reg16,reg/mem16", "0F42/r", {optO16}, {cpuP6});
		AddInstruction("reg32,reg/mem32", "0F42/r", {optO32}, {cpuP6});
		AddInstruction("reg64,reg/mem64", "0F42/r", {}, {cpuAMD64});

		StartMnemonic(opCMOVBE, "CMOVBE");
		AddInstruction("reg16,reg/mem16", "0F46/r", {optO16}, {cpuP6});
		AddInstruction("reg32,reg/mem32", "0F46/r", {optO32}, {cpuP6});
		AddInstruction("reg64,reg/mem64", "0F46/r", {}, {cpuAMD64});

		StartMnemonic(opCMOVC, "CMOVC");
		AddInstruction("reg16,reg/mem16", "0F42/r", {optO16}, {cpuP6});
		AddInstruction("reg32,reg/mem32", "0F42/r", {optO32}, {cpuP6});
		AddInstruction("reg64,reg/mem64", "0F42/r", {}, {cpuAMD64});

		StartMnemonic(opCMOVE, "CMOVE");
		AddInstruction("reg16,reg/mem16", "0F44/r", {optO16}, {cpuP6});
		AddInstruction("reg32,reg/mem32", "0F44/r", {optO32}, {cpuP6});
		AddInstruction("reg64,reg/mem64", "0F44/r", {}, {cpuAMD64});

		StartMnemonic(opCMOVG, "CMOVG");
		AddInstruction("reg16,reg/mem16", "0F4F/r", {optO16}, {cpuP6});
		AddInstruction("reg32,reg/mem32", "0F4F/r", {optO32}, {cpuP6});
		AddInstruction("reg64,reg/mem64", "0F4F/r", {}, {cpuAMD64});

		StartMnemonic(opCMOVGE, "CMOVGE");
		AddInstruction("reg16,reg/mem16", "0F4D/r", {optO16}, {cpuP6});
		AddInstruction("reg32,reg/mem32", "0F4D/r", {optO32}, {cpuP6});
		AddInstruction("reg64,reg/mem64", "0F4D/r", {}, {cpuAMD64});

		StartMnemonic(opCMOVL, "CMOVL");
		AddInstruction("reg16,reg/mem16", "0F4C/r", {optO16}, {cpuP6});
		AddInstruction("reg32,reg/mem32", "0F4C/r", {optO32}, {cpuP6});
		AddInstruction("reg64,reg/mem64", "0F4C/r", {}, {cpuAMD64});

		StartMnemonic(opCMOVLE, "CMOVLE");
		AddInstruction("reg16,reg/mem16", "0F4E/r", {optO16}, {cpuP6});
		AddInstruction("reg32,reg/mem32", "0F4E/r", {optO32}, {cpuP6});
		AddInstruction("reg64,reg/mem64", "0F4E/r", {}, {cpuAMD64});

		StartMnemonic(opCMOVNA, "CMOVNA");
		AddInstruction("reg16,reg/mem16", "0F46/r", {optO16}, {cpuP6});
		AddInstruction("reg32,reg/mem32", "0F46/r", {optO32}, {cpuP6});
		AddInstruction("reg64,reg/mem64", "0F46/r", {}, {cpuAMD64});

		StartMnemonic(opCMOVNAE, "CMOVNAE");
		AddInstruction("reg16,reg/mem16", "0F42/r", {optO16}, {cpuP6});
		AddInstruction("reg32,reg/mem32", "0F42/r", {optO32}, {cpuP6});
		AddInstruction("reg64,reg/mem64", "0F42/r", {}, {cpuAMD64});

		StartMnemonic(opCMOVNB, "CMOVNB");
		AddInstruction("reg16,reg/mem16", "0F43/r", {optO16}, {cpuP6});
		AddInstruction("reg32,reg/mem32", "0F43/r", {optO32}, {cpuP6});
		AddInstruction("reg64,reg/mem64", "0F43/r", {}, {cpuAMD64});

		StartMnemonic(opCMOVNBE, "CMOVNBE");
		AddInstruction("reg16,reg/mem16", "0F47/r", {optO16}, {cpuP6});
		AddInstruction("reg32,reg/mem32", "0F47/r", {optO32}, {cpuP6});
		AddInstruction("reg64,reg/mem64", "0F47/r", {}, {cpuAMD64});

		StartMnemonic(opCMOVNC, "CMOVNC");
		AddInstruction("reg16,reg/mem16", "0F43/r", {optO16}, {cpuP6});
		AddInstruction("reg32,reg/mem32", "0F43/r", {optO32}, {cpuP6});
		AddInstruction("reg64,reg/mem64", "0F43/r", {}, {cpuAMD64});

		StartMnemonic(opCMOVNE, "CMOVNE");
		AddInstruction("reg16,reg/mem16", "0F45/r", {optO16}, {cpuP6});
		AddInstruction("reg32,reg/mem32", "0F45/r", {optO32}, {cpuP6});
		AddInstruction("reg64,reg/mem64", "0F45/r", {}, {cpuAMD64});

		StartMnemonic(opCMOVNG, "CMOVNG");
		AddInstruction("reg16,reg/mem16", "0F4E/r", {optO16}, {cpuP6});
		AddInstruction("reg32,reg/mem32", "0F4E/r", {optO32}, {cpuP6});
		AddInstruction("reg64,reg/mem64", "0F4E/r", {}, {cpuAMD64});

		StartMnemonic(opCMOVNGE, "CMOVNGE");
		AddInstruction("reg16,reg/mem16", "0F4C/r", {optO16}, {cpuP6});
		AddInstruction("reg32,reg/mem32", "0F4C/r", {optO32}, {cpuP6});
		AddInstruction("reg64,reg/mem64", "0F4C/r", {}, {cpuAMD64});

		StartMnemonic(opCMOVNL, "CMOVNL");
		AddInstruction("reg16,reg/mem16", "0F4D/r", {optO16}, {cpuP6});
		AddInstruction("reg32,reg/mem32", "0F4D/r", {optO32}, {cpuP6});
		AddInstruction("reg64,reg/mem64", "0F4D/r", {}, {cpuAMD64});

		StartMnemonic(opCMOVNLE, "CMOVNLE");
		AddInstruction("reg16,reg/mem16", "0F4F/r", {optO16}, {cpuP6});
		AddInstruction("reg32,reg/mem32", "0F4F/r", {optO32}, {cpuP6});
		AddInstruction("reg64,reg/mem64", "0F4F/r", {}, {cpuAMD64});

		StartMnemonic(opCMOVNO, "CMOVNO");
		AddInstruction("reg16,reg/mem16", "0F41/r", {optO16}, {cpuP6});
		AddInstruction("reg32,reg/mem32", "0F41/r", {optO32}, {cpuP6});
		AddInstruction("reg64,reg/mem64", "0F41/r", {}, {cpuAMD64});

		StartMnemonic(opCMOVNP, "CMOVNP");
		AddInstruction("reg16,reg/mem16", "0F4B/r", {optO16}, {cpuP6});
		AddInstruction("reg32,reg/mem32", "0F4B/r", {optO32}, {cpuP6});
		AddInstruction("reg64,reg/mem64", "0F4B/r", {}, {cpuAMD64});

		StartMnemonic(opCMOVNS, "CMOVNS");
		AddInstruction("reg16,reg/mem16", "0F49/r", {optO16}, {cpuP6});
		AddInstruction("reg32,reg/mem32", "0F49/r", {optO32}, {cpuP6});
		AddInstruction("reg64,reg/mem64", "0F49/r", {}, {cpuAMD64});

		StartMnemonic(opCMOVNZ, "CMOVNZ");
		AddInstruction("reg16,reg/mem16", "0F45/r", {optO16}, {cpuP6});
		AddInstruction("reg32,reg/mem32", "0F45/r", {optO32}, {cpuP6});
		AddInstruction("reg64,reg/mem64", "0F45/r", {}, {cpuAMD64});

		StartMnemonic(opCMOVO, "CMOVO");
		AddInstruction("reg16,reg/mem16", "0F40/r", {optO16}, {cpuP6});
		AddInstruction("reg32,reg/mem32", "0F40/r", {optO32}, {cpuP6});
		AddInstruction("reg64,reg/mem64", "0F40/r", {}, {cpuAMD64});

		StartMnemonic(opCMOVP, "CMOVP");
		AddInstruction("reg16,reg/mem16", "0F4A/r", {optO16}, {cpuP6});
		AddInstruction("reg32,reg/mem32", "0F4A/r", {optO32}, {cpuP6});
		AddInstruction("reg64,reg/mem64", "0F4A/r", {}, {cpuAMD64});

		StartMnemonic(opCMOVPE, "CMOVPE");
		AddInstruction("reg16,reg/mem16", "0F4A/r", {optO16}, {cpuP6});
		AddInstruction("reg32,reg/mem32", "0F4A/r", {optO32}, {cpuP6});
		AddInstruction("reg64,reg/mem64", "0F4A/r", {}, {cpuAMD64});

		StartMnemonic(opCMOVPO, "CMOVPO");
		AddInstruction("reg16,reg/mem16", "0F4B/r", {optO16}, {cpuP6});
		AddInstruction("reg32,reg/mem32", "0F4B/r", {optO32}, {cpuP6});
		AddInstruction("reg64,reg/mem64", "0F4B/r", {}, {cpuAMD64});

		StartMnemonic(opCMOVS, "CMOVS");
		AddInstruction("reg16,reg/mem16", "0F48/r", {optO16}, {cpuP6});
		AddInstruction("reg32,reg/mem32", "0F48/r", {optO32}, {cpuP6});
		AddInstruction("reg64,reg/mem64", "0F48/r", {}, {cpuAMD64});

		StartMnemonic(opCMOVZ, "CMOVZ");
		AddInstruction("reg16,reg/mem16", "0F44/r", {optO16}, {cpuP6});
		AddInstruction("reg32,reg/mem32", "0F44/r", {optO32}, {cpuP6});
		AddInstruction("reg64,reg/mem64", "0F44/r", {}, {cpuAMD64});

		StartMnemonic(opCMP, "CMP");
		AddInstruction("reg/mem8,reg8", "38/r", {}, {cpu8086});
		AddInstruction("reg/mem16,reg16", "39/r", {optO16}, {cpu8086});
		AddInstruction("reg/mem32,reg32", "39/r", {optO32}, {cpu386});
		AddInstruction("reg/mem64,reg64", "39/r", {}, {cpuAMD64});
		AddInstruction("reg8,reg/mem8", "3A/r", {}, {cpu8086});
		AddInstruction("reg16,reg/mem16", "3B/r", {optO16}, {cpu8086});
		AddInstruction("reg32,reg/mem32", "3B/r", {optO32}, {cpu386});
		AddInstruction("reg64,reg/mem64", "3B/r", {}, {cpuAMD64});
		AddInstruction("AL,imm8", "3Cib", {}, {cpu8086});
		AddInstruction("AX,imm16", "3Diw", {optO16}, {cpu8086});
		AddInstruction("EAX,imm32", "3Did", {optO32}, {cpu386});
		AddInstruction("RAX,simm32", "3Did", {}, {cpuAMD64});
		AddInstruction("reg/mem8,imm8", "80/7ib", {}, {cpu8086});
		AddInstruction("reg/mem16,imm16", "81/7iw", {optO16}, {cpu8086});
		AddInstruction("reg/mem32,imm32", "81/7id", {optO32}, {cpu386});
		AddInstruction("reg/mem64,simm32", "81/7id", {}, {cpuAMD64});
		AddInstruction("reg/mem16,simm8", "83/7ib", {optO16}, {cpu8086});
		AddInstruction("reg/mem32,simm8", "83/7ib", {optO32}, {cpu386});
		AddInstruction("reg/mem64,simm8", "83/7ib", {}, {cpuAMD64});

		StartMnemonic(opCMPPD, "CMPPD");
		AddInstruction("xmm1,xmm2/mem128,uimm8", "660FC2/rib", {}, {cpuSSE2});

		StartMnemonic(opCMPPS, "CMPPS");
		AddInstruction("xmm1,xmm2/mem128,uimm8", "0FC2/rib", {}, {cpuSSE});

		StartMnemonic(opCMPS, "CMPS");
		AddInstruction("mem8,mem8", "A6", {}, {cpu8086});
		AddInstruction("mem16,mem16", "A7", {optO16}, {cpu8086});
		AddInstruction("mem32,mem32", "A7", {optO32}, {cpu386});
		AddInstruction("mem64,mem64", "A7", {}, {cpuAMD64});

		StartMnemonic(opCMPSB, "CMPSB");
		AddInstruction("", "A6", {}, {cpu8086});

		StartMnemonic(opCMPSD, "CMPSD");
		AddInstruction("", "A7", {optO32}, {cpu386});
		AddInstruction("xmm1,xmm2/mem64,uimm8", "F20FC2/rib", {}, {cpuSSE2});

		StartMnemonic(opCMPSQ, "CMPSQ");
		AddInstruction("", "A7", {}, {cpuAMD64});

		StartMnemonic(opCMPSS, "CMPSS");
		AddInstruction("xmm1,xmm2/mem32,uimm8", "F30FC2/rib", {}, {cpuSSE});

		StartMnemonic(opCMPSW, "CMPSW");
		AddInstruction("", "A7", {optO16}, {cpu8086});

		StartMnemonic(opCMPXCHG, "CMPXCHG");
		AddInstruction("reg/mem8,reg8", "0FB0/r", {}, {cpuPentium});
		AddInstruction("reg/mem16,reg16", "0FB1/r", {optO16}, {cpuPentium});
		AddInstruction("reg/mem32,reg32", "0FB1/r", {optO32}, {cpuPentium});
		AddInstruction("reg/mem64,reg64", "0FB1/r", {}, {cpuAMD64});

		StartMnemonic(opCMPXCHG16B, "CMPXCHG16B");
		AddInstruction("mem128", "0FC7/1m1", {}, {cpuSSE2});

		StartMnemonic(opCMPXCHG8B, "CMPXCHG8B");
		AddInstruction("mem64", "0FC7/1m6", {}, {cpuPentium});

		StartMnemonic(opCOMISD, "COMISD");
		AddInstruction("xmm1,xmm2/mem64", "660F2F/r", {}, {cpuSSE2});

		StartMnemonic(opCOMISS, "COMISS");
		AddInstruction("xmm1,xmm2/mem32", "0F2F/r", {}, {cpuSSE});

		StartMnemonic(opCPUID, "CPUID");
		AddInstruction("", "0FA2", {}, {cpuPentium});

		StartMnemonic(opCQO, "CQO");
		AddInstruction("", "99", {optO64}, {cpuAMD64});

		StartMnemonic(opCVTDQ2PD, "CVTDQ2PD");
		AddInstruction("xmm1,xmm2/mem64", "F30FE6/r", {}, {cpuSSE2});

		StartMnemonic(opCVTDQ2PS, "CVTDQ2PS");
		AddInstruction("xmm1,xmm2/mem128", "0F5B/r", {}, {cpuSSE2});

		StartMnemonic(opCVTPD2DQ, "CVTPD2DQ");
		AddInstruction("xmm1,xmm2/mem128", "F20FE6/r", {}, {cpuSSE2});

		StartMnemonic(opCVTPD2PI, "CVTPD2PI");
		AddInstruction("mmx,xmm2/mem128", "660F2D/r", {}, {cpuSSE2});
		AddInstruction("mmx,xmm2/mem128", "660F2D/r", {}, {cpuSSE2});
		AddInstruction("mmx,xmm/mem128", "660F2C/r", {}, {cpuSSE2});

		StartMnemonic(opCVTPD2PS, "CVTPD2PS");
		AddInstruction("xmm1,xmm2/mem128", "660F5A/r", {}, {cpuSSE2});

		StartMnemonic(opCVTPI2PD, "CVTPI2PD");
		AddInstruction("xmm,mmx/mem64", "660F2A/r", {}, {cpuSSE2});
		AddInstruction("xmm,mmx/mem64", "660F2A/r", {}, {cpuSSE2});

		StartMnemonic(opCVTPI2PS, "CVTPI2PS");
		AddInstruction("xmm,mmx/mem64", "0F2A/r", {}, {cpuSSE});
		AddInstruction("xmm,mmx/mem64", "0F2A/r", {}, {cpuSSE});

		StartMnemonic(opCVTPS2DQ, "CVTPS2DQ");
		AddInstruction("xmm1,xmm2/mem128", "660F5B/r", {}, {cpuSSE2});

		StartMnemonic(opCVTPS2PD, "CVTPS2PD");
		AddInstruction("xmm1,xmm2/mem64", "0F5A/r", {}, {cpuSSE2});

		StartMnemonic(opCVTPS2PI, "CVTPS2PI");
		AddInstruction("mmx,xmm/mem64", "0F2D/r", {}, {cpuSSE});
		AddInstruction("mmx,xmm/mem64", "0F2D/r", {}, {cpuSSE});

		StartMnemonic(opCVTSD2SI, "CVTSD2SI");
		AddInstruction("reg32,xmm/mem64", "F20F2D/r", {}, {cpuSSE2});
		AddInstruction("reg64,xmm/mem64", "F20F2D/r", {}, {cpuAMD64,cpuSSE2});

		StartMnemonic(opCVTSD2SS, "CVTSD2SS");
		AddInstruction("xmm1,xmm2/mem64", "F20F5A/r", {}, {cpuSSE2});

		StartMnemonic(opCVTSI2SD, "CVTSI2SD");
		AddInstruction("xmm,reg/mem32", "F20F2A/r", {}, {cpuSSE2});
		AddInstruction("xmm,reg/mem64", "F20F2A/r", {}, {cpuAMD64,cpuSSE2});

		StartMnemonic(opCVTSI2SS, "CVTSI2SS");
		AddInstruction("xmm,reg/mem32", "F30F2A/r", {}, {cpuSSE});
		AddInstruction("xmm,reg/mem64", "F30F2A/r", {}, {cpuAMD64,cpuSSE});

		StartMnemonic(opCVTSS2SD, "CVTSS2SD");
		AddInstruction("xmm1,xmm2/mem32", "F30F5A/r", {}, {cpuSSE2});

		StartMnemonic(opCVTSS2SI, "CVTSS2SI");
		AddInstruction("reg32,xmm2/mem32", "F30F2D/r", {}, {cpuSSE});
		AddInstruction("reg64,xmm2/mem32", "F30F2D/r", {}, {cpuAMD64,cpuSSE});

		StartMnemonic(opCVTTPD2DQ, "CVTTPD2DQ");
		AddInstruction("xmm1,xmm2/mem128", "660FE6/r", {}, {cpuSSE2});

		StartMnemonic(opCVTTPD2PI, "CVTTPD2PI");
		AddInstruction("mmx,xmm/mem128", "660F2C/r", {}, {cpuSSE2});

		StartMnemonic(opCVTTPS2DQ, "CVTTPS2DQ");
		AddInstruction("xmm1,xmm2/mem128", "F30F5B/r", {}, {cpuSSE2});

		StartMnemonic(opCVTTPS2PI, "CVTTPS2PI");
		AddInstruction("mmx,xmm/mem64", "0F2C/r", {}, {cpuSSE});
		AddInstruction("mmx,xmm/mem64", "0F2C/r", {}, {cpuSSE});

		StartMnemonic(opCVTTSD2SI, "CVTTSD2SI");
		AddInstruction("reg32,xmm/mem64", "F20F2C/r", {}, {cpuSSE2});
		AddInstruction("reg64,xmm/mem64", "F20F2C/r", {}, {cpuAMD64,cpuSSE2});

		StartMnemonic(opCVTTSS2SI, "CVTTSS2SI");
		AddInstruction("reg32,xmm/mem32", "F30F2C/r", {}, {cpuSSE});
		AddInstruction("reg64,xmm/mem32", "F30F2C/r", {}, {cpuAMD64,cpuSSE});

		StartMnemonic(opCWD, "CWD");
		AddInstruction("", "99", {optO16}, {cpu8086});

		StartMnemonic(opCWDE, "CWDE");
		AddInstruction("", "98", {optO32}, {cpu386});

		StartMnemonic(opDAA, "DAA");
		AddInstruction("", "27", {optNot64}, {cpu8086});

		StartMnemonic(opDAS, "DAS");
		AddInstruction("", "2F", {optNot64}, {cpu8086});

		StartMnemonic(opDEC, "DEC");
		AddInstruction("reg16", "48rw", {optO16}, {cpu8086});
		AddInstruction("reg32", "48rd", {optO32}, {cpu386});
		AddInstruction("reg/mem8", "FE/1", {}, {cpu8086});
		AddInstruction("reg/mem16", "FF/1", {optO16}, {cpu8086});
		AddInstruction("reg/mem32", "FF/1", {optO32}, {cpu386});
		AddInstruction("reg/mem64", "FF/1", {}, {cpuAMD64});

		StartMnemonic(opDIV, "DIV");
		AddInstruction("reg/mem8", "F6/6", {}, {cpu8086});
		AddInstruction("reg/mem16", "F7/6", {optO16}, {cpu8086});
		AddInstruction("reg/mem32", "F7/6", {optO32}, {cpu386});
		AddInstruction("reg/mem64", "F7/6", {}, {cpuAMD64});

		StartMnemonic(opDIVPD, "DIVPD");
		AddInstruction("xmm1,xmm2/mem128", "660F5E/r", {}, {cpuSSE2});

		StartMnemonic(opDIVPS, "DIVPS");
		AddInstruction("xmm1,xmm2/mem128", "0F5E/r", {}, {cpuSSE});

		StartMnemonic(opDIVSD, "DIVSD");
		AddInstruction("xmm1,xmm2/mem64", "F20F5E/r", {}, {cpuSSE2});

		StartMnemonic(opDIVSS, "DIVSS");
		AddInstruction("xmm1,xmm2/mem32", "F30F5E/r", {}, {cpuSSE});

		StartMnemonic(opEMMS, "EMMS");
		AddInstruction("", "0F77", {}, {cpuMMX});

		StartMnemonic(opENTER, "ENTER");
		AddInstruction("uimm16,uimm8", "C8iwib", {}, {cpu186});

		StartMnemonic(opF2XM1, "F2XM1");
		AddInstruction("", "D9F0", {}, {cpu8086,cpuFPU});

		StartMnemonic(opFABS, "FABS");
		AddInstruction("", "D9E1", {}, {cpu8086,cpuFPU});

		StartMnemonic(opFADD, "FADD");
		AddInstruction("mem32real", "D8/0", {}, {cpu8086,cpuFPU});
		AddInstruction("mem64real", "DC/0", {}, {cpu8086,cpuFPU});
		AddInstruction("ST(0),ST(i)", "D8C0+i", {}, {cpu8086,cpuFPU});
		AddInstruction("ST(i),ST(0)", "DCC0+i", {}, {cpu8086,cpuFPU});

		StartMnemonic(opFADDP, "FADDP");
		AddInstruction("", "DEC1", {}, {cpu8086,cpuFPU});
		AddInstruction("ST(i),ST(0)", "DEC0+i", {}, {cpu8086,cpuFPU});

		StartMnemonic(opFBLD, "FBLD");
		AddInstruction("mem80dec", "DF/4", {}, {cpu8086,cpuFPU});

		StartMnemonic(opFBSTP, "FBSTP");
		AddInstruction("mem80dec", "DF/6", {}, {cpu8086,cpuFPU});

		StartMnemonic(opFCHS, "FCHS");
		AddInstruction("", "D9E0", {}, {cpu8086,cpuFPU});

		StartMnemonic(opFCLEX, "FCLEX");
		AddInstruction("", "9BDBE2", {}, {cpu8086,cpuFPU});

		StartMnemonic(opFCMOVB, "FCMOVB");
		AddInstruction("ST(0),ST(i)", "DAC0+i", {}, {cpuP6,cpuFPU});

		StartMnemonic(opFCMOVBE, "FCMOVBE");
		AddInstruction("ST(0),ST(i)", "DAD0+i", {}, {cpuP6,cpuFPU});

		StartMnemonic(opFCMOVE, "FCMOVE");
		AddInstruction("ST(0),ST(i)", "DAC8+i", {}, {cpuP6,cpuFPU});

		StartMnemonic(opFCMOVNB, "FCMOVNB");
		AddInstruction("ST(0),ST(i)", "DBC0+i", {}, {cpuP6,cpuFPU});

		StartMnemonic(opFCMOVNBE, "FCMOVNBE");
		AddInstruction("ST(0),ST(i)", "DBD0+i", {}, {cpuP6,cpuFPU});

		StartMnemonic(opFCMOVNE, "FCMOVNE");
		AddInstruction("ST(0),ST(i)", "DBC8+i", {}, {cpuP6,cpuFPU});

		StartMnemonic(opFCMOVNU, "FCMOVNU");
		AddInstruction("ST(0),ST(i)", "DBD8+i", {}, {cpuP6,cpuFPU});

		StartMnemonic(opFCMOVU, "FCMOVU");
		AddInstruction("ST(0),ST(i)", "DAD8+i", {}, {cpuP6,cpuFPU});

		StartMnemonic(opFCOM, "FCOM");
		AddInstruction("", "D8D1", {}, {cpu8086,cpuFPU});
		AddInstruction("ST(i)", "D8D0+i", {}, {cpu8086,cpuFPU});
		AddInstruction("mem32real", "D8/2", {}, {cpu8086,cpuFPU});
		AddInstruction("mem64real", "DC/2", {}, {cpu8086,cpuFPU});

		StartMnemonic(opFCOMI, "FCOMI");
		AddInstruction("ST(0),ST(i)", "DBF0+i", {}, {cpuP6,cpuFPU});

		StartMnemonic(opFCOMIP, "FCOMIP");
		AddInstruction("ST(0),ST(i)", "DFF0+i", {}, {cpuP6,cpuFPU});

		StartMnemonic(opFCOMP, "FCOMP");
		AddInstruction("", "D8D9", {}, {cpu8086,cpuFPU});
		AddInstruction("ST(i)", "D8D8+i", {}, {cpu8086,cpuFPU});
		AddInstruction("mem32real", "D8/3", {}, {cpu8086,cpuFPU});
		AddInstruction("mem64real", "DC/3", {}, {cpu8086,cpuFPU});

		StartMnemonic(opFCOMPP, "FCOMPP");
		AddInstruction("", "DED9", {}, {cpu8086,cpuFPU});

		StartMnemonic(opFCOS, "FCOS");
		AddInstruction("", "D9FF", {}, {cpu386,cpuFPU});

		StartMnemonic(opFDECSTP, "FDECSTP");
		AddInstruction("", "D9F6", {}, {cpu8086,cpuFPU});

		StartMnemonic(opFDIV, "FDIV");
		AddInstruction("mem32real", "D8/6", {}, {cpu8086,cpuFPU});
		AddInstruction("mem64real", "DC/6", {}, {cpu8086,cpuFPU});
		AddInstruction("ST(0),ST(i)", "D8F0+i", {}, {cpu8086,cpuFPU});
		AddInstruction("ST(i),ST(0)", "DCF8+i", {}, {cpu8086,cpuFPU});

		StartMnemonic(opFDIVP, "FDIVP");
		AddInstruction("", "DEF9", {}, {cpu8086,cpuFPU});
		AddInstruction("ST(i),ST(0)", "DEF8+i", {}, {cpu8086,cpuFPU});

		StartMnemonic(opFDIVR, "FDIVR");
		AddInstruction("mem32real", "D8/7", {}, {cpu8086,cpuFPU});
		AddInstruction("mem64real", "DC/7", {}, {cpu8086,cpuFPU});
		AddInstruction("ST(0),ST(i)", "D8F8+i", {}, {cpu8086,cpuFPU});
		AddInstruction("ST(i),ST(0)", "DCF0+i", {}, {cpu8086,cpuFPU});

		StartMnemonic(opFDIVRP, "FDIVRP");
		AddInstruction("", "DEF1", {}, {cpu8086,cpuFPU});
		AddInstruction("ST(i),ST(0)", "DEF0+i", {}, {cpu8086,cpuFPU});

		StartMnemonic(opFEMMS, "FEMMS");
		AddInstruction("", "0F0E", {}, {cpu3DNow});

		StartMnemonic(opFFREE, "FFREE");
		AddInstruction("ST(i)", "DDC0+i", {}, {cpu8086,cpuFPU});

		StartMnemonic(opFIADD, "FIADD");
		AddInstruction("mem16int", "DE/0", {}, {cpu8086,cpuFPU});
		AddInstruction("mem32int", "DA/0", {}, {cpu8086,cpuFPU});

		StartMnemonic(opFICOM, "FICOM");
		AddInstruction("mem16int", "DE/2", {}, {cpu8086,cpuFPU});
		AddInstruction("mem32int", "DA/2", {}, {cpu8086,cpuFPU});

		StartMnemonic(opFICOMP, "FICOMP");
		AddInstruction("mem16int", "DE/3", {}, {cpu8086,cpuFPU});
		AddInstruction("mem32int", "DA/3", {}, {cpu8086,cpuFPU});

		StartMnemonic(opFIDIV, "FIDIV");
		AddInstruction("mem16int", "DE/6", {}, {cpu8086,cpuFPU});
		AddInstruction("mem32int", "DA/6", {}, {cpu8086,cpuFPU});

		StartMnemonic(opFIDIVR, "FIDIVR");
		AddInstruction("mem16int", "DE/7", {}, {cpu8086,cpuFPU});
		AddInstruction("mem32int", "DA/7", {}, {cpu8086,cpuFPU});

		StartMnemonic(opFILD, "FILD");
		AddInstruction("mem16int", "DF/0", {}, {cpu8086,cpuFPU});
		AddInstruction("mem32int", "DB/0", {}, {cpu8086,cpuFPU});
		AddInstruction("mem64int", "DF/5", {}, {cpu8086,cpuFPU});

		StartMnemonic(opFIMUL, "FIMUL");
		AddInstruction("mem16int", "DE/1", {}, {cpu8086,cpuFPU});
		AddInstruction("mem32int", "DA/1", {}, {cpu8086,cpuFPU});

		StartMnemonic(opFINCSTP, "FINCSTP");
		AddInstruction("", "D9F7", {}, {cpu8086,cpuFPU});

		StartMnemonic(opFINIT, "FINIT");
		AddInstruction("", "9BDBE3", {}, {cpu8086,cpuFPU});

		StartMnemonic(opFIST, "FIST");
		AddInstruction("mem16int", "DF/2", {}, {cpu8086,cpuFPU});
		AddInstruction("mem32int", "DB/2", {}, {cpu8086,cpuFPU});

		StartMnemonic(opFISTP, "FISTP");
		AddInstruction("mem16int", "DF/3", {}, {cpu8086,cpuFPU});
		AddInstruction("mem32int", "DB/3", {}, {cpu8086,cpuFPU});
		AddInstruction("mem64int", "DF/7", {}, {cpu8086,cpuFPU});

		StartMnemonic(opFISTTP, "FISTTP");
		AddInstruction("mem16int", "DF/1", {}, {cpuFPU});
		AddInstruction("mem32int", "DB/1", {}, {cpuFPU});
		AddInstruction("mem64int", "DD/1", {}, {cpuFPU});

		StartMnemonic(opFISUB, "FISUB");
		AddInstruction("mem16int", "DE/4", {}, {cpu8086,cpuFPU});
		AddInstruction("mem32int", "DA/4", {}, {cpu8086,cpuFPU});

		StartMnemonic(opFISUBR, "FISUBR");
		AddInstruction("mem16int", "DE/5", {}, {cpu8086,cpuFPU});
		AddInstruction("mem32int", "DA/5", {}, {cpu8086,cpuFPU});

		StartMnemonic(opFLD, "FLD");
		AddInstruction("ST(i)", "D9C0+i", {}, {cpu8086,cpuFPU});
		AddInstruction("mem32real", "D9/0", {}, {cpu8086,cpuFPU});
		AddInstruction("mem64real", "DD/0", {}, {cpu8086,cpuFPU});
		AddInstruction("mem80real", "DB/5", {}, {cpu8086,cpuFPU});

		StartMnemonic(opFLD1, "FLD1");
		AddInstruction("", "D9E8", {}, {cpu8086,cpuFPU});

		StartMnemonic(opFLDCW, "FLDCW");
		AddInstruction("mem2env", "D9/5", {}, {cpu8086,cpuFPU});

		StartMnemonic(opFLDENV, "FLDENV");
		AddInstruction("mem14/28env", "D9/4", {}, {cpu8086,cpuFPU});

		StartMnemonic(opFLDL2E, "FLDL2E");
		AddInstruction("", "D9EA", {}, {cpu8086,cpuFPU});

		StartMnemonic(opFLDL2T, "FLDL2T");
		AddInstruction("", "D9E9", {}, {cpu8086,cpuFPU});

		StartMnemonic(opFLDLG2, "FLDLG2");
		AddInstruction("", "D9EC", {}, {cpu8086,cpuFPU});

		StartMnemonic(opFLDLN2, "FLDLN2");
		AddInstruction("", "D9ED", {}, {cpu8086,cpuFPU});

		StartMnemonic(opFLDPI, "FLDPI");
		AddInstruction("", "D9EB", {}, {cpu8086,cpuFPU});

		StartMnemonic(opFLDZ, "FLDZ");
		AddInstruction("", "D9EE", {}, {cpu8086,cpuFPU});

		StartMnemonic(opFMUL, "FMUL");
		AddInstruction("mem32real", "D8/1", {}, {cpu8086,cpuFPU});
		AddInstruction("mem64real", "DC/1", {}, {cpu8086,cpuFPU});
		AddInstruction("ST(0),ST(i)", "D8C8+i", {}, {cpu8086,cpuFPU});
		AddInstruction("ST(i),ST(0)", "DCC8+i", {}, {cpu8086,cpuFPU});

		StartMnemonic(opFMULP, "FMULP");
		AddInstruction("", "DEC9", {}, {cpu8086,cpuFPU});
		AddInstruction("ST(i),ST(0)", "DEC8+i", {}, {cpu8086,cpuFPU});

		StartMnemonic(opFNCLEX, "FNCLEX");
		AddInstruction("", "DBE2", {}, {cpu8086,cpuFPU});

		StartMnemonic(opFNINIT, "FNINIT");
		AddInstruction("", "DBE3", {}, {cpu8086,cpuFPU});

		StartMnemonic(opFNOP, "FNOP");
		AddInstruction("", "D9D0", {}, {cpu8086,cpuFPU});

		StartMnemonic(opFNSAVE, "FNSAVE");
		AddInstruction("mem94/108env", "DD/6", {}, {cpu8086,cpuFPU});
		AddInstruction("mem94/108env", "DD/6", {}, {cpu8086,cpuFPU});

		StartMnemonic(opFNSTCW, "FNSTCW");
		AddInstruction("mem2env", "D9/7", {}, {cpu8086,cpuFPU});

		StartMnemonic(opFNSTENV, "FNSTENV");
		AddInstruction("mem14/28env", "D9/6", {}, {cpu8086,cpuFPU});

		StartMnemonic(opFNSTSW, "FNSTSW");
		AddInstruction("AX", "DFE0", {}, {cpu286,cpuFPU});
		AddInstruction("mem2env", "DD/7", {}, {cpu8086,cpuFPU});

		StartMnemonic(opFPATAN, "FPATAN");
		AddInstruction("", "D9F3", {}, {cpu8086,cpuFPU});

		StartMnemonic(opFPREM, "FPREM");
		AddInstruction("", "D9F8", {}, {cpu8086,cpuFPU});

		StartMnemonic(opFPREM1, "FPREM1");
		AddInstruction("", "D9F5", {}, {cpu386,cpuFPU});

		StartMnemonic(opFPTAN, "FPTAN");
		AddInstruction("", "D9F2", {}, {cpu8086,cpuFPU});

		StartMnemonic(opFRNDINT, "FRNDINT");
		AddInstruction("", "D9FC", {}, {cpu8086,cpuFPU});

		StartMnemonic(opFRSTOR, "FRSTOR");
		AddInstruction("mem94/108env", "DD/4", {}, {cpu8086,cpuFPU});
		AddInstruction("mem94/108env", "DD/4", {}, {cpu8086,cpuFPU});

		StartMnemonic(opFSAVE, "FSAVE");
		AddInstruction("mem94/108env", "9BDD/6", {}, {cpu8086,cpuFPU});
		AddInstruction("mem94/108env", "9BDD/6", {}, {cpu8086,cpuFPU});

		StartMnemonic(opFSCALE, "FSCALE");
		AddInstruction("", "D9FD", {}, {cpu8086,cpuFPU});

		StartMnemonic(opFSIN, "FSIN");
		AddInstruction("", "D9FE", {}, {cpu386,cpuFPU});

		StartMnemonic(opFSINCOS, "FSINCOS");
		AddInstruction("", "D9FB", {}, {cpu386,cpuFPU});

		StartMnemonic(opFSQRT, "FSQRT");
		AddInstruction("", "D9FA", {}, {cpu8086,cpuFPU});

		StartMnemonic(opFST, "FST");
		AddInstruction("ST(i)", "DDD0+i", {}, {cpu8086,cpuFPU});
		AddInstruction("mem32real", "D9/2", {}, {cpu8086,cpuFPU});
		AddInstruction("mem64real", "DD/2", {}, {cpu8086,cpuFPU});

		StartMnemonic(opFSTCW, "FSTCW");
		AddInstruction("mem2env", "9BD9/7", {}, {cpu8086,cpuFPU});

		StartMnemonic(opFSTENV, "FSTENV");
		AddInstruction("mem14/28env", "9BD9/6", {}, {cpu8086,cpuFPU});

		StartMnemonic(opFSTP, "FSTP");
		AddInstruction("ST(i)", "DDD8+i", {}, {cpu8086,cpuFPU});
		AddInstruction("mem32real", "D9/3", {}, {cpu8086,cpuFPU});
		AddInstruction("mem64real", "DD/3", {}, {cpu8086,cpuFPU});
		AddInstruction("mem80real", "DB/7", {}, {cpu8086,cpuFPU});

		StartMnemonic(opFSTSW, "FSTSW");
		AddInstruction("AX", "9BDFE0", {}, {cpu286,cpuFPU});
		AddInstruction("mem2env", "9BDD/7", {}, {cpu8086,cpuFPU});

		StartMnemonic(opFSUB, "FSUB");
		AddInstruction("mem32real", "D8/4", {}, {cpu8086,cpuFPU});
		AddInstruction("mem64real", "DC/4", {}, {cpu8086,cpuFPU});
		AddInstruction("ST(0),ST(i)", "D8E0+i", {}, {cpu8086,cpuFPU});
		AddInstruction("ST(i),ST(0)", "DCE8+i", {}, {cpu8086,cpuFPU});

		StartMnemonic(opFSUBP, "FSUBP");
		AddInstruction("", "DEE9", {}, {cpu8086,cpuFPU});
		AddInstruction("ST(i),ST(0)", "DEE8+i", {}, {cpu8086,cpuFPU});

		StartMnemonic(opFSUBR, "FSUBR");
		AddInstruction("mem32real", "D8/5", {}, {cpu8086,cpuFPU});
		AddInstruction("mem64real", "DC/5", {}, {cpu8086,cpuFPU});
		AddInstruction("ST(0),ST(i)", "D8E8+i", {}, {cpu8086,cpuFPU});
		AddInstruction("ST(i),ST(0)", "DCE0+i", {}, {cpu8086,cpuFPU});

		StartMnemonic(opFSUBRP, "FSUBRP");
		AddInstruction("", "DEE1", {}, {cpu8086,cpuFPU});
		AddInstruction("ST(i),ST(0)", "DEE0+i", {}, {cpu8086,cpuFPU});

		StartMnemonic(opFTST, "FTST");
		AddInstruction("", "D9E4", {}, {cpu8086,cpuFPU});

		StartMnemonic(opFUCOM, "FUCOM");
		AddInstruction("", "DDE1", {}, {cpu386,cpuFPU});
		AddInstruction("ST(i)", "DDE0+i", {}, {cpu386,cpuFPU});

		StartMnemonic(opFUCOMI, "FUCOMI");
		AddInstruction("ST(0),ST(i)", "DBE8+i", {}, {cpuP6,cpuFPU});

		StartMnemonic(opFUCOMIP, "FUCOMIP");
		AddInstruction("ST(0),ST(i)", "DFE8+i", {}, {cpuP6,cpuFPU});

		StartMnemonic(opFUCOMP, "FUCOMP");
		AddInstruction("", "DDE9", {}, {cpu386,cpuFPU});
		AddInstruction("ST(i)", "DDE8+i", {}, {cpu386,cpuFPU});

		StartMnemonic(opFUCOMPP, "FUCOMPP");
		AddInstruction("", "DAE9", {}, {cpu386,cpuFPU});

		StartMnemonic(opFWAIT, "FWAIT");
		AddInstruction("", "9B", {}, {cpu8086});

		StartMnemonic(opFXAM, "FXAM");
		AddInstruction("", "D9E5", {}, {cpu8086,cpuFPU});

		StartMnemonic(opFXCH, "FXCH");
		AddInstruction("", "D9C9", {}, {cpu8086,cpuFPU});
		AddInstruction("ST(i)", "D9C8+i", {}, {cpu8086,cpuFPU});

		StartMnemonic(opFXRSTOR, "FXRSTOR");
		AddInstruction("mem512env", "0FAE/1", {}, {cpuP6,cpuSSE,cpuFPU});
		AddInstruction("mem512env", "0FAE/1", {}, {cpuP6,cpuSSE,cpuFPU});
		AddInstruction("mem512env", "0FAE/1", {}, {cpuP6,cpuSSE,cpuFPU});

		StartMnemonic(opFXSAVE, "FXSAVE");
		AddInstruction("mem512env", "0FAE/0", {}, {cpuP6,cpuSSE,cpuFPU});
		AddInstruction("mem512env", "0FAE/0", {}, {cpuP6,cpuSSE,cpuFPU});
		AddInstruction("mem512env", "0FAE/0", {}, {cpuP6,cpuSSE,cpuFPU});

		StartMnemonic(opFXTRACT, "FXTRACT");
		AddInstruction("", "D9F4", {}, {cpu8086,cpuFPU});

		StartMnemonic(opFYL2X, "FYL2X");
		AddInstruction("", "D9F1", {}, {cpu8086,cpuFPU});

		StartMnemonic(opFYL2XP1, "FYL2XP1");
		AddInstruction("", "D9F9", {}, {cpu8086,cpuFPU});

		StartMnemonic(opHADDPD, "HADDPD");
		AddInstruction("xmm1,xmm2/mem128", "660F7C/r", {}, {cpuSSE3});

		StartMnemonic(opHADDPS, "HADDPS");
		AddInstruction("xmm1,xmm2/mem128", "F20F7C/r", {}, {cpuSSE3});

		StartMnemonic(opHLT, "HLT");
		AddInstruction("", "F4", {}, {cpu8086,cpuPrivileged});

		StartMnemonic(opHSUBPD, "HSUBPD");
		AddInstruction("xmm1,xmm2/mem128", "660F7D/r", {}, {cpuSSE3});

		StartMnemonic(opHSUBPS, "HSUBPS");
		AddInstruction("xmm1,xmm2/mem128", "F20F7D/r", {}, {cpuSSE3});

		StartMnemonic(opIDIV, "IDIV");
		AddInstruction("reg/mem8", "F6/7", {}, {cpu8086});
		AddInstruction("reg/mem16", "F7/7", {optO16}, {cpu8086});
		AddInstruction("reg/mem32", "F7/7", {optO32}, {cpu386});
		AddInstruction("reg/mem64", "F7/7", {}, {cpuAMD64});

		StartMnemonic(opIMUL, "IMUL");
		AddInstruction("reg/mem8", "F6/5", {}, {cpu8086});
		AddInstruction("reg/mem16", "F7/5", {optO16}, {cpu8086});
		AddInstruction("reg/mem32", "F7/5", {optO32}, {cpu386});
		AddInstruction("reg/mem64", "F7/5", {}, {cpuAMD64});
		AddInstruction("reg16,reg/mem16", "0FAF/r", {optO16}, {cpu386});
		AddInstruction("reg32,reg/mem32", "0FAF/r", {optO32}, {cpu386});
		AddInstruction("reg64,reg/mem64", "0FAF/r", {}, {cpuAMD64});
		AddInstruction("reg16,reg/mem16,simm8", "6B/rib", {optO16}, {cpu186});
		AddInstruction("reg32,reg/mem32,simm8", "6B/rib", {optO32}, {cpu386});
		AddInstruction("reg64,reg/mem64,simm8", "6B/rib", {}, {cpuAMD64});
		AddInstruction("reg16,reg/mem16,simm16", "69/riw", {optO16}, {cpu186});
		AddInstruction("reg32,reg/mem32,simm32", "69/rid", {optO32}, {cpu386});
		AddInstruction("reg64,reg/mem64,simm32", "69/rid", {}, {cpuAMD64});

		StartMnemonic(opIN, "IN");
		AddInstruction("AL,uimm8", "E4ib", {}, {cpu8086});
		AddInstruction("AX,uimm8", "E5ib", {optO16}, {cpu8086});
		AddInstruction("EAX,uimm8", "E5ib", {optO32}, {cpu386});
		AddInstruction("AL,DX", "EC", {}, {cpu8086});
		AddInstruction("AX,DX", "ED", {optO16}, {cpu8086});
		AddInstruction("EAX,DX", "ED", {optO32}, {cpu386});

		StartMnemonic(opINC, "INC");
		AddInstruction("reg16", "40rw", {optO16}, {cpu8086});
		AddInstruction("reg32", "40rd", {optO32}, {cpu386});
		AddInstruction("reg/mem8", "FE/0", {}, {cpu8086});
		AddInstruction("reg/mem16", "FF/0", {optO16}, {cpu8086});
		AddInstruction("reg/mem32", "FF/0", {optO32}, {cpu386});
		AddInstruction("reg/mem64", "FF/0", {}, {cpuAMD64});

		StartMnemonic(opINS, "INS");
		AddInstruction("mem8,DX", "6C", {}, {cpu186});
		AddInstruction("mem16,DX", "6D", {optO16}, {cpu186});
		AddInstruction("mem32,DX", "6D", {optO32}, {cpu386});

		StartMnemonic(opINSB, "INSB");
		AddInstruction("", "6C", {}, {cpu186});

		StartMnemonic(opINSD, "INSD");
		AddInstruction("", "6D", {optO32}, {cpu386});

		StartMnemonic(opINSW, "INSW");
		AddInstruction("", "6D", {optO16}, {cpu186});

		StartMnemonic(opINT, "INT");
		AddInstruction("uimm8", "CDib", {}, {cpu8086});

		StartMnemonic(opINT3, "INT3");
		AddInstruction("", "CC", {}, {cpu8086});

		StartMnemonic(opINTO, "INTO");
		AddInstruction("", "CE", {optNot64}, {cpu8086});

		StartMnemonic(opINVD, "INVD");
		AddInstruction("", "0F08", {}, {cpu486,cpuPrivileged});

		StartMnemonic(opINVLPG, "INVLPG");
		AddInstruction("mem8", "0F01/7", {}, {cpu486});

		StartMnemonic(opINVLPGA, "INVLPGA");
		AddInstruction("rAX,ECX", "0F01DF", {}, {cpu386});

		StartMnemonic(opIRET, "IRET");
		AddInstruction("", "CF", {optO16}, {cpu8086});

		StartMnemonic(opIRETD, "IRETD");
		AddInstruction("", "CF", {optO32}, {cpu386});

		StartMnemonic(opIRETQ, "IRETQ");
		AddInstruction("", "CF", {optO64}, {cpuAMD64});

		StartMnemonic(opJA, "JA");
		AddInstruction("rel8off", "77cb", {}, {cpu8086});
		AddInstruction("rel16off", "0F87cw", {optO16}, {cpu386});
		AddInstruction("rel32off", "0F87cd", {optO32}, {cpu386});

		StartMnemonic(opJAE, "JAE");
		AddInstruction("rel8off", "73cb", {}, {cpu8086});
		AddInstruction("rel16off", "0F83cw", {optO16}, {cpu386});
		AddInstruction("rel32off", "0F83cd", {optO32}, {cpu386});

		StartMnemonic(opJB, "JB");
		AddInstruction("rel8off", "72cb", {}, {cpu8086});
		AddInstruction("rel16off", "0F82cw", {optO16}, {cpu386});
		AddInstruction("rel32off", "0F82cd", {optO32}, {cpu386});

		StartMnemonic(opJBE, "JBE");
		AddInstruction("rel8off", "76cb", {}, {cpu8086});
		AddInstruction("rel16off", "0F86cw", {optO16}, {cpu386});
		AddInstruction("rel32off", "0F86cd", {optO32}, {cpu386});

		StartMnemonic(opJC, "JC");
		AddInstruction("rel8off", "72cb", {}, {cpu8086});
		AddInstruction("rel16off", "0F82cw", {optO16}, {cpu386});
		AddInstruction("rel32off", "0F82cd", {optO32}, {cpu386});

		StartMnemonic(opJCXZ, "JCXZ");
		AddInstruction("rel8off", "E3cb", {optA16}, {cpu8086});

		StartMnemonic(opJE, "JE");
		AddInstruction("rel8off", "74cb", {}, {cpu8086});
		AddInstruction("rel16off", "0F84cw", {optO16}, {cpu386});
		AddInstruction("rel32off", "0F84cd", {optO32}, {cpu386});

		StartMnemonic(opJECXZ, "JECXZ");
		AddInstruction("rel8off", "E3cb", {optA32}, {cpu386});

		StartMnemonic(opJG, "JG");
		AddInstruction("rel8off", "7Fcb", {}, {cpu8086});
		AddInstruction("rel16off", "0F8Fcw", {optO16}, {cpu386});
		AddInstruction("rel32off", "0F8Fcd", {optO32}, {cpu386});

		StartMnemonic(opJGE, "JGE");
		AddInstruction("rel8off", "7Dcb", {}, {cpu8086});
		AddInstruction("rel16off", "0F8Dcw", {optO16}, {cpu386});
		AddInstruction("rel32off", "0F8Dcd", {optO32}, {cpu386});

		StartMnemonic(opJL, "JL");
		AddInstruction("rel8off", "7Ccb", {}, {cpu8086});
		AddInstruction("rel16off", "0F8Ccw", {optO16}, {cpu386});
		AddInstruction("rel32off", "0F8Ccd", {optO32}, {cpu386});

		StartMnemonic(opJLE, "JLE");
		AddInstruction("rel8off", "7Ecb", {}, {cpu8086});
		AddInstruction("rel16off", "0F8Ecw", {optO16}, {cpu386});
		AddInstruction("rel32off", "0F8Ecd", {optO32}, {cpu386});

		StartMnemonic(opJMP, "JMP");
		AddInstruction("rel8off", "EBcb", {}, {cpu8086});
		AddInstruction("rel16off", "E9cw", {optO16}, {cpu8086});
		AddInstruction("rel32off", "E9cd", {optO32}, {cpu8086});
		AddInstruction("reg/mem16", "FF/4", {optO16}, {cpu8086});
		AddInstruction("reg/mem32", "FF/4", {optO32}, {cpu386});
		AddInstruction("reg/mem64", "FF/4", {}, {cpuAMD64});

		StartMnemonic(opJMPFAR, "JMPFAR");
		AddInstruction("pntr16:16", "EAcd", {optO16,optNot64}, {cpu8086});
		AddInstruction("pntr16:32", "EAcp", {optO32,optNot64}, {cpu386});
		AddInstruction("mem16:16", "FF/5", {optO16}, {cpu8086});
		AddInstruction("mem16:32", "FF/5", {optO32}, {cpu386});

		StartMnemonic(opJNA, "JNA");
		AddInstruction("rel8off", "76cb", {}, {cpu8086});
		AddInstruction("rel16off", "0F86cw", {optO16}, {cpu386});
		AddInstruction("rel32off", "0F86cd", {optO32}, {cpu386});

		StartMnemonic(opJNAE, "JNAE");
		AddInstruction("rel8off", "72cb", {}, {cpu8086});
		AddInstruction("rel16off", "0F82cw", {optO16}, {cpu386});
		AddInstruction("rel32off", "0F82cd", {optO32}, {cpu386});

		StartMnemonic(opJNB, "JNB");
		AddInstruction("rel8off", "73cb", {}, {cpu8086});
		AddInstruction("rel16off", "0F83cw", {optO16}, {cpu386});
		AddInstruction("rel32off", "0F83cd", {optO32}, {cpu386});

		StartMnemonic(opJNBE, "JNBE");
		AddInstruction("rel8off", "77cb", {}, {cpu8086});
		AddInstruction("rel16off", "0F87cw", {optO16}, {cpu386});
		AddInstruction("rel32off", "0F87cd", {optO32}, {cpu386});

		StartMnemonic(opJNC, "JNC");
		AddInstruction("rel8off", "73cb", {}, {cpu8086});
		AddInstruction("rel16off", "0F83cw", {optO16}, {cpu386});
		AddInstruction("rel32off", "0F83cd", {optO32}, {cpu386});

		StartMnemonic(opJNE, "JNE");
		AddInstruction("rel8off", "75cb", {}, {cpu8086});
		AddInstruction("rel16off", "0F85cw", {optO16}, {cpu386});
		AddInstruction("rel32off", "0F85cd", {optO32}, {cpu386});

		StartMnemonic(opJNG, "JNG");
		AddInstruction("rel8off", "7Ecb", {}, {cpu8086});
		AddInstruction("rel16off", "0F8Ecw", {optO16}, {cpu386});
		AddInstruction("rel32off", "0F8Ecd", {optO32}, {cpu386});

		StartMnemonic(opJNGE, "JNGE");
		AddInstruction("rel8off", "7Ccb", {}, {cpu8086});
		AddInstruction("rel16off", "0F8Ccw", {optO16}, {cpu386});
		AddInstruction("rel32off", "0F8Ccd", {optO32}, {cpu386});

		StartMnemonic(opJNL, "JNL");
		AddInstruction("rel8off", "7Dcb", {}, {cpu8086});
		AddInstruction("rel16off", "0F8Dcw", {optO16}, {cpu386});
		AddInstruction("rel32off", "0F8Dcd", {optO32}, {cpu386});

		StartMnemonic(opJNLE, "JNLE");
		AddInstruction("rel8off", "7Fcb", {}, {cpu8086});
		AddInstruction("rel16off", "0F8Fcw", {optO16}, {cpu386});
		AddInstruction("rel32off", "0F8Fcd", {optO32}, {cpu386});

		StartMnemonic(opJNO, "JNO");
		AddInstruction("rel8off", "71cb", {}, {cpu8086});
		AddInstruction("rel16off", "0F81cw", {optO16}, {cpu386});
		AddInstruction("rel32off", "0F81cd", {optO32}, {cpu386});

		StartMnemonic(opJNP, "JNP");
		AddInstruction("rel8off", "7Bcb", {}, {cpu8086});
		AddInstruction("rel16off", "0F8Bcw", {optO16}, {cpu386});
		AddInstruction("rel32off", "0F8Bcd", {optO32}, {cpu386});

		StartMnemonic(opJNS, "JNS");
		AddInstruction("rel8off", "79cb", {}, {cpu8086});
		AddInstruction("rel16off", "0F89cw", {optO16}, {cpu386});
		AddInstruction("rel32off", "0F89cd", {optO32}, {cpu386});

		StartMnemonic(opJNZ, "JNZ");
		AddInstruction("rel8off", "75cb", {}, {cpu8086});
		AddInstruction("rel16off", "0F85cw", {optO16}, {cpu386});
		AddInstruction("rel32off", "0F85cd", {optO32}, {cpu386});

		StartMnemonic(opJO, "JO");
		AddInstruction("rel8off", "70cb", {}, {cpu8086});
		AddInstruction("rel16off", "0F80cw", {optO16}, {cpu386});
		AddInstruction("rel32off", "0F80cd", {optO32}, {cpu386});

		StartMnemonic(opJP, "JP");
		AddInstruction("rel8off", "7Acb", {}, {cpu8086});
		AddInstruction("rel16off", "0F8Acw", {optO16}, {cpu386});
		AddInstruction("rel32off", "0F8Acd", {optO32}, {cpu386});

		StartMnemonic(opJPE, "JPE");
		AddInstruction("rel8off", "7Acb", {}, {cpu8086});
		AddInstruction("rel16off", "0F8Acw", {optO16}, {cpu386});
		AddInstruction("rel32off", "0F8Acd", {optO32}, {cpu386});

		StartMnemonic(opJPO, "JPO");
		AddInstruction("rel8off", "7Bcb", {}, {cpu8086});
		AddInstruction("rel16off", "0F8Bcw", {optO16}, {cpu386});
		AddInstruction("rel32off", "0F8Bcd", {optO32}, {cpu386});

		StartMnemonic(opJRCXZ, "JRCXZ");
		AddInstruction("rel8off", "E3cb", {}, {cpuAMD64});

		StartMnemonic(opJS, "JS");
		AddInstruction("rel8off", "78cb", {}, {cpu8086});
		AddInstruction("rel16off", "0F88cw", {optO16}, {cpu386});
		AddInstruction("rel32off", "0F88cd", {optO32}, {cpu386});

		StartMnemonic(opJZ, "JZ");
		AddInstruction("rel8off", "74cb", {}, {cpu8086});
		AddInstruction("rel16off", "0F84cw", {optO16}, {cpu386});
		AddInstruction("rel32off", "0F84cd", {optO32}, {cpu386});

		StartMnemonic(opLAHF, "LAHF");
		AddInstruction("", "9F", {}, {cpu8086});

		StartMnemonic(opLAR, "LAR");
		AddInstruction("reg16,reg/mem16", "0F02/r", {optO16}, {cpu286,cpuPrivileged});
		AddInstruction("reg32,reg/mem16", "0F02/r", {optO32}, {cpu286,cpuPrivileged});
		AddInstruction("reg64,reg/mem16", "0F02/r", {}, {cpuAMD64,cpuPrivileged});

		StartMnemonic(opLDDQU, "LDDQU");
		AddInstruction("xmm1,mem128", "F20FF0/r", {}, {cpuSSE3});

		StartMnemonic(opLDMXCSR, "LDMXCSR");
		AddInstruction("mem32", "0FAE/2", {}, {cpuSSE});

		StartMnemonic(opLDS, "LDS");
		AddInstruction("reg16,mem16:16", "C5/r", {optO16,optNot64}, {cpu8086});
		AddInstruction("reg32,mem16:32", "C5/r", {optO32,optNot64}, {cpu386});

		StartMnemonic(opLEA, "LEA");
		AddInstruction("reg16,mem", "8D/r", {optO16}, {cpu8086});
		AddInstruction("reg32,mem", "8D/r", {optO32}, {cpu386});
		AddInstruction("reg64,mem", "8D/r", {}, {cpuAMD64});

		StartMnemonic(opLEAVE, "LEAVE");
		AddInstruction("", "C9", {}, {cpu186});

		StartMnemonic(opLES, "LES");
		AddInstruction("reg16,mem16:16", "C4/r", {optO16,optNot64}, {cpu8086});
		AddInstruction("reg32,mem16:32", "C4/r", {optO32,optNot64}, {cpu386});

		StartMnemonic(opLFENCE, "LFENCE");
		AddInstruction("", "0FAEE8", {}, {cpuSSE2});

		StartMnemonic(opLFS, "LFS");
		AddInstruction("reg16,mem16:16", "0FB4/r", {optO16}, {cpu386});
		AddInstruction("reg32,mem16:32", "0FB4/r", {optO32}, {cpu386});

		StartMnemonic(opLGDT, "LGDT");
		AddInstruction("mem16:32", "0F01/2", {}, {cpu286,cpuPrivileged});
		AddInstruction("mem16:64", "0F01/2", {}, {cpuAMD64,cpuPrivileged});

		StartMnemonic(opLGS, "LGS");
		AddInstruction("reg16,mem16:16", "0FB5/r", {optO16}, {cpu386});
		AddInstruction("reg32,mem16:32", "0FB5/r", {optO32}, {cpu386});

		StartMnemonic(opLIDT, "LIDT");
		AddInstruction("mem16:32", "0F01/3", {}, {cpu286,cpuPrivileged});
		AddInstruction("mem16:64", "0F01/3", {}, {cpuAMD64,cpuPrivileged});

		StartMnemonic(opLLDT, "LLDT");
		AddInstruction("reg/mem16", "0F00/2", {}, {cpu286,cpuPrivileged});

		StartMnemonic(opLMSW, "LMSW");
		AddInstruction("reg/mem16", "0F01/6", {}, {cpu286,cpuPrivileged});

		StartMnemonic(opLODS, "LODS");
		AddInstruction("mem8", "AC", {}, {cpu8086});
		AddInstruction("mem16", "AD", {optO16}, {cpu8086});
		AddInstruction("mem32", "AD", {optO32}, {cpu386});
		AddInstruction("mem64", "AD", {}, {cpuAMD64});

		StartMnemonic(opLODSB, "LODSB");
		AddInstruction("", "AC", {}, {cpu8086});

		StartMnemonic(opLODSD, "LODSD");
		AddInstruction("", "AD", {optO32}, {cpu386});

		StartMnemonic(opLODSQ, "LODSQ");
		AddInstruction("", "AD", {}, {cpuAMD64});

		StartMnemonic(opLODSW, "LODSW");
		AddInstruction("", "AD", {optO16}, {cpu8086});

		StartMnemonic(opLOOP, "LOOP");
		AddInstruction("rel8off", "E2cb", {}, {cpu8086});

		StartMnemonic(opLOOPE, "LOOPE");
		AddInstruction("rel8off", "E1cb", {}, {cpu8086});

		StartMnemonic(opLOOPNE, "LOOPNE");
		AddInstruction("rel8off", "E0cb", {}, {cpu8086});

		StartMnemonic(opLOOPNZ, "LOOPNZ");
		AddInstruction("rel8off", "E0cb", {}, {cpu8086});

		StartMnemonic(opLOOPZ, "LOOPZ");
		AddInstruction("rel8off", "E1cb", {}, {cpu8086});

		StartMnemonic(opLSL, "LSL");
		AddInstruction("reg16,reg/mem16", "0F03/r", {}, {cpu286,cpuPrivileged});
		AddInstruction("reg32,reg/mem16", "0F03/r", {}, {cpu286,cpuPrivileged});
		AddInstruction("reg64,reg/mem16", "0F03/r", {}, {cpuAMD64,cpuPrivileged});

		StartMnemonic(opLSS, "LSS");
		AddInstruction("reg16,mem16:16", "0FB2/r", {optO16}, {cpu386});
		AddInstruction("reg32,mem16:32", "0FB2/r", {optO32}, {cpu386});

		StartMnemonic(opLTR, "LTR");
		AddInstruction("reg/mem16", "0F00/3", {}, {cpu286,cpuPrivileged});

		StartMnemonic(opMASKMOVDQU, "MASKMOVDQU");
		AddInstruction("xmm1,xmm2", "660FF7/r", {}, {cpuSSE2});

		StartMnemonic(opMASKMOVQ, "MASKMOVQ");
		AddInstruction("mmx1,mmx2", "0FF7/r", {}, {cpuMMX});

		StartMnemonic(opMAXPD, "MAXPD");
		AddInstruction("xmm1,xmm2/mem128", "660F5F/r", {}, {cpuSSE2});

		StartMnemonic(opMAXPS, "MAXPS");
		AddInstruction("xmm1,xmm2/mem128", "0F5F/r", {}, {cpuSSE});

		StartMnemonic(opMAXSD, "MAXSD");
		AddInstruction("xmm1,xmm2/mem64", "F20F5F/r", {}, {cpuSSE2});

		StartMnemonic(opMAXSS, "MAXSS");
		AddInstruction("xmm1,xmm2/mem32", "F30F5F/r", {}, {cpuSSE});

		StartMnemonic(opMFENCE, "MFENCE");
		AddInstruction("", "0FAEF0", {}, {cpuSSE2});

		StartMnemonic(opMINPD, "MINPD");
		AddInstruction("xmm1,xmm2/mem128", "660F5D/r", {}, {cpuSSE2});

		StartMnemonic(opMINPS, "MINPS");
		AddInstruction("xmm1,xmm2/mem128", "0F5D/r", {}, {cpuSSE});

		StartMnemonic(opMINSD, "MINSD");
		AddInstruction("xmm1,xmm2/mem64", "F20F5D/r", {}, {cpuSSE2});

		StartMnemonic(opMINSS, "MINSS");
		AddInstruction("xmm1,xmm2/mem32", "F30F5D/r", {}, {cpuSSE});

		StartMnemonic(opMOV, "MOV");
		AddInstruction("reg/mem8,reg8", "88/r", {}, {cpu8086});
		AddInstruction("reg/mem16,reg16", "89/r", {optO16}, {cpu8086});
		AddInstruction("reg/mem32,reg32", "89/r", {optO32}, {cpu386});
		AddInstruction("reg/mem64,reg64", "89/r", {}, {cpuAMD64});
		AddInstruction("reg8,reg/mem8", "8A/r", {}, {cpu8086});
		AddInstruction("reg16,reg/mem16", "8B/r", {optO16}, {cpu8086});
		AddInstruction("reg32,reg/mem32", "8B/r", {optO32}, {cpu386});
		AddInstruction("reg64,reg/mem64", "8B/r", {}, {cpuAMD64});
		AddInstruction("reg8,imm8", "B0rbib", {}, {cpu8086});
		AddInstruction("reg16,imm16", "B8rwiw", {optO16}, {cpu8086});
		AddInstruction("reg32,imm32", "B8rdid", {optO32}, {cpu386});
		AddInstruction("reg64,imm64", "B8rqiq", {}, {cpuAMD64});
		AddInstruction("CRn,reg32", "0F22/r", {}, {cpu386});
		AddInstruction("CRn,reg64", "0F22/r", {}, {cpuAMD64});
		AddInstruction("reg32,CRn", "0F20/r", {}, {cpu386});
		AddInstruction("reg64,CRn", "0F20/r", {}, {cpuAMD64});
		AddInstruction("CR8,reg32", "F00F22/r", {}, {cpu386});
		AddInstruction("CR8,reg64", "F00F22/r", {}, {cpuAMD64});
		AddInstruction("reg32,CR8", "F00F20/r", {}, {cpu386});
		AddInstruction("reg64,CR8", "F00F20/r", {}, {cpuAMD64});
		AddInstruction("reg32,DRn", "0F21/r", {}, {cpu386});
		AddInstruction("reg64,DRn", "0F21/r", {}, {cpuAMD64});
		AddInstruction("DRn,reg32", "0F23/r", {}, {cpu386});
		AddInstruction("DRn,reg64", "0F23/r", {}, {cpuAMD64});
		AddInstruction("reg/mem16,segReg", "8C/r", {optO16}, {cpu8086});
		AddInstruction("reg/mem32,segReg", "8C/r", {optO32}, {cpu386});
		AddInstruction("reg/mem64,segReg", "8C/r", {}, {cpuAMD64});
		AddInstruction("segReg,reg/mem16", "8E/r", {optO16}, {cpu8086});
		AddInstruction("segReg,reg/mem32", "8E/r", {optO32}, {cpu386});
		AddInstruction("segReg,reg/mem64", "8E/r", {}, {cpuAMD64});
		AddInstruction("AL,moffset8", "A0+o", {}, {cpu8086});
		AddInstruction("AX,moffset16", "A1+o", {optO16}, {cpu8086});
		AddInstruction("EAX,moffset32", "A1+o", {optO32}, {cpu386});
		AddInstruction("RAX,moffset64", "A1+o", {}, {cpuAMD64});
		AddInstruction("moffset8,AL", "A2+o", {}, {cpu8086});
		AddInstruction("moffset16,AX", "A3+o", {optO16}, {cpu8086});
		AddInstruction("moffset32,EAX", "A3+o", {optO32}, {cpu386});
		AddInstruction("moffset64,RAX", "A3+o", {}, {cpuAMD64});
		AddInstruction("reg/mem8,imm8", "C6/0ib", {}, {cpu8086});
		AddInstruction("reg/mem16,imm16", "C7/0iw", {optO16}, {cpu8086});
		AddInstruction("reg/mem32,imm32", "C7/0id", {optO32}, {cpu386});
		AddInstruction("reg/mem64,simm32", "C7/0id", {}, {cpuAMD64});

		StartMnemonic(opMOVAPD, "MOVAPD");
		AddInstruction("xmm1,xmm2/mem128", "660F28/r", {}, {cpuSSE2});
		AddInstruction("xmm1/mem128,xmm2", "660F29/r", {}, {cpuSSE2});

		StartMnemonic(opMOVAPS, "MOVAPS");
		AddInstruction("xmm1,xmm2/mem128", "0F28/r", {}, {cpuSSE});
		AddInstruction("xmm1/mem128,xmm2", "0F29/r", {}, {cpuSSE});

		StartMnemonic(opMOVD, "MOVD");
		AddInstruction("xmm,reg/mem32", "660F6E/r", {}, {cpuSSE2});
		AddInstruction("xmm,reg/mem64", "660F6E/r", {}, {cpuAMD64,cpuSSE2});
		AddInstruction("reg/mem32,xmm", "660F7E/r", {}, {cpuSSE2});
		AddInstruction("reg/mem64,xmm", "660F7E/r", {}, {cpuAMD64,cpuSSE2});
		AddInstruction("mmx,reg/mem32", "0F6E/r", {}, {cpuMMX});
		AddInstruction("mmx,reg/mem64", "0F6E/r", {}, {cpuAMD64,cpuMMX});
		AddInstruction("reg/mem32,mmx", "0F7E/r", {}, {cpuMMX});
		AddInstruction("reg/mem64,mmx", "0F7E/r", {}, {cpuAMD64,cpuMMX});
		AddInstruction("xmm,reg/mem32", "660F6E/r", {}, {cpuSSE2});
		AddInstruction("xmm,reg/mem64", "660F6E/r", {}, {cpuAMD64,cpuSSE2});
		AddInstruction("reg/mem32,xmm", "660F7E/r", {}, {cpuSSE2});
		AddInstruction("reg/mem64,xmm", "660F7E/r", {}, {cpuAMD64,cpuSSE2});
		AddInstruction("mmx,reg/mem32", "0F6E/r", {}, {cpuMMX});
		AddInstruction("mmx,reg/mem64", "0F6E/r", {}, {cpuAMD64,cpuMMX});
		AddInstruction("reg/mem32,mmx", "0F7E/r", {}, {cpuMMX});
		AddInstruction("reg/mem64,mmx", "0F7E/r", {}, {cpuAMD64,cpuMMX});

		StartMnemonic(opMOVDDUP, "MOVDDUP");
		AddInstruction("xmm1,xmm2/mem64", "F20F12/r", {}, {cpuSSE3});

		StartMnemonic(opMOVDQ2Q, "MOVDQ2Q");
		AddInstruction("mmx,xmm", "F20FD6/r", {}, {cpuSSE2});
		AddInstruction("mmx,xmm", "F20FD6/r", {}, {cpuSSE2});

		StartMnemonic(opMOVDQA, "MOVDQA");
		AddInstruction("xmm1,xmm2/mem128", "660F6F/r", {}, {cpuSSE2});
		AddInstruction("xmm1/mem128,xmm2", "660F7F/r", {}, {cpuSSE2});

		StartMnemonic(opMOVDQU, "MOVDQU");
		AddInstruction("xmm1,xmm2/mem128", "F30F6F/r", {}, {cpuSSE2});
		AddInstruction("xmm1/mem128,xmm2", "F30F7F/r", {}, {cpuSSE2});

		StartMnemonic(opMOVHLPS, "MOVHLPS");
		AddInstruction("xmm1,xmm2", "0F12/r", {}, {cpuSSE});

		StartMnemonic(opMOVHPD, "MOVHPD");
		AddInstruction("xmm,mem64", "660F16/r", {}, {cpuSSE2});
		AddInstruction("mem64,xmm", "660F17/r", {}, {cpuSSE2});

		StartMnemonic(opMOVHPS, "MOVHPS");
		AddInstruction("xmm,mem64", "0F16/r", {}, {cpuSSE});
		AddInstruction("mem64,xmm", "0F17/r", {}, {cpuSSE});

		StartMnemonic(opMOVLHPS, "MOVLHPS");
		AddInstruction("xmm1,xmm2", "0F16/r", {}, {cpuSSE});

		StartMnemonic(opMOVLPD, "MOVLPD");
		AddInstruction("xmm,mem64", "660F12/r", {}, {cpuSSE2});
		AddInstruction("mem64,xmm", "660F13/r", {}, {cpuSSE2});

		StartMnemonic(opMOVLPS, "MOVLPS");
		AddInstruction("xmm,mem64", "0F12/r", {}, {cpuSSE});
		AddInstruction("mem64,xmm", "0F13/r", {}, {cpuSSE});

		StartMnemonic(opMOVMSKPD, "MOVMSKPD");
		AddInstruction("reg32,xmm", "660F50/r", {}, {cpuSSE2});

		StartMnemonic(opMOVMSKPS, "MOVMSKPS");
		AddInstruction("reg32,xmm", "0F50/r", {}, {cpuSSE});
		AddInstruction("reg32,xmm", "0F50/r", {}, {cpuSSE});

		StartMnemonic(opMOVNTDQ, "MOVNTDQ");
		AddInstruction("mem128,xmm", "660FE7/r", {}, {cpuSSE2});

		StartMnemonic(opMOVNTI, "MOVNTI");
		AddInstruction("mem32,reg32", "0FC3/r", {}, {cpuSSE2});
		AddInstruction("mem64,reg64", "0FC3/r", {}, {cpuAMD64,cpuSSE2});

		StartMnemonic(opMOVNTPD, "MOVNTPD");
		AddInstruction("mem128,xmm", "660F2B/r", {}, {cpuSSE2});

		StartMnemonic(opMOVNTPS, "MOVNTPS");
		AddInstruction("mem128,xmm", "0F2B/r", {}, {cpuSSE});

		StartMnemonic(opMOVNTQ, "MOVNTQ");
		AddInstruction("mem64,mmx", "0FE7/r", {}, {cpuMMX});

		StartMnemonic(opMOVQ, "MOVQ");
		AddInstruction("xmm1,xmm2/mem64", "F30F7E/r", {}, {cpuSSE2});
		AddInstruction("xmm1/mem64,xmm2", "660FD6/r", {}, {cpuSSE2});
		AddInstruction("mmx1,mmx2/mem64", "0F6F/r", {}, {cpuMMX});
		AddInstruction("mmx1/mem64,mmx2", "0F7F/r", {}, {cpuMMX});

		StartMnemonic(opMOVQ2DQ, "MOVQ2DQ");
		AddInstruction("xmm,mmx", "F30FD6/r", {}, {cpuSSE2});
		AddInstruction("xmm,mmx", "F30FD6/r", {}, {cpuSSE2});

		StartMnemonic(opMOVS, "MOVS");
		AddInstruction("mem8,mem8", "A4", {}, {cpu8086});
		AddInstruction("mem16,mem16", "A5", {optO16}, {cpu8086});
		AddInstruction("mem32,mem32", "A5", {optO32}, {cpu386});
		AddInstruction("mem64,mem64", "A5", {}, {cpuAMD64});

		StartMnemonic(opMOVSB, "MOVSB");
		AddInstruction("", "A4", {}, {cpu8086});

		StartMnemonic(opMOVSD, "MOVSD");
		AddInstruction("", "A5", {optO32}, {cpu386});
		AddInstruction("xmm1,xmm2/mem64", "F20F10/r", {}, {cpuSSE2});
		AddInstruction("xmm1/mem64,xmm2", "F20F11/r", {}, {cpuSSE2});

		StartMnemonic(opMOVSHDUP, "MOVSHDUP");
		AddInstruction("xmm1,xmm2/mem128", "F30F16/r", {}, {cpuSSE3});

		StartMnemonic(opMOVSLDUP, "MOVSLDUP");
		AddInstruction("xmm1,xmm2/mem128", "F30F12/r", {}, {cpuSSE3});

		StartMnemonic(opMOVSQ, "MOVSQ");
		AddInstruction("", "A5", {}, {cpuAMD64});

		StartMnemonic(opMOVSS, "MOVSS");
		AddInstruction("xmm1,xmm2/mem32", "F30F10/r", {}, {cpuSSE});
		AddInstruction("xmm1/mem32,xmm2", "F30F11/r", {}, {cpuSSE});

		StartMnemonic(opMOVSW, "MOVSW");
		AddInstruction("", "A5", {optO16}, {cpu8086});

		StartMnemonic(opMOVSX, "MOVSX");
		AddInstruction("reg16,reg/mem8", "0FBE/r", {optO16}, {cpu386});
		AddInstruction("reg32,reg/mem8", "0FBE/r", {optO32}, {cpu386});
		AddInstruction("reg64,reg/mem8", "0FBE/r", {}, {cpuAMD64});
		AddInstruction("reg32,reg/mem16", "0FBF/r", {optO32}, {cpu386});
		AddInstruction("reg64,reg/mem16", "0FBF/r", {}, {cpuAMD64});

		StartMnemonic(opMOVSXD, "MOVSXD");
		AddInstruction("reg64,reg/mem32", "63/r", {}, {cpuAMD64});

		StartMnemonic(opMOVUPD, "MOVUPD");
		AddInstruction("xmm1,xmm2/mem128", "660F10/r", {}, {cpuSSE2});
		AddInstruction("xmm1/mem128,xmm2", "660F11/r", {}, {cpuSSE2});

		StartMnemonic(opMOVUPS, "MOVUPS");
		AddInstruction("xmm1,xmm2/mem128", "0F10/r", {}, {cpuSSE});
		AddInstruction("xmm1/mem128,xmm2", "0F11/r", {}, {cpuSSE});

		StartMnemonic(opMOVZX, "MOVZX");
		AddInstruction("reg16,reg/mem8", "0FB6/r", {optO16}, {cpu386});
		AddInstruction("reg32,reg/mem8", "0FB6/r", {optO32}, {cpu386});
		AddInstruction("reg64,reg/mem8", "0FB6/r", {}, {cpuAMD64});
		AddInstruction("reg32,reg/mem16", "0FB7/r", {optO32}, {cpu386});
		AddInstruction("reg64,reg/mem16", "0FB7/r", {}, {cpuAMD64});

		StartMnemonic(opMUL, "MUL");
		AddInstruction("reg/mem8", "F6/4", {}, {cpu8086});
		AddInstruction("reg/mem16", "F7/4", {optO16}, {cpu8086});
		AddInstruction("reg/mem32", "F7/4", {optO32}, {cpu386});
		AddInstruction("reg/mem64", "F7/4", {}, {cpuAMD64});
		AddInstruction("AL,reg/mem8", "F6/4", {}, {cpu8086});
		AddInstruction("AX,reg/mem16", "F7/4", {optO16}, {cpu8086});
		AddInstruction("EAX,reg/mem32", "F7/4", {optO32}, {cpu386});
		AddInstruction("RAX,reg/mem64", "F7/4", {}, {cpuAMD64});

		StartMnemonic(opMULPD, "MULPD");
		AddInstruction("xmm1,xmm2/mem128", "660F59/r", {}, {cpuSSE2});

		StartMnemonic(opMULPS, "MULPS");
		AddInstruction("xmm1,xmm2/mem128", "0F59/r", {}, {cpuSSE});

		StartMnemonic(opMULSD, "MULSD");
		AddInstruction("xmm1,xmm2/mem64", "F20F59/r", {}, {cpuSSE2});

		StartMnemonic(opMULSS, "MULSS");
		AddInstruction("xmm1,xmm2/mem32", "F30F59/r", {}, {cpuSSE});

		StartMnemonic(opNEG, "NEG");
		AddInstruction("reg/mem8", "F6/3", {}, {cpu8086});
		AddInstruction("reg/mem16", "F7/3", {optO16}, {cpu8086});
		AddInstruction("reg/mem32", "F7/3", {optO32}, {cpu386});
		AddInstruction("reg/mem64", "F7/3", {}, {cpuAMD64});

		StartMnemonic(opNOP, "NOP");
		AddInstruction("", "90", {}, {cpu8086});

		StartMnemonic(opNOT, "NOT");
		AddInstruction("reg/mem8", "F6/2", {}, {cpu8086});
		AddInstruction("reg/mem16", "F7/2", {optO16}, {cpu8086});
		AddInstruction("reg/mem32", "F7/2", {optO32}, {cpu386});
		AddInstruction("reg/mem64", "F7/2", {}, {cpuAMD64});

		StartMnemonic(opOR, "OR");
		AddInstruction("reg/mem8,reg8", "08/r", {}, {cpu8086});
		AddInstruction("reg/mem16,reg16", "09/r", {optO16}, {cpu8086});
		AddInstruction("reg/mem32,reg32", "09/r", {optO32}, {cpu386});
		AddInstruction("reg/mem64,reg64", "09/r", {}, {cpuAMD64});
		AddInstruction("reg8,reg/mem8", "0A/r", {}, {cpu8086});
		AddInstruction("reg16,reg/mem16", "0B/r", {optO16}, {cpu8086});
		AddInstruction("reg32,reg/mem32", "0B/r", {optO32}, {cpu386});
		AddInstruction("reg64,reg/mem64", "0B/r", {}, {cpuAMD64});
		AddInstruction("AL,imm8", "0Cib", {}, {cpu8086});
		AddInstruction("AX,imm16", "0Diw", {optO16}, {cpu8086});
		AddInstruction("EAX,imm32", "0Did", {optO32}, {cpu386});
		AddInstruction("RAX,simm32", "0Did", {}, {cpuAMD64});
		AddInstruction("reg/mem8,imm8", "80/1ib", {}, {cpu8086});
		AddInstruction("reg/mem16,imm16", "81/1iw", {optO16}, {cpu8086});
		AddInstruction("reg/mem32,imm32", "81/1id", {optO32}, {cpu386});
		AddInstruction("reg/mem64,simm32", "81/1id", {}, {cpuAMD64});
		AddInstruction("reg/mem16,simm8", "83/1ib", {optO16}, {cpu8086});
		AddInstruction("reg/mem32,simm8", "83/1ib", {optO32}, {cpu386});
		AddInstruction("reg/mem64,simm8", "83/1ib", {}, {cpuAMD64});

		StartMnemonic(opORPD, "ORPD");
		AddInstruction("xmm1,xmm2/mem128", "660F56/r", {}, {cpuSSE2});

		StartMnemonic(opORPS, "ORPS");
		AddInstruction("xmm1,xmm2/mem128", "0F56/r", {}, {cpuSSE});

		StartMnemonic(opOUT, "OUT");
		AddInstruction("uimm8,AL", "E6ib", {}, {cpu8086});
		AddInstruction("uimm8,AX", "E7ib", {optO16}, {cpu8086});
		AddInstruction("uimm8,EAX", "E7ib", {optO32}, {cpu386});
		AddInstruction("DX,AL", "EE", {}, {cpu8086});
		AddInstruction("DX,AX", "EF", {optO16}, {cpu8086});
		AddInstruction("DX,EAX", "EF", {optO32}, {cpu386});

		StartMnemonic(opOUTS, "OUTS");
		AddInstruction("DX,mem8", "6E", {}, {cpu186});
		AddInstruction("DX,mem16", "6F", {optO16}, {cpu186});
		AddInstruction("DX,mem32", "6F", {optO32}, {cpu386});

		StartMnemonic(opOUTSB, "OUTSB");
		AddInstruction("", "6E", {}, {cpu186});

		StartMnemonic(opOUTSD, "OUTSD");
		AddInstruction("", "6F", {optO32}, {cpu386});

		StartMnemonic(opOUTSW, "OUTSW");
		AddInstruction("", "6F", {optO16}, {cpu186});

		StartMnemonic(opPACKSSDW, "PACKSSDW");
		AddInstruction("xmm1,xmm2/mem128", "660F6B/r", {}, {cpuSSE2});
		AddInstruction("mmx1,mmx2/mem64", "0F6B/r", {}, {cpuMMX});

		StartMnemonic(opPACKSSWB, "PACKSSWB");
		AddInstruction("xmm1,xmm2/mem128", "660F63/r", {}, {cpuSSE2});
		AddInstruction("mmx1,mmx2/mem64", "0F63/r", {}, {cpuMMX});

		StartMnemonic(opPACKUSWB, "PACKUSWB");
		AddInstruction("xmm1,xmm2/mem128", "660F67/r", {}, {cpuSSE2});
		AddInstruction("mmx1,mmx2/mem64", "0F67/r", {}, {cpuMMX});

		StartMnemonic(opPADDB, "PADDB");
		AddInstruction("xmm1,xmm2/mem128", "660FFC/r", {}, {cpuSSE2});
		AddInstruction("mmx1,mmx2/mem64", "0FFC/r", {}, {cpuMMX});

		StartMnemonic(opPADDD, "PADDD");
		AddInstruction("xmm1,xmm2/mem128", "660FFE/r", {}, {cpuSSE2});
		AddInstruction("mmx1,mmx2/mem64", "0FFE/r", {}, {cpuMMX});

		StartMnemonic(opPADDQ, "PADDQ");
		AddInstruction("xmm1,xmm2/mem128", "660FD4/r", {}, {cpuSSE2});
		AddInstruction("mmx1,mmx2/mem64", "0FD4/r", {}, {cpuMMX});

		StartMnemonic(opPADDSB, "PADDSB");
		AddInstruction("xmm1,xmm2/mem128", "660FEC/r", {}, {cpuSSE2});
		AddInstruction("mmx1,mmx2/mem64", "0FEC/r", {}, {cpuMMX});

		StartMnemonic(opPADDSW, "PADDSW");
		AddInstruction("xmm1,xmm2/mem128", "660FED/r", {}, {cpuSSE2});
		AddInstruction("mmx1,mmx2/mem64", "0FED/r", {}, {cpuMMX});

		StartMnemonic(opPADDUSB, "PADDUSB");
		AddInstruction("xmm1,xmm2/mem128", "660FDC/r", {}, {cpuSSE2});
		AddInstruction("mmx1,mmx2/mem64", "0FDC/r", {}, {cpuMMX});

		StartMnemonic(opPADDUSW, "PADDUSW");
		AddInstruction("xmm1,xmm2/mem128", "660FDD/r", {}, {cpuSSE2});
		AddInstruction("mmx1,mmx2/mem64", "0FDD/r", {}, {cpuMMX});

		StartMnemonic(opPADDW, "PADDW");
		AddInstruction("xmm1,xmm2/mem128", "660FFD/r", {}, {cpuSSE2});
		AddInstruction("mmx1,mmx2/mem64", "0FFD/r", {}, {cpuMMX});

		StartMnemonic(opPAND, "PAND");
		AddInstruction("xmm1,xmm2/mem128", "660FDB/r", {}, {cpuSSE2});
		AddInstruction("mmx1,mmx2/mem64", "0FDB/r", {}, {cpuMMX});

		StartMnemonic(opPANDN, "PANDN");
		AddInstruction("xmm1,xmm2/mem128", "660FDF/r", {}, {cpuSSE2});
		AddInstruction("mmx1,mmx2/mem64", "0FDF/r", {}, {cpuMMX});

		StartMnemonic(opPAUSE, "PAUSE");
		AddInstruction("", "F390", {}, {cpuSSE2});

		StartMnemonic(opPAVGB, "PAVGB");
		AddInstruction("xmm1,xmm2/mem128", "660FE0/r", {}, {cpuSSE2});
		AddInstruction("mmx1,mmx2/mem64", "0FE0/r", {}, {cpuMMX});

		StartMnemonic(opPAVGUSB, "PAVGUSB");
		AddInstruction("mmx1,mmx2/mem64", "0F0F/rBF", {}, {cpu3DNow});

		StartMnemonic(opPAVGW, "PAVGW");
		AddInstruction("xmm1,xmm2/mem128", "660FE3/r", {}, {cpuSSE2});
		AddInstruction("mmx1,mmx2/mem64", "0FE3/r", {}, {cpuMMX});

		StartMnemonic(opPCMPEQB, "PCMPEQB");
		AddInstruction("xmm1,xmm2/mem128", "660F74/r", {}, {cpuSSE2});
		AddInstruction("mmx1,mmx2/mem64", "0F74/r", {}, {cpuMMX});

		StartMnemonic(opPCMPEQD, "PCMPEQD");
		AddInstruction("xmm1,xmm2/mem128", "660F76/r", {}, {cpuSSE2});
		AddInstruction("mmx1,mmx2/mem64", "0F76/r", {}, {cpuMMX});

		StartMnemonic(opPCMPEQW, "PCMPEQW");
		AddInstruction("xmm1,xmm2/mem128", "660F75/r", {}, {cpuSSE2});
		AddInstruction("mmx1,mmx2/mem64", "0F75/r", {}, {cpuMMX});

		StartMnemonic(opPCMPGTB, "PCMPGTB");
		AddInstruction("xmm1,xmm2/mem128", "660F64/r", {}, {cpuSSE2});
		AddInstruction("mmx1,mmx2/mem64", "0F64/r", {}, {cpuMMX});

		StartMnemonic(opPCMPGTD, "PCMPGTD");
		AddInstruction("xmm1,xmm2/mem128", "660F66/r", {}, {cpuSSE2});
		AddInstruction("mmx1,mmx2/mem64", "0F66/r", {}, {cpuMMX});

		StartMnemonic(opPCMPGTW, "PCMPGTW");
		AddInstruction("xmm1,xmm2/mem128", "660F65/r", {}, {cpuSSE2});
		AddInstruction("mmx1,mmx2/mem64", "0F65/r", {}, {cpuMMX});

		StartMnemonic(opPEXTRW, "PEXTRW");
		AddInstruction("reg32,xmm,uimm8", "660FC5/rib", {}, {cpuSSE2});
		AddInstruction("reg32,mmx,uimm8", "0FC5/rib", {}, {cpuMMX});

		StartMnemonic(opPF2ID, "PF2ID");
		AddInstruction("mmx1,mmx2/mem64", "0F0F/r1D", {}, {cpu3DNow});

		StartMnemonic(opPF2IW, "PF2IW");
		AddInstruction("mmx1,mmx2/mem64", "0F0F/r1C", {}, {cpu3DNow});

		StartMnemonic(opPFACC, "PFACC");
		AddInstruction("mmx1,mmx2/mem64", "0F0F/rAE", {}, {cpu3DNow});

		StartMnemonic(opPFADD, "PFADD");
		AddInstruction("mmx1,mmx2/mem64", "0F0F/r9E", {}, {cpu3DNow});

		StartMnemonic(opPFCMPEQ, "PFCMPEQ");
		AddInstruction("mmx1,mmx2/mem64", "0F0F/rB0", {}, {cpu3DNow});

		StartMnemonic(opPFCMPGE, "PFCMPGE");
		AddInstruction("mmx1,mmx2/mem64", "0F0F/r90", {}, {cpu3DNow});

		StartMnemonic(opPFCMPGT, "PFCMPGT");
		AddInstruction("mmx1,mmx2/mem64", "0F0F/rA0", {}, {cpu3DNow});

		StartMnemonic(opPFMAX, "PFMAX");
		AddInstruction("mmx1,mmx2/mem64", "0F0F/rA4", {}, {cpu3DNow});

		StartMnemonic(opPFMIN, "PFMIN");
		AddInstruction("mmx1,mmx2/mem64", "0F0F/r94", {}, {cpu3DNow});

		StartMnemonic(opPFMUL, "PFMUL");
		AddInstruction("mmx1,mmx2/mem64", "0F0F/rB4", {}, {cpu3DNow});

		StartMnemonic(opPFNACC, "PFNACC");
		AddInstruction("mmx1,mmx2/mem64", "0F0F/r8A", {}, {cpu3DNow});

		StartMnemonic(opPFPNACC, "PFPNACC");
		AddInstruction("mmx1,mmx2/mem64", "0F0F/r8E", {}, {cpu3DNow});

		StartMnemonic(opPFRCP, "PFRCP");
		AddInstruction("mmx1,mmx2/mem64", "0F0F/r96", {}, {cpu3DNow});

		StartMnemonic(opPFRCPIT1, "PFRCPIT1");
		AddInstruction("mmx1,mmx2/mem64", "0F0F/rA6", {}, {cpu3DNow});

		StartMnemonic(opPFRCPIT2, "PFRCPIT2");
		AddInstruction("mmx1,mmx2/mem64", "0F0F/rB6", {}, {cpu3DNow});

		StartMnemonic(opPFRSQIT1, "PFRSQIT1");
		AddInstruction("mmx1,mmx2/mem64", "0F0F/rA7", {}, {cpu3DNow});

		StartMnemonic(opPFRSQRT, "PFRSQRT");
		AddInstruction("mmx1,mmx2/mem64", "0F0F/r97", {}, {cpu3DNow});

		StartMnemonic(opPFSUB, "PFSUB");
		AddInstruction("mmx1,mmx2/mem64", "0F0F/r9A", {}, {cpu3DNow});

		StartMnemonic(opPFSUBR, "PFSUBR");
		AddInstruction("mmx1,mmx2/mem64", "0F0F/rAA", {}, {cpu3DNow});

		StartMnemonic(opPI2FD, "PI2FD");
		AddInstruction("mmx1,mmx2/mem64", "0F0F/r0D", {}, {cpu3DNow});

		StartMnemonic(opPI2FW, "PI2FW");
		AddInstruction("mmx1,mmx2/mem64", "0F0F/r0C", {}, {cpu3DNow});

		StartMnemonic(opPINSRW, "PINSRW");
		AddInstruction("xmm,reg/mem16,uimm8", "660FC4/rib", {}, {cpuSSE2});
		AddInstruction("xmm,reg/mem32,uimm8", "660FC4/rib", {}, {cpuSSE2});
		AddInstruction("mmx,reg/mem16,uimm8", "0FC4/rib", {}, {cpuMMX});
		AddInstruction("mmx,reg/mem32,uimm8", "0FC4/rib", {}, {cpuMMX});

		StartMnemonic(opPMADDWD, "PMADDWD");
		AddInstruction("xmm1,xmm2/mem128", "660FF5/r", {}, {cpuSSE2});
		AddInstruction("mmx1,mmx2/mem64", "0FF5/r", {}, {cpuMMX});

		StartMnemonic(opPMAXSW, "PMAXSW");
		AddInstruction("xmm1,xmm2/mem128", "660FEE/r", {}, {cpuSSE2});
		AddInstruction("mmx1,mmx2/mem64", "0FEE/r", {}, {cpuMMX});

		StartMnemonic(opPMAXUB, "PMAXUB");
		AddInstruction("xmm1,xmm2/mem128", "660FDE/r", {}, {cpuSSE2});
		AddInstruction("mmx1,mmx2/mem64", "0FDE/r", {}, {cpuMMX});

		StartMnemonic(opPMINSW, "PMINSW");
		AddInstruction("xmm1,xmm2/mem128", "660FEA/r", {}, {cpuSSE2});
		AddInstruction("mmx1,mmx2/mem64", "0FEA/r", {}, {cpuMMX});

		StartMnemonic(opPMINUB, "PMINUB");
		AddInstruction("xmm1,xmm2/mem128", "660FDA/r", {}, {cpuSSE2});
		AddInstruction("mmx1,mmx2/mem64", "0FDA/r", {}, {cpuMMX});

		StartMnemonic(opPMOVMSKB, "PMOVMSKB");
		AddInstruction("reg32,xmm", "660FD7/r", {}, {cpuSSE2});
		AddInstruction("reg32,mmx", "0FD7/r", {}, {cpuMMX});

		StartMnemonic(opPMULHRW, "PMULHRW");
		AddInstruction("mmx1,mmx2/mem64", "0F0F/rB7", {}, {cpu3DNow});

		StartMnemonic(opPMULHUW, "PMULHUW");
		AddInstruction("xmm1,xmm2/mem128", "660FE4/r", {}, {cpuSSE2});
		AddInstruction("mmx1,mmx2/mem64", "0FE4/r", {}, {cpuMMX});

		StartMnemonic(opPMULHW, "PMULHW");
		AddInstruction("xmm1,xmm2/mem128", "660FE5/r", {}, {cpuSSE2});
		AddInstruction("mmx1,mmx2/mem64", "0FE5/r", {}, {cpuMMX});

		StartMnemonic(opPMULLW, "PMULLW");
		AddInstruction("xmm1,xmm2/mem128", "660FD5/r", {}, {cpuSSE2});
		AddInstruction("mmx1,mmx2/mem64", "0FD5/r", {}, {cpuMMX});

		StartMnemonic(opPMULUDQ, "PMULUDQ");
		AddInstruction("xmm1,xmm2/mem128", "660FF4/r", {}, {cpuSSE2});
		AddInstruction("mmx1,mmx2/mem64", "0FF4/r", {}, {cpuSSE2});

		StartMnemonic(opPOP, "POP");
		AddInstruction("reg16", "58rw", {optO16}, {cpu8086});
		AddInstruction("reg32", "58rd", {optO32}, {cpu386});
		AddInstruction("reg64", "58rq", {}, {cpuAMD64});
		AddInstruction("reg/mem16", "8F/0", {optO16}, {cpu8086});
		AddInstruction("reg/mem32", "8F/0", {optO32}, {cpu386});
		AddInstruction("reg/mem64", "8F/0", {}, {cpuAMD64});
		AddInstruction("DS", "1F", {optNot64}, {cpu8086});
		AddInstruction("ES", "07", {optNot64}, {cpu8086});
		AddInstruction("SS", "17", {optNot64}, {cpu8086});
		AddInstruction("FS", "0FA1", {}, {cpu386});
		AddInstruction("GS", "0FA9", {}, {cpu386});

		StartMnemonic(opPOPA, "POPA");
		AddInstruction("", "61", {optNot64}, {cpu186});

		StartMnemonic(opPOPAD, "POPAD");
		AddInstruction("", "61", {optO32,optNot64}, {cpu386});

		StartMnemonic(opPOPAW, "POPAW");
		AddInstruction("", "61", {optO16,optNot64}, {cpu186});

		StartMnemonic(opPOPF, "POPF");
		AddInstruction("", "9D", {}, {cpu8086});

		StartMnemonic(opPOPFD, "POPFD");
		AddInstruction("", "9D", {optO32}, {cpu386});

		StartMnemonic(opPOPFQ, "POPFQ");
		AddInstruction("", "9D", {}, {cpuAMD64});

		StartMnemonic(opPOR, "POR");
		AddInstruction("xmm1,xmm2/mem128", "660FEB/r", {}, {cpuSSE2});
		AddInstruction("mmx1,mmx2/mem64", "0FEB/r", {}, {cpuMMX});

		StartMnemonic(opPREFETCH, "PREFETCH");
		AddInstruction("mem8", "0F0D/0", {}, {cpu3DNow});

		StartMnemonic(opPREFETCHNTA, "PREFETCHNTA");
		AddInstruction("mem8", "0F18/0", {}, {cpuSSE,cpuMMX});

		StartMnemonic(opPREFETCHT0, "PREFETCHT0");
		AddInstruction("mem8", "0F18/1", {}, {cpuSSE,cpuMMX});

		StartMnemonic(opPREFETCHT1, "PREFETCHT1");
		AddInstruction("mem8", "0F18/2", {}, {cpuSSE,cpuMMX});

		StartMnemonic(opPREFETCHT2, "PREFETCHT2");
		AddInstruction("mem8", "0F18/3", {}, {cpuSSE,cpuMMX});

		StartMnemonic(opPREFETCHW, "PREFETCHW");
		AddInstruction("mem8", "0F0D/1", {}, {cpu3DNow});

		StartMnemonic(opPSADBW, "PSADBW");
		AddInstruction("xmm1,xmm2/mem128", "660FF6/r", {}, {cpuSSE2});
		AddInstruction("mmx1,mmx2/mem64", "0FF6/r", {}, {cpuMMX});

		StartMnemonic(opPSHUFD, "PSHUFD");
		AddInstruction("xmm1,xmm2/mem128,uimm8", "660F70/rib", {}, {cpuSSE2});

		StartMnemonic(opPSHUFHW, "PSHUFHW");
		AddInstruction("xmm1,xmm2/mem128,uimm8", "F30F70/rib", {}, {cpuSSE2});

		StartMnemonic(opPSHUFLW, "PSHUFLW");
		AddInstruction("xmm1,xmm2/mem128,uimm8", "F20F70/rib", {}, {cpuSSE2});

		StartMnemonic(opPSHUFW, "PSHUFW");
		AddInstruction("mmx1,mmx2/mem64,imm8", "0F70/rib", {}, {cpuSSE2});

		StartMnemonic(opPSLLD, "PSLLD");
		AddInstruction("xmm1,xmm2/mem128", "660FF2/r", {}, {cpuSSE2});
		AddInstruction("xmm,uimm8", "660F72/6ib", {}, {cpuSSE2});
		AddInstruction("mmx1,mmx2/mem64", "0FF2/r", {}, {cpuMMX});
		AddInstruction("mmx,imm8", "0F72/6ib", {}, {cpuMMX});

		StartMnemonic(opPSLLDQ, "PSLLDQ");
		AddInstruction("xmm,uimm8", "660F73/7ib", {}, {cpuSSE2});

		StartMnemonic(opPSLLQ, "PSLLQ");
		AddInstruction("xmm1,xmm2/mem128", "660FF3/r", {}, {cpuSSE2});
		AddInstruction("xmm,uimm8", "660F73/6ib", {}, {cpuSSE2});
		AddInstruction("mmx1,mmx2/mem64", "0FF3/r", {}, {cpuMMX});
		AddInstruction("mmx,imm8", "0F73/6ib", {}, {cpuMMX});

		StartMnemonic(opPSLLW, "PSLLW");
		AddInstruction("xmm1,xmm2/mem128", "660FF1/r", {}, {cpuSSE2});
		AddInstruction("xmm,uimm8", "660F71/6ib", {}, {cpuSSE2});
		AddInstruction("mmx1,mmx2/mem64", "0FF1/r", {}, {cpuMMX});
		AddInstruction("mmx,imm8", "0F71/6ib", {}, {cpuMMX});

		StartMnemonic(opPSRAD, "PSRAD");
		AddInstruction("xmm1,xmm2/mem128", "660FE2/r", {}, {cpuSSE2});
		AddInstruction("xmm,uimm8", "660F72/4ib", {}, {cpuSSE2});
		AddInstruction("mmx1,mmx2/mem64", "0FE2/r", {}, {cpuMMX});
		AddInstruction("mmx,imm8", "0F72/4ib", {}, {cpuMMX});

		StartMnemonic(opPSRAW, "PSRAW");
		AddInstruction("xmm1,xmm2/mem128", "660FE1/r", {}, {cpuSSE2});
		AddInstruction("xmm,uimm8", "660F71/4ib", {}, {cpuSSE2});
		AddInstruction("mmx1,mmx2/mem64", "0FE1/r", {}, {cpuMMX});
		AddInstruction("mmx,imm8", "0F71/4ib", {}, {cpuMMX});

		StartMnemonic(opPSRLD, "PSRLD");
		AddInstruction("xmm1,xmm2/mem128", "660FD2/r", {}, {cpuSSE2});
		AddInstruction("xmm,uimm8", "660F72/2ib", {}, {cpuSSE2});
		AddInstruction("mmx1,mmx2/mem64", "0FD2/r", {}, {cpuMMX});
		AddInstruction("mmx,imm8", "0F72/2ib", {}, {cpuMMX});

		StartMnemonic(opPSRLDQ, "PSRLDQ");
		AddInstruction("xmm,uimm8", "660F73/3ib", {}, {cpuSSE2});

		StartMnemonic(opPSRLQ, "PSRLQ");
		AddInstruction("xmm1,xmm2/mem128", "660FD3/r", {}, {cpuSSE2});
		AddInstruction("xmm,uimm8", "660F73/2ib", {}, {cpuSSE2});
		AddInstruction("mmx1,mmx2/mem64", "0FD3/r", {}, {cpuMMX});
		AddInstruction("mmx,imm8", "0F73/2ib", {}, {cpuMMX});

		StartMnemonic(opPSRLW, "PSRLW");
		AddInstruction("xmm1,xmm2/mem128", "660FD1/r", {}, {cpuSSE2});
		AddInstruction("xmm,uimm8", "660F71/2ib", {}, {cpuSSE2});
		AddInstruction("mmx1,mmx2/mem64", "0FD1/r", {}, {cpuMMX});
		AddInstruction("mmx,imm8", "0F71/2ib", {}, {cpuMMX});

		StartMnemonic(opPSUBB, "PSUBB");
		AddInstruction("xmm1,xmm2/mem128", "660FF8/r", {}, {cpuSSE2});
		AddInstruction("mmx1,mmx2/mem64", "0FF8/r", {}, {cpuMMX});

		StartMnemonic(opPSUBD, "PSUBD");
		AddInstruction("xmm1,xmm2/mem128", "660FFA/r", {}, {cpuSSE2});
		AddInstruction("mmx1,mmx2/mem64", "0FFA/r", {}, {cpuMMX});

		StartMnemonic(opPSUBQ, "PSUBQ");
		AddInstruction("xmm1,xmm2/mem128", "660FFB/r", {}, {cpuSSE2});
		AddInstruction("mmx1,mmx2/mem64", "0FFB/r", {}, {cpuMMX});

		StartMnemonic(opPSUBSB, "PSUBSB");
		AddInstruction("xmm1,xmm2/mem128", "660FE8/r", {}, {cpuSSE2});
		AddInstruction("mmx1,mmx2/mem64", "0FE8/r", {}, {cpuMMX});

		StartMnemonic(opPSUBSW, "PSUBSW");
		AddInstruction("xmm1,xmm2/mem128", "660FE9/r", {}, {cpuSSE2});
		AddInstruction("mmx1,mmx2/mem64", "0FE9/r", {}, {cpuMMX});

		StartMnemonic(opPSUBUSB, "PSUBUSB");
		AddInstruction("xmm1,xmm2/mem128", "660FD8/r", {}, {cpuSSE2});
		AddInstruction("mmx1,mmx2/mem64", "0FD8/r", {}, {cpuMMX});

		StartMnemonic(opPSUBUSW, "PSUBUSW");
		AddInstruction("xmm1,xmm2/mem128", "660FD9/r", {}, {cpuSSE2});
		AddInstruction("mmx1,mmx2/mem64", "0FD9/r", {}, {cpuMMX});

		StartMnemonic(opPSUBW, "PSUBW");
		AddInstruction("xmm1,xmm2/mem128", "660FF9/r", {}, {cpuSSE2});
		AddInstruction("mmx1,mmx2/mem64", "0FF9/r", {}, {cpuMMX});

		StartMnemonic(opPSWAPD, "PSWAPD");
		AddInstruction("mmx1,mmx2/mem64", "0F0F/rBB", {}, {cpu3DNow});

		StartMnemonic(opPUNPCKHBW, "PUNPCKHBW");
		AddInstruction("xmm1,xmm2/mem128", "660F68/r", {}, {cpuSSE2});
		AddInstruction("mmx1,mmx2/mem64", "0F68/r", {}, {cpuMMX});

		StartMnemonic(opPUNPCKHDQ, "PUNPCKHDQ");
		AddInstruction("xmm1,xmm2/mem128", "660F6A/r", {}, {cpuSSE2});
		AddInstruction("mmx1,mmx2/mem64", "0F6A/r", {}, {cpuMMX});

		StartMnemonic(opPUNPCKHQDQ, "PUNPCKHQDQ");
		AddInstruction("xmm1,xmm2/mem128", "660F6D/r", {}, {cpuSSE2});

		StartMnemonic(opPUNPCKHWD, "PUNPCKHWD");
		AddInstruction("xmm1,xmm2/mem128", "660F69/r", {}, {cpuSSE2});
		AddInstruction("mmx1,mmx2/mem64", "0F69/r", {}, {cpuMMX});

		StartMnemonic(opPUNPCKLBW, "PUNPCKLBW");
		AddInstruction("xmm1,xmm2/mem128", "660F60/r", {}, {cpuSSE2});
		AddInstruction("mmx1,mmx2/mem32", "0F60/r", {}, {cpuMMX});

		StartMnemonic(opPUNPCKLDQ, "PUNPCKLDQ");
		AddInstruction("xmm1,xmm2/mem128", "660F62/r", {}, {cpuSSE2});
		AddInstruction("mmx1,mmx2/mem32", "0F62/r", {}, {cpuMMX});

		StartMnemonic(opPUNPCKLQDQ, "PUNPCKLQDQ");
		AddInstruction("xmm1,xmm2/mem128", "660F6C/r", {}, {cpuSSE2});

		StartMnemonic(opPUNPCKLWD, "PUNPCKLWD");
		AddInstruction("xmm1,xmm2/mem128", "660F61/r", {}, {cpuSSE2});
		AddInstruction("mmx1,mmx2/mem32", "0F61/r", {}, {cpuMMX});

		StartMnemonic(opPUSH, "PUSH");
		AddInstruction("reg16", "50rw", {optO16}, {cpu8086});
		AddInstruction("reg32", "50rd", {optO32}, {cpu386});
		AddInstruction("reg64", "50rq", {}, {cpuAMD64});
		AddInstruction("reg/mem16", "FF/6", {optO16}, {cpu8086});
		AddInstruction("reg/mem32", "FF/6", {optO32}, {cpu386});
		AddInstruction("reg/mem64", "FF/6", {}, {cpuAMD64});
		AddInstruction("imm8", "6Aib", {}, {cpu186});
		AddInstruction("imm16", "68iw", {}, {cpu186});
		AddInstruction("imm32", "68id", {optNot64}, {cpu186});
		AddInstruction("simm32", "68id", {}, {cpuAMD64});
		AddInstruction("CS", "0E", {optNot64}, {cpu8086});
		AddInstruction("SS", "16", {optNot64}, {cpu8086});
		AddInstruction("DS", "1E", {optNot64}, {cpu8086});
		AddInstruction("ES", "06", {optNot64}, {cpu8086});
		AddInstruction("FS", "0FA0", {}, {cpu386});
		AddInstruction("GS", "0FA8", {}, {cpu386});

		StartMnemonic(opPUSHA, "PUSHA");
		AddInstruction("", "60", {optNot64}, {cpu186});

		StartMnemonic(opPUSHAD, "PUSHAD");
		AddInstruction("", "60", {optO32,optNot64}, {cpu386});

		StartMnemonic(opPUSHF, "PUSHF");
		AddInstruction("", "9C", {}, {cpu8086});

		StartMnemonic(opPUSHFD, "PUSHFD");
		AddInstruction("", "9C", {optO32}, {cpu386});

		StartMnemonic(opPUSHFQ, "PUSHFQ");
		AddInstruction("", "9C", {}, {cpuAMD64});

		StartMnemonic(opPXOR, "PXOR");
		AddInstruction("xmm1,xmm2/mem128", "660FEF/r", {}, {cpuSSE2});
		AddInstruction("mmx1,mmx2/mem64", "0FEF/r", {}, {cpuMMX});

		StartMnemonic(opRCL, "RCL");
		AddInstruction("reg/mem8,1", "D0/2", {}, {cpu8086});
		AddInstruction("reg/mem8,CL", "D2/2", {}, {cpu8086});
		AddInstruction("reg/mem8,uimm8", "C0/2ib", {}, {cpu186});
		AddInstruction("reg/mem16,1", "D1/2", {optO16}, {cpu8086});
		AddInstruction("reg/mem16,CL", "D3/2", {optO16}, {cpu8086});
		AddInstruction("reg/mem16,uimm8", "C1/2ib", {optO16}, {cpu186});
		AddInstruction("reg/mem32,1", "D1/2", {optO32}, {cpu386});
		AddInstruction("reg/mem32,CL", "D3/2", {optO32}, {cpu386});
		AddInstruction("reg/mem32,uimm8", "C1/2ib", {optO32}, {cpu386});
		AddInstruction("reg/mem64,1", "D1/2", {}, {cpuAMD64});
		AddInstruction("reg/mem64,CL", "D3/2", {}, {cpuAMD64});
		AddInstruction("reg/mem64,uimm8", "C1/2ib", {}, {cpuAMD64});

		StartMnemonic(opRCPPS, "RCPPS");
		AddInstruction("xmm1,xmm2/mem128", "0F53/r", {}, {cpuSSE});

		StartMnemonic(opRCPSS, "RCPSS");
		AddInstruction("xmm1,xmm2/mem32", "F30F53/r", {}, {cpuSSE});

		StartMnemonic(opRCR, "RCR");
		AddInstruction("reg/mem8,1", "D0/3", {}, {cpu8086});
		AddInstruction("reg/mem8,CL", "D2/3", {}, {cpu8086});
		AddInstruction("reg/mem8,uimm8", "C0/3ib", {}, {cpu186});
		AddInstruction("reg/mem16,1", "D1/3", {optO16}, {cpu8086});
		AddInstruction("reg/mem16,CL", "D3/3", {optO16}, {cpu8086});
		AddInstruction("reg/mem16,uimm8", "C1/3ib", {optO16}, {cpu186});
		AddInstruction("reg/mem32,1", "D1/3", {optO32}, {cpu386});
		AddInstruction("reg/mem32,CL", "D3/3", {optO32}, {cpu386});
		AddInstruction("reg/mem32,uimm8", "C1/3ib", {optO32}, {cpu386});
		AddInstruction("reg/mem64,1", "D1/3", {}, {cpuAMD64});
		AddInstruction("reg/mem64,CL", "D3/3", {}, {cpuAMD64});
		AddInstruction("reg/mem64,uimm8", "C1/3ib", {}, {cpuAMD64});

		StartMnemonic(opRDMSR, "RDMSR");
		AddInstruction("", "0F32", {}, {cpuPentium,cpuPrivileged});

		StartMnemonic(opRDPMC, "RDPMC");
		AddInstruction("", "0F33", {}, {cpuP6});

		StartMnemonic(opRDTSC, "RDTSC");
		AddInstruction("", "0F31", {}, {cpuPentium});

		StartMnemonic(opRDTSCP, "RDTSCP");
		AddInstruction("", "0F01F9", {}, {cpuPentium});

		StartMnemonic(opRET, "RET");
		AddInstruction("", "C3", {}, {cpu8086});
		AddInstruction("uimm16", "C2iw", {}, {cpu8086});

		StartMnemonic(opRETF, "RETF");
		AddInstruction("", "CB", {}, {cpu8086});
		AddInstruction("uimm16", "CAiw", {}, {cpu8086});

		StartMnemonic(opROL, "ROL");
		AddInstruction("reg/mem8,1", "D0/0", {}, {cpu8086});
		AddInstruction("reg/mem8,CL", "D2/0", {}, {cpu8086});
		AddInstruction("reg/mem8,uimm8", "C0/0ib", {}, {cpu186});
		AddInstruction("reg/mem16,1", "D1/0", {optO16}, {cpu8086});
		AddInstruction("reg/mem16,CL", "D3/0", {optO16}, {cpu8086});
		AddInstruction("reg/mem16,uimm8", "C1/0ib", {optO16}, {cpu186});
		AddInstruction("reg/mem32,1", "D1/0", {optO32}, {cpu386});
		AddInstruction("reg/mem32,CL", "D3/0", {optO32}, {cpu386});
		AddInstruction("reg/mem32,uimm8", "C1/0ib", {optO32}, {cpu386});
		AddInstruction("reg/mem64,1", "D1/0", {}, {cpuAMD64});
		AddInstruction("reg/mem64,CL", "D3/0", {}, {cpuAMD64});
		AddInstruction("reg/mem64,uimm8", "C1/0ib", {}, {cpuAMD64});

		StartMnemonic(opROR, "ROR");
		AddInstruction("reg/mem8,1", "D0/1", {}, {cpu8086});
		AddInstruction("reg/mem8,CL", "D2/1", {}, {cpu8086});
		AddInstruction("reg/mem8,uimm8", "C0/1ib", {}, {cpu186});
		AddInstruction("reg/mem16,1", "D1/1", {optO16}, {cpu8086});
		AddInstruction("reg/mem16,CL", "D3/1", {optO16}, {cpu8086});
		AddInstruction("reg/mem16,uimm8", "C1/1ib", {optO16}, {cpu186});
		AddInstruction("reg/mem32,1", "D1/1", {optO32}, {cpu386});
		AddInstruction("reg/mem32,CL", "D3/1", {optO32}, {cpu386});
		AddInstruction("reg/mem32,uimm8", "C1/1ib", {optO32}, {cpu386});
		AddInstruction("reg/mem64,1", "D1/1", {}, {cpuAMD64});
		AddInstruction("reg/mem64,CL", "D3/1", {}, {cpuAMD64});
		AddInstruction("reg/mem64,uimm8", "C1/1ib", {}, {cpuAMD64});

		StartMnemonic(opRSM, "RSM");
		AddInstruction("", "0FAA", {}, {});

		StartMnemonic(opRSQRTPS, "RSQRTPS");
		AddInstruction("xmm1,xmm2/mem128", "0F52/r", {}, {cpuSSE});

		StartMnemonic(opRSQRTSS, "RSQRTSS");
		AddInstruction("xmm1,xmm2/mem32", "F30F52/r", {}, {cpuSSE});

		StartMnemonic(opSAHF, "SAHF");
		AddInstruction("", "9E", {}, {cpu8086});

		StartMnemonic(opSAL, "SAL");
		AddInstruction("reg/mem8,1", "D0/4", {}, {cpu8086});
		AddInstruction("reg/mem8,CL", "D2/4", {}, {cpu8086});
		AddInstruction("reg/mem8,uimm8", "C0/4ib", {}, {cpu186});
		AddInstruction("reg/mem16,1", "D1/4", {optO16}, {cpu8086});
		AddInstruction("reg/mem16,CL", "D3/4", {optO16}, {cpu8086});
		AddInstruction("reg/mem16,uimm8", "C1/4ib", {optO16}, {cpu186});
		AddInstruction("reg/mem32,1", "D1/4", {optO32}, {cpu386});
		AddInstruction("reg/mem32,CL", "D3/4", {optO32}, {cpu386});
		AddInstruction("reg/mem32,uimm8", "C1/4ib", {optO32}, {cpu386});
		AddInstruction("reg/mem64,1", "D1/4", {}, {cpuAMD64});
		AddInstruction("reg/mem64,CL", "D3/4", {}, {cpuAMD64});
		AddInstruction("reg/mem64,uimm8", "C1/4ib", {}, {cpuAMD64});

		StartMnemonic(opSAR, "SAR");
		AddInstruction("reg/mem8,1", "D0/7", {}, {cpu8086});
		AddInstruction("reg/mem8,CL", "D2/7", {}, {cpu8086});
		AddInstruction("reg/mem8,uimm8", "C0/7ib", {}, {cpu186});
		AddInstruction("reg/mem16,1", "D1/7", {optO16}, {cpu8086});
		AddInstruction("reg/mem16,CL", "D3/7", {optO16}, {cpu8086});
		AddInstruction("reg/mem16,uimm8", "C1/7ib", {optO16}, {cpu186});
		AddInstruction("reg/mem32,1", "D1/7", {optO32}, {cpu386});
		AddInstruction("reg/mem32,CL", "D3/7", {optO32}, {cpu386});
		AddInstruction("reg/mem32,uimm8", "C1/7ib", {optO32}, {cpu386});
		AddInstruction("reg/mem64,1", "D1/7", {}, {cpuAMD64});
		AddInstruction("reg/mem64,CL", "D3/7", {}, {cpuAMD64});
		AddInstruction("reg/mem64,uimm8", "C1/7ib", {}, {cpuAMD64});

		StartMnemonic(opSBB, "SBB");
		AddInstruction("reg/mem8,reg8", "18/r", {}, {cpu8086});
		AddInstruction("reg/mem16,reg16", "19/r", {optO16}, {cpu8086});
		AddInstruction("reg/mem32,reg32", "19/r", {optO32}, {cpu386});
		AddInstruction("reg/mem64,reg64", "19/r", {}, {cpuAMD64});
		AddInstruction("reg8,reg/mem8", "1A/r", {}, {cpu8086});
		AddInstruction("reg16,reg/mem16", "1B/r", {optO16}, {cpu8086});
		AddInstruction("reg32,reg/mem32", "1B/r", {optO32}, {cpu386});
		AddInstruction("reg64,reg/mem64", "1B/r", {}, {cpuAMD64});
		AddInstruction("AL,imm8", "1Cib", {}, {cpu8086});
		AddInstruction("AX,imm16", "1Diw", {optO16}, {cpu8086});
		AddInstruction("EAX,imm32", "1Did", {optO32}, {cpu386});
		AddInstruction("RAX,simm32", "1Did", {}, {cpuAMD64});
		AddInstruction("reg/mem8,imm8", "80/3ib", {}, {cpu8086});
		AddInstruction("reg/mem16,imm16", "81/3iw", {optO16}, {cpu8086});
		AddInstruction("reg/mem32,imm32", "81/3id", {optO32}, {cpu386});
		AddInstruction("reg/mem64,simm32", "81/3id", {}, {cpuAMD64});
		AddInstruction("reg/mem16,simm8", "83/3ib", {optO16}, {cpu8086});
		AddInstruction("reg/mem32,simm8", "83/3ib", {optO32}, {cpu386});
		AddInstruction("reg/mem64,simm8", "83/3ib", {}, {cpuAMD64});

		StartMnemonic(opSCAS, "SCAS");
		AddInstruction("mem8", "AE", {}, {cpu8086});
		AddInstruction("mem16", "AF", {optO16}, {cpu8086});
		AddInstruction("mem32", "AF", {optO32}, {cpu386});
		AddInstruction("mem64", "AF", {}, {cpuAMD64});

		StartMnemonic(opSCASB, "SCASB");
		AddInstruction("", "AE", {}, {cpu8086});

		StartMnemonic(opSCASD, "SCASD");
		AddInstruction("", "AF", {optO32}, {cpu386});

		StartMnemonic(opSCASQ, "SCASQ");
		AddInstruction("", "AF", {}, {cpuAMD64});

		StartMnemonic(opSCASW, "SCASW");
		AddInstruction("", "AF", {optO16}, {cpu8086});

		StartMnemonic(opSETA, "SETA");
		AddInstruction("reg/mem8", "0F97/0", {}, {cpu386});

		StartMnemonic(opSETAE, "SETAE");
		AddInstruction("reg/mem8", "0F93/0", {}, {cpu386});

		StartMnemonic(opSETB, "SETB");
		AddInstruction("reg/mem8", "0F92/0", {}, {cpu386});

		StartMnemonic(opSETBE, "SETBE");
		AddInstruction("reg/mem8", "0F96/0", {}, {cpu386});

		StartMnemonic(opSETC, "SETC");
		AddInstruction("reg/mem8", "0F92/0", {}, {cpu386});

		StartMnemonic(opSETE, "SETE");
		AddInstruction("reg/mem8", "0F94/0", {}, {cpu386});

		StartMnemonic(opSETG, "SETG");
		AddInstruction("reg/mem8", "0F9F/0", {}, {cpu386});

		StartMnemonic(opSETGE, "SETGE");
		AddInstruction("reg/mem8", "0F9D/0", {}, {cpu386});

		StartMnemonic(opSETL, "SETL");
		AddInstruction("reg/mem8", "0F9C/0", {}, {cpu386});

		StartMnemonic(opSETLE, "SETLE");
		AddInstruction("reg/mem8", "0F9E/0", {}, {cpu386});

		StartMnemonic(opSETNA, "SETNA");
		AddInstruction("reg/mem8", "0F96/0", {}, {cpu386});

		StartMnemonic(opSETNAE, "SETNAE");
		AddInstruction("reg/mem8", "0F92/0", {}, {cpu386});

		StartMnemonic(opSETNB, "SETNB");
		AddInstruction("reg/mem8", "0F93/0", {}, {cpu386});

		StartMnemonic(opSETNBE, "SETNBE");
		AddInstruction("reg/mem8", "0F97/0", {}, {cpu386});

		StartMnemonic(opSETNC, "SETNC");
		AddInstruction("reg/mem8", "0F93/0", {}, {cpu386});

		StartMnemonic(opSETNE, "SETNE");
		AddInstruction("reg/mem8", "0F95/0", {}, {cpu386});

		StartMnemonic(opSETNG, "SETNG");
		AddInstruction("reg/mem8", "0F9E/0", {}, {cpu386});

		StartMnemonic(opSETNGE, "SETNGE");
		AddInstruction("reg/mem8", "0F9C/0", {}, {cpu386});

		StartMnemonic(opSETNL, "SETNL");
		AddInstruction("reg/mem8", "0F9D/0", {}, {cpu386});

		StartMnemonic(opSETNLE, "SETNLE");
		AddInstruction("reg/mem8", "0F9F/0", {}, {cpu386});

		StartMnemonic(opSETNO, "SETNO");
		AddInstruction("reg/mem8", "0F91/0", {}, {cpu386});

		StartMnemonic(opSETNP, "SETNP");
		AddInstruction("reg/mem8", "0F9B/0", {}, {cpu386});

		StartMnemonic(opSETNS, "SETNS");
		AddInstruction("reg/mem8", "0F99/0", {}, {cpu386});

		StartMnemonic(opSETNZ, "SETNZ");
		AddInstruction("reg/mem8", "0F95/0", {}, {cpu386});

		StartMnemonic(opSETO, "SETO");
		AddInstruction("reg/mem8", "0F90/0", {}, {cpu386});

		StartMnemonic(opSETP, "SETP");
		AddInstruction("reg/mem8", "0F9A/0", {}, {cpu386});

		StartMnemonic(opSETPE, "SETPE");
		AddInstruction("reg/mem8", "0F9A/0", {}, {cpu386});

		StartMnemonic(opSETPO, "SETPO");
		AddInstruction("reg/mem8", "0F9B/0", {}, {cpu386});

		StartMnemonic(opSETS, "SETS");
		AddInstruction("reg/mem8", "0F98/0", {}, {cpu386});

		StartMnemonic(opSETZ, "SETZ");
		AddInstruction("reg/mem8", "0F94/0", {}, {cpu386});

		StartMnemonic(opSFENCE, "SFENCE");
		AddInstruction("", "0FAEF8", {}, {cpuSSE,cpuMMX});

		StartMnemonic(opSGDT, "SGDT");
		AddInstruction("mem16:32", "0F01/0", {}, {cpu286,cpuPrivileged});
		AddInstruction("mem16:64", "0F01/0", {}, {cpuAMD64,cpuPrivileged});

		StartMnemonic(opSHL, "SHL");
		AddInstruction("reg/mem8,1", "D0/4", {}, {cpu8086});
		AddInstruction("reg/mem8,CL", "D2/4", {}, {cpu8086});
		AddInstruction("reg/mem8,uimm8", "C0/4ib", {}, {cpu186});
		AddInstruction("reg/mem16,1", "D1/4", {optO16}, {cpu8086});
		AddInstruction("reg/mem16,CL", "D3/4", {optO16}, {cpu8086});
		AddInstruction("reg/mem16,uimm8", "C1/4ib", {optO16}, {cpu186});
		AddInstruction("reg/mem32,1", "D1/4", {optO32}, {cpu386});
		AddInstruction("reg/mem32,CL", "D3/4", {optO32}, {cpu386});
		AddInstruction("reg/mem32,uimm8", "C1/4ib", {optO32}, {cpu386});
		AddInstruction("reg/mem64,1", "D1/4", {}, {cpuAMD64});
		AddInstruction("reg/mem64,CL", "D3/4", {}, {cpuAMD64});
		AddInstruction("reg/mem64,uimm8", "C1/4ib", {}, {cpuAMD64});

		StartMnemonic(opSHLD, "SHLD");
		AddInstruction("reg/mem16,reg16,uimm8", "0FA4/rib", {optO16}, {cpu386});
		AddInstruction("reg/mem16,reg16,CL", "0FA5/r", {optO16}, {cpu386});
		AddInstruction("reg/mem32,reg32,uimm8", "0FA4/rib", {optO32}, {cpu386});
		AddInstruction("reg/mem32,reg32,CL", "0FA5/r", {optO32}, {cpu386});
		AddInstruction("reg/mem64,reg64,uimm8", "0FA4/rib", {}, {cpuAMD64});
		AddInstruction("reg/mem64,reg64,CL", "0FA5/r", {}, {cpuAMD64});

		StartMnemonic(opSHR, "SHR");
		AddInstruction("reg/mem8,1", "D0/5", {}, {cpu8086});
		AddInstruction("reg/mem8,CL", "D2/5", {}, {cpu8086});
		AddInstruction("reg/mem8,uimm8", "C0/5ib", {}, {cpu186});
		AddInstruction("reg/mem16,1", "D1/5", {optO16}, {cpu8086});
		AddInstruction("reg/mem16,CL", "D3/5", {optO16}, {cpu8086});
		AddInstruction("reg/mem16,uimm8", "C1/5ib", {optO16}, {cpu186});
		AddInstruction("reg/mem32,1", "D1/5", {optO32}, {cpu386});
		AddInstruction("reg/mem32,CL", "D3/5", {optO32}, {cpu386});
		AddInstruction("reg/mem32,uimm8", "C1/5ib", {optO32}, {cpu386});
		AddInstruction("reg/mem64,1", "D1/5", {}, {cpuAMD64});
		AddInstruction("reg/mem64,CL", "D3/5", {}, {cpuAMD64});
		AddInstruction("reg/mem64,uimm8", "C1/5ib", {}, {cpuAMD64});

		StartMnemonic(opSHRD, "SHRD");
		AddInstruction("reg/mem16,reg16,uimm8", "0FAC/rib", {optO16}, {cpu386});
		AddInstruction("reg/mem16,reg16,CL", "0FAD/r", {optO16}, {cpu386});
		AddInstruction("reg/mem32,reg32,uimm8", "0FAC/rib", {optO32}, {cpu386});
		AddInstruction("reg/mem32,reg32,CL", "0FAD/r", {optO32}, {cpu386});
		AddInstruction("reg/mem64,reg64,uimm8", "0FAC/rib", {}, {cpuAMD64});
		AddInstruction("reg/mem64,reg64,CL", "0FAD/r", {}, {cpuAMD64});

		StartMnemonic(opSHUFPD, "SHUFPD");
		AddInstruction("xmm1,xmm2/mem128,uimm8", "660FC6/rib", {}, {cpuSSE2});

		StartMnemonic(opSHUFPS, "SHUFPS");
		AddInstruction("xmm1,xmm2/mem128,uimm8", "0FC6/rib", {}, {cpuSSE});

		StartMnemonic(opSIDT, "SIDT");
		AddInstruction("mem16:32", "0F01/1", {}, {cpu286,cpuPrivileged});
		AddInstruction("mem16:64", "0F01/1", {}, {cpuAMD64,cpuPrivileged});

		StartMnemonic(opSKINIT, "SKINIT");
		AddInstruction("EAX", "0F01DE", {}, {cpuAMD64});

		StartMnemonic(opSLDT, "SLDT");
		AddInstruction("reg16", "0F00/0", {optO16}, {cpu286});
		AddInstruction("reg32", "0F00/0", {optO32}, {cpu386});
		AddInstruction("reg64", "0F00/0", {}, {cpuAMD64});
		AddInstruction("mem16", "0F00/0", {}, {cpu286});

		StartMnemonic(opSMSW, "SMSW");
		AddInstruction("reg16", "0F01/4", {optO16}, {cpu286});
		AddInstruction("reg32", "0F01/4", {optO32}, {cpu386});
		AddInstruction("reg64", "0F01/4", {}, {cpuAMD64});
		AddInstruction("mem16", "0F01/4", {}, {cpu286});

		StartMnemonic(opSQRTPD, "SQRTPD");
		AddInstruction("xmm1,xmm2/mem128", "660F51/r", {}, {cpuSSE2});

		StartMnemonic(opSQRTPS, "SQRTPS");
		AddInstruction("xmm1,xmm2/mem128", "0F51/r", {}, {cpuSSE});

		StartMnemonic(opSQRTSD, "SQRTSD");
		AddInstruction("xmm1,xmm2/mem64", "F20F51/r", {}, {cpuSSE2});

		StartMnemonic(opSQRTSS, "SQRTSS");
		AddInstruction("xmm1,xmm2/mem32", "F30F51/r", {}, {cpuSSE});

		StartMnemonic(opSTC, "STC");
		AddInstruction("", "F9", {}, {cpu8086});

		StartMnemonic(opSTD, "STD");
		AddInstruction("", "FD", {}, {cpu8086});

		StartMnemonic(opSTGI, "STGI");
		AddInstruction("", "0F01DC", {}, {cpuPentium});

		StartMnemonic(opSTI, "STI");
		AddInstruction("", "FB", {}, {cpu8086});

		StartMnemonic(opSTMXCSR, "STMXCSR");
		AddInstruction("mem32", "0FAE/3", {}, {cpuSSE});

		StartMnemonic(opSTOS, "STOS");
		AddInstruction("mem8", "AA", {}, {cpu8086});
		AddInstruction("mem16", "AB", {optO16}, {cpu8086});
		AddInstruction("mem32", "AB", {optO32}, {cpu386});
		AddInstruction("mem64", "AB", {}, {cpuAMD64});

		StartMnemonic(opSTOSB, "STOSB");
		AddInstruction("", "AA", {}, {cpu8086});

		StartMnemonic(opSTOSD, "STOSD");
		AddInstruction("", "AB", {optO32}, {cpu386});

		StartMnemonic(opSTOSQ, "STOSQ");
		AddInstruction("", "AB", {}, {cpuAMD64});

		StartMnemonic(opSTOSW, "STOSW");
		AddInstruction("", "AB", {optO16}, {cpu8086});

		StartMnemonic(opSTR, "STR");
		AddInstruction("reg16", "0F00/1", {optO16}, {cpu286,cpuProtected});
		AddInstruction("reg32", "0F00/1", {optO32}, {cpu386,cpuProtected});
		AddInstruction("reg64", "0F00/1", {}, {cpuAMD64});
		AddInstruction("mem16", "0F00/1", {}, {cpu286,cpuProtected});

		StartMnemonic(opSUB, "SUB");
		AddInstruction("reg/mem8,reg8", "28/r", {}, {cpu8086});
		AddInstruction("reg/mem16,reg16", "29/r", {optO16}, {cpu8086});
		AddInstruction("reg/mem32,reg32", "29/r", {optO32}, {cpu386});
		AddInstruction("reg/mem64,reg64", "29/r", {}, {cpuAMD64});
		AddInstruction("reg8,reg/mem8", "2A/r", {}, {cpu8086});
		AddInstruction("reg16,reg/mem16", "2B/r", {optO16}, {cpu8086});
		AddInstruction("reg32,reg/mem32", "2B/r", {optO32}, {cpu386});
		AddInstruction("reg64,reg/mem64", "2B/r", {}, {cpuAMD64});
		AddInstruction("AL,imm8", "2Cib", {}, {cpu8086});
		AddInstruction("AX,imm16", "2Diw", {optO16}, {cpu8086});
		AddInstruction("EAX,imm32", "2Did", {optO32}, {cpu386});
		AddInstruction("RAX,simm32", "2Did", {}, {cpuAMD64});
		AddInstruction("reg/mem8,imm8", "80/5ib", {}, {cpu8086});
		AddInstruction("reg/mem16,imm16", "81/5iw", {optO16}, {cpu8086});
		AddInstruction("reg/mem32,imm32", "81/5id", {optO32}, {cpu386});
		AddInstruction("reg/mem64,simm32", "81/5id", {}, {cpuAMD64});
		AddInstruction("reg/mem16,simm8", "83/5ib", {optO16}, {cpu8086});
		AddInstruction("reg/mem32,simm8", "83/5ib", {optO32}, {cpu386});
		AddInstruction("reg/mem64,simm8", "83/5ib", {}, {cpuAMD64});

		StartMnemonic(opSUBPD, "SUBPD");
		AddInstruction("xmm1,xmm2/mem128", "660F5C/r", {}, {cpuSSE2});

		StartMnemonic(opSUBPS, "SUBPS");
		AddInstruction("xmm1,xmm2/mem128", "0F5C/r", {}, {cpuSSE});

		StartMnemonic(opSUBSD, "SUBSD");
		AddInstruction("xmm1,xmm2/mem64", "F20F5C/r", {}, {cpuSSE2});

		StartMnemonic(opSUBSS, "SUBSS");
		AddInstruction("xmm1,xmm2/mem32", "F30F5C/r", {}, {cpuSSE});

		StartMnemonic(opSWAPGS, "SWAPGS");
		AddInstruction("", "0F01F8", {}, {cpuAMD64});

		StartMnemonic(opSYSCALL, "SYSCALL");
		AddInstruction("", "0F05", {}, {cpuP6});

		StartMnemonic(opSYSENTER, "SYSENTER");
		AddInstruction("", "0F34", {optNot64}, {cpuP6});

		StartMnemonic(opSYSEXIT, "SYSEXIT");
		AddInstruction("", "0F35", {optNot64}, {cpuP6,cpuPrivileged});

		StartMnemonic(opSYSRET, "SYSRET");
		AddInstruction("", "0F07", {}, {cpuP6,cpuPrivileged});

		StartMnemonic(opTEST, "TEST");
		AddInstruction("reg/mem8,reg8", "84/r", {}, {cpu8086});
		AddInstruction("reg/mem16,reg16", "85/r", {optO16}, {cpu8086});
		AddInstruction("reg/mem32,reg32", "85/r", {optO32}, {cpu386});
		AddInstruction("reg/mem64,reg64", "85/r", {}, {cpuAMD64});
		AddInstruction("AL,imm8", "A8ib", {}, {cpu8086});
		AddInstruction("AX,imm16", "A9iw", {optO16}, {cpu8086});
		AddInstruction("EAX,imm32", "A9id", {optO32}, {cpu386});
		AddInstruction("RAX,simm32", "A9id", {}, {cpuAMD64});
		AddInstruction("reg/mem8,imm8", "F6/0ib", {}, {cpu8086});
		AddInstruction("reg/mem16,imm16", "F7/0iw", {optO16}, {cpu8086});
		AddInstruction("reg/mem32,imm32", "F7/0id", {optO32}, {cpu386});
		AddInstruction("reg/mem64,simm32", "F7/0id", {}, {cpuAMD64});

		StartMnemonic(opUCOMISD, "UCOMISD");
		AddInstruction("xmm1,xmm2/mem64", "660F2E/r", {}, {cpuSSE2});

		StartMnemonic(opUCOMISS, "UCOMISS");
		AddInstruction("xmm1,xmm2/mem32", "0F2E/r", {}, {cpuSSE});

		StartMnemonic(opUD2, "UD2");
		AddInstruction("", "0F0B", {}, {cpu286});

		StartMnemonic(opUNPCKHPD, "UNPCKHPD");
		AddInstruction("xmm1,xmm2/mem128", "660F15/r", {}, {cpuSSE2});

		StartMnemonic(opUNPCKHPS, "UNPCKHPS");
		AddInstruction("xmm1,xmm2/mem128", "0F15/r", {}, {cpuSSE});

		StartMnemonic(opUNPCKLPD, "UNPCKLPD");
		AddInstruction("xmm1,xmm2/mem128", "660F14/r", {}, {cpuSSE2});

		StartMnemonic(opUNPCKLPS, "UNPCKLPS");
		AddInstruction("xmm1,xmm2/mem128", "0F14/r", {}, {cpuSSE});

		StartMnemonic(opVERR, "VERR");
		AddInstruction("reg/mem16", "0F00/4", {}, {cpu286,cpuPrivileged});

		StartMnemonic(opVERW, "VERW");
		AddInstruction("reg/mem16", "0F00/5", {}, {cpu286,cpuPrivileged});

		StartMnemonic(opVMLOAD, "VMLOAD");
		AddInstruction("rAX", "0F01DA", {}, {cpuAMD64});

		StartMnemonic(opVMMCALL, "VMMCALL");
		AddInstruction("", "0F01D9", {}, {cpuAMD64});

		StartMnemonic(opVMRUN, "VMRUN");
		AddInstruction("rAX", "0F01D8", {}, {cpuAMD64});

		StartMnemonic(opVMSAVE, "VMSAVE");
		AddInstruction("rAX", "0F01DB", {}, {cpuAMD64});

		StartMnemonic(opWBINVD, "WBINVD");
		AddInstruction("", "0F09", {}, {cpu486,cpuPrivileged});

		StartMnemonic(opWRMSR, "WRMSR");
		AddInstruction("", "0F30", {}, {cpuPentium,cpuPrivileged});

		StartMnemonic(opXADD, "XADD");
		AddInstruction("reg/mem8,reg8", "0FC0/r", {}, {cpu486});
		AddInstruction("reg/mem16,reg16", "0FC1/r", {optO16}, {cpu486});
		AddInstruction("reg/mem32,reg32", "0FC1/r", {optO32}, {cpu486});
		AddInstruction("reg/mem64,reg64", "0FC1/r", {}, {cpuAMD64});

		StartMnemonic(opXCHG, "XCHG");
		AddInstruction("AX,reg16", "90rw", {optO16}, {cpu8086});
		AddInstruction("reg16,AX", "90rw", {optO16}, {cpu8086});
		AddInstruction("EAX,reg32", "90rd", {optO32}, {cpu386});
		AddInstruction("reg32,EAX", "90rd", {optO32}, {cpu386});
		AddInstruction("RAX,reg64", "90rq", {}, {cpuAMD64});
		AddInstruction("reg64,RAX", "90rq", {}, {cpuAMD64});
		AddInstruction("reg/mem8,reg8", "86/r", {}, {cpu8086});
		AddInstruction("reg8,reg/mem8", "86/r", {}, {cpu8086});
		AddInstruction("reg/mem16,reg16", "87/r", {optO16}, {cpu8086});
		AddInstruction("reg16,reg/mem16", "87/r", {optO16}, {cpu8086});
		AddInstruction("reg/mem32,reg32", "87/r", {optO32}, {cpu386});
		AddInstruction("reg32,reg/mem32", "87/r", {optO32}, {cpu386});
		AddInstruction("reg/mem64,reg64", "87/r", {}, {cpuAMD64});
		AddInstruction("reg64,reg/mem64", "87/r", {}, {cpuAMD64});

		StartMnemonic(opXLAT, "XLAT");
		AddInstruction("mem8", "D7", {}, {cpu8086});

		StartMnemonic(opXLATB, "XLATB");
		AddInstruction("", "D7", {}, {cpu8086});

		StartMnemonic(opXOR, "XOR");
		AddInstruction("reg/mem8,reg8", "30/r", {}, {cpu8086});
		AddInstruction("reg/mem16,reg16", "31/r", {optO16}, {cpu8086});
		AddInstruction("reg/mem32,reg32", "31/r", {optO32}, {cpu386});
		AddInstruction("reg/mem64,reg64", "31/r", {}, {cpuAMD64});
		AddInstruction("reg8,reg/mem8", "32/r", {}, {cpu8086});
		AddInstruction("reg16,reg/mem16", "33/r", {optO16}, {cpu8086});
		AddInstruction("reg32,reg/mem32", "33/r", {optO32}, {cpu386});
		AddInstruction("reg64,reg/mem64", "33/r", {}, {cpuAMD64});
		AddInstruction("AL,imm8", "34ib", {}, {cpu8086});
		AddInstruction("AX,imm16", "35iw", {optO16}, {cpu8086});
		AddInstruction("EAX,imm32", "35id", {optO32}, {cpu386});
		AddInstruction("RAX,simm32", "35id", {}, {cpuAMD64});
		AddInstruction("reg/mem8,imm8", "80/6ib", {}, {cpu8086});
		AddInstruction("reg/mem16,imm16", "81/6iw", {optO16}, {cpu8086});
		AddInstruction("reg/mem32,imm32", "81/6id", {optO32}, {cpu386});
		AddInstruction("reg/mem64,simm32", "81/6id", {}, {cpuAMD64});
		AddInstruction("reg/mem16,simm8", "83/6ib", {optO16}, {cpu8086});
		AddInstruction("reg/mem32,simm8", "83/6ib", {optO32}, {cpu386});
		AddInstruction("reg/mem64,simm8", "83/6ib", {}, {cpuAMD64});

		StartMnemonic(opXORPD, "XORPD");
		AddInstruction("xmm1,xmm2/mem128", "660F57/r", {}, {cpuSSE2});

		StartMnemonic(opXORPS, "XORPS");
		AddInstruction("xmm1,xmm2/mem128", "0F57/r", {}, {cpuSSE});

	END InitInstructions;

	PROCEDURE IsImmediate8*(operandType: OperandType): BOOLEAN;
	BEGIN RETURN (operandType = imm8) OR (operandType = simm8) OR (operandType = uimm8)
	END IsImmediate8;

	PROCEDURE IsImmediate16*(operandType: OperandType): BOOLEAN;
	BEGIN RETURN (operandType = imm16) OR (operandType = simm16) OR (operandType = uimm16)
	END IsImmediate16;

	PROCEDURE IsImmediate32*(operandType: OperandType): BOOLEAN;
	BEGIN RETURN (operandType = imm32) OR (operandType = simm32) OR (operandType = uimm32)
	END IsImmediate32;

	PROCEDURE IsImmediate64*(operandType: OperandType): BOOLEAN;
	BEGIN RETURN (operandType = imm64)
	END IsImmediate64;

	PROCEDURE IsRegister8*(index: LONGINT): BOOLEAN;
	BEGIN
		RETURN registers[index].type = reg8;
	END IsRegister8;

	PROCEDURE Register8*(index: SHORTINT): LONGINT;
	BEGIN
		RETURN registersByClass[reg8,index]
	END Register8;

	PROCEDURE IsRegister8Low*(index: LONGINT): BOOLEAN;
	BEGIN
		CASE index OF
			regAL, regBL, regCL,regDL,regR8B,regR9B,regR10B,regR11B,regR12B,regR13B,regR14B,regR15B: RETURN TRUE
		ELSE
			RETURN FALSE
		END
	END IsRegister8Low;

	PROCEDURE IsRegister8High*(index: LONGINT): BOOLEAN;
	BEGIN
		CASE index OF
			regAH, regBH, regCH,regDH: RETURN TRUE
		ELSE
			RETURN FALSE
		END
	END IsRegister8High;

	PROCEDURE Register16*(index: SHORTINT): LONGINT;
	BEGIN
		RETURN registersByClass[reg16,index]
	END Register16;

	PROCEDURE IsRegister16*(index: LONGINT): BOOLEAN;
	BEGIN
		RETURN registers[index].type = reg16;
	END IsRegister16;

	PROCEDURE Register32*(index: SHORTINT): LONGINT;
	BEGIN
		RETURN registersByClass[reg32,index]
	END Register32;

	PROCEDURE IsRegister32*(index: LONGINT): BOOLEAN;
	BEGIN
		RETURN registers[index].type = reg32;
	END IsRegister32;

	PROCEDURE Register64*(index: SHORTINT): LONGINT;
	BEGIN
		RETURN registersByClass[reg64,index]
	END Register64;

	PROCEDURE IsRegister64*(index: LONGINT): BOOLEAN;
	BEGIN
		RETURN registers[index].type = reg64;
	END IsRegister64;

	PROCEDURE CounterRegister*(index: SHORTINT): LONGINT;
	BEGIN
		RETURN registersByClass[CRn,index]
	END CounterRegister;

	PROCEDURE IsCounterRegister*(index: LONGINT): BOOLEAN;
	BEGIN
		RETURN registers[index].type = CRn;
	END IsCounterRegister;

	PROCEDURE DebugRegister*(index: SHORTINT): LONGINT;
	BEGIN
		RETURN registersByClass[DRn,index]
	END DebugRegister;

	PROCEDURE IsDebugRegister*(index: LONGINT): BOOLEAN;
	BEGIN
		RETURN registers[index].type = DRn;
	END IsDebugRegister;

	PROCEDURE SegmentRegister*(index: SHORTINT): LONGINT;
	BEGIN
		RETURN registersByClass[segReg,index]
	END SegmentRegister;

	PROCEDURE IsSegmentRegister*(index: LONGINT): BOOLEAN;
	BEGIN
		RETURN registers[index].type = segReg;
	END IsSegmentRegister;

	PROCEDURE MMXRegister*(index: SHORTINT): LONGINT;
	BEGIN
		RETURN registersByClass[mmx,index]
	END MMXRegister;

	PROCEDURE IsMMXRegister*(index: LONGINT): BOOLEAN;
	BEGIN
		RETURN registers[index].type = mmx;
	END IsMMXRegister;

	PROCEDURE SSERegister*(index: SHORTINT): LONGINT;
	BEGIN
		RETURN registersByClass[xmm,index]
	END SSERegister;

	PROCEDURE IsSSERegister*(index: LONGINT): BOOLEAN;
	BEGIN
		RETURN registers[index].type = xmm;
	END IsSSERegister;

	PROCEDURE FPRegister*(index: SHORTINT): LONGINT;
	BEGIN
		RETURN registersByClass[sti,index]
	END FPRegister;

	PROCEDURE IsFPRegister*(index: LONGINT): BOOLEAN;
	BEGIN
		RETURN registers[index].type = sti;
	END IsFPRegister;

	(** setup register tables **)
	PROCEDURE InitRegisters;
		(* insert an new register *)
		PROCEDURE AddRegister (number: LONGINT; CONST name: ARRAY OF CHAR; type: OperandType; sizeInBytes: SHORTINT; index: SHORTINT);
		BEGIN
			COPY (name, registers[number].name);
			registers[number].type := type;
			registers[number].index := index;
			registers[number].sizeInBytes := sizeInBytes;
			registersByClass[type,index] := number;
		END AddRegister;

		PROCEDURE InitRegisters;
		VAR i,j: LONGINT;
		BEGIN
			FOR i := 0 TO LEN(registersByClass)-1 DO
				FOR j := 0 TO LEN(registersByClass[i])-1 DO
					registersByClass[i,j] := none;
				END;
			END;
		END InitRegisters;

	BEGIN
		InitRegisters;

		AddRegister (regAL,"AL", reg8, bits8, 0);
		AddRegister (regCL,"CL", reg8, bits8,1);
		AddRegister (regDL,"DL", reg8, bits8,2);
		AddRegister (regBL,"BL", reg8, bits8,3);
		AddRegister (regAH,"AH", reg8, bits8,4);
		AddRegister (regCH,"CH", reg8, bits8,5);
		AddRegister (regDH,"DH", reg8, bits8,6);
		AddRegister (regBH,"BH", reg8, bits8,7);
		AddRegister (regSPL,"SPL", reg8, bits8, 4);
		AddRegister (regBPL,"BPL", reg8, bits8,5);
		AddRegister (regSIL,"SIL", reg8, bits8,6);
		AddRegister (regDIL,"DIL", reg8, bits8,7);
		AddRegister (regR8B,"R8B", reg8, bits8,8);
		AddRegister (regR9B,"R9B", reg8, bits8,9);
		AddRegister (regR10B,"R10B", reg8, bits8,10);
		AddRegister (regR11B,"R11B", reg8, bits8,11);
		AddRegister (regR12B,"R12B", reg8, bits8,12);
		AddRegister (regR13B,"R13B", reg8, bits8,13);
		AddRegister (regR14B,"R14B", reg8, bits8,14);
		AddRegister (regR15B,"R15B", reg8, bits8,15);

		AddRegister (regAX,"AX", reg16, bits16, 0);
		AddRegister (regCX,"CX", reg16, bits16, 1);
		AddRegister (regDX,"DX", reg16, bits16, 2);
		AddRegister (regBX,"BX", reg16, bits16, 3);
		AddRegister (regSP,"SP", reg16, bits16, 4);
		AddRegister (regBP,"BP", reg16, bits16, 5);
		AddRegister (regSI,"SI", reg16, bits16, 6);
		AddRegister (regDI,"DI", reg16, bits16, 7);
		AddRegister (regR8W,"R8W", reg16, bits16, 8);
		AddRegister (regR9W,"R9W", reg16, bits16, 9);
		AddRegister (regR10W,"R10W", reg16, bits16, 10);
		AddRegister (regR11W,"R11W", reg16, bits16, 11);
		AddRegister (regR12W,"R12W", reg16, bits16, 12);
		AddRegister (regR13W,"R13W", reg16, bits16, 13);
		AddRegister (regR14W,"R14W", reg16, bits16, 14);
		AddRegister (regR15W,"R15W", reg16, bits16, 15);

		AddRegister (regEAX,"EAX", reg32, bits32, 0);
		AddRegister (regECX,"ECX", reg32, bits32, 1);
		AddRegister (regEDX,"EDX", reg32, bits32, 2);
		AddRegister (regEBX,"EBX", reg32, bits32, 3);
		AddRegister (regESP,"ESP", reg32, bits32, 4);
		AddRegister (regEBP,"EBP", reg32, bits32, 5);
		AddRegister (regESI,"ESI", reg32, bits32, 6);
		AddRegister (regEDI,"EDI", reg32, bits32, 7);
		AddRegister (regR8D,"R8D", reg32, bits32, 8);
		AddRegister (regR9D,"R9D", reg32, bits32, 9);
		AddRegister (regR10D,"R10D", reg32, bits32, 10);
		AddRegister (regR11D,"R11D", reg32, bits32, 11);
		AddRegister (regR12D,"R12D", reg32, bits32, 12);
		AddRegister (regR13D,"R13D", reg32, bits32, 13);
		AddRegister (regR14D,"R14D", reg32, bits32, 14);
		AddRegister (regR15D,"R15D", reg32, bits32, 15);

		AddRegister (regRAX,"RAX", reg64, bits64, 0);
		AddRegister (regRCX,"RCX", reg64, bits64, 1);
		AddRegister (regRDX,"RDX", reg64, bits64, 2);
		AddRegister (regRBX,"RBX", reg64, bits64, 3);
		AddRegister (regRSP,"RSP", reg64, bits64, 4);
		AddRegister (regRBP,"RBP", reg64, bits64, 5);
		AddRegister (regRSI, "RSI", reg64,bits64,  6);
		AddRegister (regRDI,"RDI", reg64, bits64, 7);
		AddRegister (regR8,"R8", reg64, bits64, 8);
		AddRegister (regR9,"R9", reg64, bits64, 9);
		AddRegister (regR10,"R10", reg64, bits64, 10);
		AddRegister (regR11,"R11", reg64, bits64, 11);
		AddRegister (regR12,"R12", reg64, bits64, 12);
		AddRegister (regR13,"R13", reg64, bits64, 13);
		AddRegister (regR14,"R14", reg64, bits64, 14);
		AddRegister (regR15,"R15", reg64, bits64, 15);
		AddRegister (regRIP,"RIP", reg64, bits64, 16);

		AddRegister (regES,"ES", segReg, bitsDefault, 0);
		AddRegister (regCS,"CS", segReg,  bitsDefault, 1);
		AddRegister (regSS,"SS", segReg,  bitsDefault, 2);
		AddRegister (regDS,"DS", segReg,  bitsDefault, 3);
		AddRegister (regFS,"FS", segReg,  bitsDefault, 4);
		AddRegister (regGS,"GS", segReg,  bitsDefault, 5);

		AddRegister (regCR0,"CR0", CRn, bitsDefault, 0);
		AddRegister (regCR1,"CR1", CRn, bitsDefault, 1);
		AddRegister (regCR2,"CR2", CRn, bitsDefault, 2);
		AddRegister (regCR3,"CR3", CRn, bitsDefault, 3);
		AddRegister (regCR4,"CR4", CRn, bitsDefault, 4);
		AddRegister (regCR5,"CR5", CRn, bitsDefault, 5);
		AddRegister (regCR6,"CR6", CRn, bitsDefault, 6);
		AddRegister (regCR7,"CR7", CRn, bitsDefault, 7);
		AddRegister (regCR8,"CR8", CRn, bitsDefault, 8);
		AddRegister (regCR9,"CR9", CRn, bitsDefault, 9);
		AddRegister (regCR10,"CR10", CRn, bitsDefault, 10);
		AddRegister (regCR11,"CR11", CRn, bitsDefault, 11);
		AddRegister (regCR12,"CR12", CRn, bitsDefault, 12);
		AddRegister (regCR13,"CR13", CRn, bitsDefault, 13);
		AddRegister (regCR14,"CR14", CRn, bitsDefault, 14);
		AddRegister (regCR15,"CR15", CRn, bitsDefault, 15);

		AddRegister (regDR0,"DR0", DRn, bitsDefault, 0);
		AddRegister (regDR1,"DR1", DRn, bitsDefault, 1);
		AddRegister (regDR2,"DR2", DRn, bitsDefault, 2);
		AddRegister (regDR3,"DR3", DRn, bitsDefault, 3);
		AddRegister (regDR4,"DR4", DRn, bitsDefault, 4);
		AddRegister (regDR5,"DR5", DRn, bitsDefault, 5);
		AddRegister (regDR6,"DR6", DRn, bitsDefault, 6);
		AddRegister (regDR7,"DR7", DRn, bitsDefault, 7);
		AddRegister (regDR8,"DR8", DRn, bitsDefault, 8);
		AddRegister (regDR9,"DR9", DRn, bitsDefault, 9);
		AddRegister (regDR10,"DR10", DRn, bitsDefault, 10);
		AddRegister (regDR11,"DR11", DRn, bitsDefault, 11);
		AddRegister (regDR12,"DR12", DRn, bitsDefault, 12);
		AddRegister (regDR13,"DR13", DRn, bitsDefault, 13);
		AddRegister (regDR14,"DR14", DRn, bitsDefault, 14);
		AddRegister (regDR15,"DR15", DRn, bitsDefault, 15);

		AddRegister (regST0,"ST0", sti, bitsDefault, 0);
		AddRegister (regST1,"ST1", sti, bitsDefault, 1);
		AddRegister (regST2,"ST2", sti, bitsDefault, 2);
		AddRegister (regST3,"ST3", sti, bitsDefault, 3);
		AddRegister (regST4,"ST4", sti, bitsDefault, 4);
		AddRegister (regST5,"ST5", sti, bitsDefault, 5);
		AddRegister (regST6,"ST6", sti, bitsDefault, 6);
		AddRegister (regST7,"ST7", sti, bitsDefault, 7);

		AddRegister (regXMM0,"XMM0", xmm, bits64, 0);
		AddRegister (regXMM1,"XMM1", xmm, bits64, 1);
		AddRegister (regXMM2,"XMM2", xmm, bits64, 2);
		AddRegister (regXMM3,"XMM3", xmm, bits64, 3);
		AddRegister (regXMM4,"XMM4", xmm, bits64, 4);
		AddRegister (regXMM5,"XMM5", xmm, bits64, 5);
		AddRegister (regXMM6,"XMM6", xmm, bits64, 6);
		AddRegister (regXMM7,"XMM7", xmm, bits64, 7);
		AddRegister (regXMM8,"XMM8", xmm, bits64, 8);
		AddRegister (regXMM9,"XMM9", xmm, bits64, 9);
		AddRegister (regXMM10,"XMM10", xmm, bits64, 10);
		AddRegister (regXMM11,"XMM11", xmm, bits64, 11);
		AddRegister (regXMM12,"XMM12", xmm, bits64, 12);
		AddRegister (regXMM13,"XMM13", xmm, bits64, 13);
		AddRegister (regXMM14,"XMM14", xmm, bits64, 14);
		AddRegister (regXMM15,"XMM15", xmm, bits64, 15);

		AddRegister (regMMX0,"MMX0", mmx, bits128, 0);
		AddRegister (regMMX1,"MMX1", mmx, bits128, 1);
		AddRegister (regMMX2,"MMX2", mmx, bits128, 2);
		AddRegister (regMMX3,"MMX3", mmx, bits128, 3);
		AddRegister (regMMX4,"MMX4", mmx, bits128, 4);
		AddRegister (regMMX5,"MMX5", mmx, bits128, 5);
		AddRegister (regMMX6,"MMX6", mmx, bits128, 6);
		AddRegister (regMMX7,"MMX7", mmx, bits128, 7);

	END InitRegisters;

	(** setup CPU tables **)
	PROCEDURE InitCPUs;
		(* insert a new cpu type *)
		PROCEDURE AddCpu (CONST name: ARRAY OF CHAR; cpuoptions: SET);
		BEGIN
			COPY (name, cpus[cpuCount].name);
			cpus[cpuCount].cpuOptions := cpuoptions;
			INC (cpuCount);
		END AddCpu;
	BEGIN
		cpuCount := 0;
		AddCpu ("8086", {cpu8086});
		AddCpu ("186", {cpu8086, cpu186});
		AddCpu ("286", {cpu8086 .. cpu286});
		AddCpu ("386", {cpu8086 .. cpu386});
		AddCpu ("I386", {cpu8086 .. cpu386});
		AddCpu ("486", {cpu8086 .. cpu486});
		AddCpu ("I486", {cpu8086 .. cpu486});
		AddCpu ("586", {cpu8086 .. cpuPentium});
		AddCpu ("PENTIUM", {cpu8086 .. cpuPentium});
		AddCpu ("686", {cpu8086 .. cpuP6});
		AddCpu ("PPRO", {cpu8086 .. cpuP6});
		AddCpu ("PENTIUMPRO", {cpu8086 .. cpuP6});
		AddCpu ("P2", {cpu8086 .. cpuP6});
		AddCpu ("P3", {cpu8086 .. cpuKatmai});
		AddCpu ("KATMAI", {cpu8086 .. cpuKatmai});
		AddCpu ("P4", {cpu8086 .. cpuWillamette});
		AddCpu ("WILLAMETTE", {cpu8086 .. cpuWillamette});
		AddCpu ("PRESCOTT", {cpu8086 .. cpuPrescott});
		AddCpu ("AMD64", {cpu8086 .. cpuAMD64, cpuSSE, cpuSSE2, cpuSSE3, cpu3DNow, cpuMMX});

		AddCpu ("PRIVILEGED", {cpuPrivileged});
		AddCpu ("PROTECTED", {cpuProtected});
		AddCpu ("SSE", {cpuSSE});
		AddCpu ("SSE2", {cpuSSE2,cpuSSE});
		AddCpu ("SSE3", {cpuSSE3,cpuSSE2,cpuSSE});
		AddCpu ("3DNOW", {cpu3DNow});
		AddCpu ("MMX", {cpuMMX});
		AddCpu ("FPU", {cpuFPU});
	END InitCPUs;

	PROCEDURE Trace*;
	VAR instr: LONGINT; i: LONGINT;
	BEGIN
		instr := 0;
		WHILE instr < numberInstructions DO
			KernelLog.Int(instr,5);
			KernelLog.String(" ");
			FOR i := 0 TO maxCodeLength-1 DO
				KernelLog.Hex(ORD(instructions[instr].code[i]),-2); KernelLog.String(" ");
			END;
			FOR i := 0 TO maxNumberOperands-1 DO
				KernelLog.Int(instructions[instr].operands[i],1); KernelLog.String(" ");
			END;
			KernelLog.Ln;
			INC(instr);
		END;
	END Trace;


BEGIN
	InitInstructions;
	InitRegisters;
	InitCPUs;
END FoxAMD64InstructionSet.

FoxAMD6InstructionSet.Trace

SystemTools.Free FoxAMD64InstructionSet ~
4
	(** Instruction Format, cf. [AMD:3], chapter 1
		[LegacyPrefix] ; Operand-Size Override / modify opcode of media instructions
		[LegacyPrefix] ; Address-Size Override
		[LegacyPrefix] ; Segment Override
		[LegacyPrefix] ; LOCK Prefix
		[LegacyPrefix] ; Repeat Prefixes
		[REXPrefix]; 7-4: 0100 3:W 2:R 1:X 0:B register modification (W) and extension bits (R-register X-index B-base)
		Opcode
		[Opcode]
		[Opcode]
		[ModRM]; 7:6:mod 5:3:reg  2:0:r/m (op code modifier, register, memory)
		[SIB]; 7:6 scale 5:3:index 2:0:base (scale, index, base)
		[Displacement]
		[Displacement]
		[Displacement]
		[Displacement]
		is a 64bit displacement possible ?
		[Immediate]
		[Immediate]
		[Immediate]
		[Immediate]
		[Immediate]; only for MOV instruction
		[Immediate]; only for MOV instruction
		[Immediate]; only for MOV instruction
		[Immediate]; only for MOV instruction

			Instruction = RECORD
		cpuoptions-: CPUOptions; (* necessary CPU options for the instruction to be available *)

		prefixFlags-: SET;
		numerLegacyPrefixes-: SHORTINT;
		legacyPrefixes-: ARRAY MaxLegacyPrefixes OF CHAR; (* legacy prefixes *)

		usedREXPrefix-:BOOLEAN;
		REXPrefix-:CHAR; (* REX prefix *)

		opcodeFlags-: SET;
		numberOpcodes-: SHORTINT; (* 1..MaxOpCodes *)
		opcode-: ARRAY MaxOpCodes OF CHAR;
		usedModRM-: BOOLEAN;
		ModRM: CHAR; (* mode-register-memory *)
		usedSIB_: BOOLEAN;
		SIB-: CHAR; (* scale-index-base *)

		numberOperands-: SHORTINT; (* 0.. MaxOperands *)
		operand-: ARRAY MaxOperands OF Operand;
	END;

	**)