FoxAMDBackend.Mod 140 KB

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  1. MODULE FoxAMDBackend; (** AUTHOR ""; PURPOSE ""; *)
  2. IMPORT
  3. Basic := FoxBasic, Scanner := FoxScanner, SyntaxTree := FoxSyntaxTree, Global := FoxGlobal, Backend := FoxBackend, Sections := FoxSections,
  4. IntermediateCode := FoxIntermediateCode, IntermediateBackend := FoxIntermediateBackend, BinaryCode := FoxBinaryCode,
  5. InstructionSet := FoxAMD64InstructionSet, Assembler := FoxAMD64Assembler, SemanticChecker := FoxSemanticChecker, Formats := FoxFormats,
  6. Diagnostics, Streams, Options, Strings, ObjectFileFormat := FoxBinaryObjectFile, Compiler,
  7. Machine, D := Debugging, CodeGenerators := FoxCodeGenerators, ObjectFile;
  8. CONST
  9. (* constants for the register allocator *)
  10. none=-1;
  11. RAX=InstructionSet.regRAX; RCX=InstructionSet.regRCX; RDX=InstructionSet.regRDX; RBX=InstructionSet.regRBX;
  12. RSP=InstructionSet.regRSP; RBP=InstructionSet.regRBP; RSI=InstructionSet.regRSI; RDI=InstructionSet.regRDI;
  13. R8=InstructionSet.regR8; R9=InstructionSet.regR9; R10=InstructionSet.regR10; R11=InstructionSet.regR11;
  14. R12=InstructionSet.regR12; R13=InstructionSet.regR13; R14=InstructionSet.regR14; R15=InstructionSet.regR15;
  15. EAX=InstructionSet.regEAX; ECX=InstructionSet.regECX; EDX=InstructionSet.regEDX; EBX=InstructionSet.regEBX;
  16. ESP=InstructionSet.regESP; EBP=InstructionSet.regEBP; ESI=InstructionSet.regESI; EDI=InstructionSet.regEDI;
  17. R8D=InstructionSet.regR8D; R9D=InstructionSet.regR9D; R10D=InstructionSet.regR10D; R11D=InstructionSet.regR11D;
  18. R12D=InstructionSet.regR12D; R13D=InstructionSet.regR13D; R14D=InstructionSet.regR14D; R15D=InstructionSet.regR15D;
  19. AX=InstructionSet.regAX; CX=InstructionSet.regCX; DX=InstructionSet.regDX; BX=InstructionSet.regBX;
  20. SI=InstructionSet.regSI; DI=InstructionSet.regDI; BP=InstructionSet.regBP; SP=InstructionSet.regSP;
  21. R8W=InstructionSet.regR8W; R9W=InstructionSet.regR9W; R10W=InstructionSet.regR10W; R11W=InstructionSet.regR11W;
  22. R12W=InstructionSet.regR12W; R13W=InstructionSet.regR13W; R14W=InstructionSet.regR14W; R15W=InstructionSet.regR15W;
  23. AL=InstructionSet.regAL; CL=InstructionSet.regCL; DL=InstructionSet.regDL; BL=InstructionSet.regBL; SIL=InstructionSet.regSIL;
  24. DIL=InstructionSet.regDIL; BPL=InstructionSet.regBPL; SPL=InstructionSet.regSPL;
  25. R8B=InstructionSet.regR8B; R9B=InstructionSet.regR9B; R10B=InstructionSet.regR10B; R11B=InstructionSet.regR11B;
  26. R12B=InstructionSet.regR12B; R13B=InstructionSet.regR13B; R14B=InstructionSet.regR14B; R15B=InstructionSet.regR15B;
  27. AH=InstructionSet.regAH; CH=InstructionSet.regCH; DH=InstructionSet.regDH; BH=InstructionSet.regBH;
  28. ST0=InstructionSet.regST0;
  29. XMM0 = InstructionSet.regXMM0;
  30. XMM7 = InstructionSet.regXMM7;
  31. YMM0 = InstructionSet.regYMM0;
  32. YMM7 = InstructionSet.regYMM7;
  33. Low=0; High=1;
  34. FrameSpillStack=TRUE;
  35. VAR registerOperands: ARRAY InstructionSet.numberRegisters OF Assembler.Operand;
  36. usePool: BOOLEAN;
  37. opEAX, opECX, opEDX, opEBX, opESP, opEBP,
  38. opESI, opEDI, opAX, opCX, opDX, opBX, opSI, opDI, opAL, opCL, opDL, opBL, opAH, opCH, opDH, opBH,opST0
  39. , opRSP, opRBP: Assembler.Operand;
  40. unusable,split,blocked,free: CodeGenerators.Ticket;
  41. traceStackSize: LONGINT;
  42. TYPE
  43. Ticket=CodeGenerators.Ticket;
  44. PhysicalRegisters*=OBJECT (CodeGenerators.PhysicalRegisters)
  45. VAR
  46. toVirtual: ARRAY InstructionSet.numberRegisters OF Ticket; (* registers real register -> none / reserved / split / blocked / virtual register (>0) *)
  47. reserved: ARRAY InstructionSet.numberRegisters OF BOOLEAN;
  48. hint: LONGINT;
  49. useFPU: BOOLEAN;
  50. PROCEDURE &InitPhysicalRegisters(fpu,cooperative: BOOLEAN);
  51. VAR i: LONGINT;
  52. BEGIN
  53. FOR i := 0 TO LEN(toVirtual)-1 DO
  54. toVirtual[i] := NIL;
  55. reserved[i] := FALSE;
  56. END;
  57. (* reserve stack and base pointer registers *)
  58. toVirtual[BPL] := unusable;
  59. toVirtual[SPL] := unusable;
  60. toVirtual[BP] := unusable;
  61. toVirtual[SP] := unusable;
  62. toVirtual[EBP] := unusable;
  63. toVirtual[ESP] := unusable;
  64. toVirtual[RBP] := unusable;
  65. toVirtual[RSP] := unusable;
  66. hint := none;
  67. useFPU := fpu
  68. END InitPhysicalRegisters;
  69. PROCEDURE AllocationHint(index: LONGINT);
  70. BEGIN hint := index
  71. END AllocationHint;
  72. PROCEDURE NumberRegisters(): LONGINT;
  73. BEGIN
  74. RETURN LEN(toVirtual)
  75. END NumberRegisters;
  76. END PhysicalRegisters;
  77. PhysicalRegisters32=OBJECT (PhysicalRegisters) (* 32 bit implementation *)
  78. PROCEDURE & InitPhysicalRegisters32(fpu,cooperative: BOOLEAN);
  79. VAR i: LONGINT;
  80. BEGIN
  81. InitPhysicalRegisters(fpu,cooperative);
  82. (* disable registers that are only usable in 64 bit mode *)
  83. FOR i := 0 TO 31 DO
  84. toVirtual[i+RAX] := unusable;
  85. END;
  86. FOR i := 8 TO 15 DO
  87. toVirtual[i+AL] := unusable;
  88. toVirtual[i+AH] := unusable;
  89. toVirtual[i+EAX] := unusable;
  90. toVirtual[i+AX] := unusable;
  91. END;
  92. FOR i := 4 TO 7 DO
  93. toVirtual[i+AL] := unusable;
  94. toVirtual[i+AH] := unusable;
  95. END;
  96. FOR i := 0 TO LEN(reserved)-1 DO reserved[i] := FALSE END;
  97. END InitPhysicalRegisters32;
  98. PROCEDURE Allocate(index: LONGINT; virtualRegister: Ticket);
  99. BEGIN
  100. (*
  101. D.String("allocate register x : index="); D.Int(index,1); D.Ln;
  102. *)
  103. Assert(toVirtual[index] = free,"register already allocated");
  104. toVirtual[index] := virtualRegister;
  105. IF index DIV 32 = 2 THEN (* 32 bit *)
  106. Assert(toVirtual[index MOD 32 + AX] = free,"free register split");
  107. toVirtual[index MOD 32 + AX] := blocked;
  108. IF index MOD 32 < 4 THEN
  109. Assert(toVirtual[index MOD 32 + AL] = free,"register already allocated");
  110. Assert(toVirtual[index MOD 32 + AH] = free,"register already allocated");
  111. toVirtual[index MOD 32 + AL] := blocked;
  112. toVirtual[index MOD 32 + AH] := blocked;
  113. END;
  114. ELSIF index DIV 32 = 1 THEN (* 16 bit *)
  115. Assert(toVirtual[index MOD 8 + EAX] = free,"free register split");
  116. toVirtual[index MOD 32 + EAX] := split;
  117. IF index MOD 32 < 4 THEN
  118. Assert(toVirtual[index MOD 32 + AL] = free,"register already allocated");
  119. Assert(toVirtual[index MOD 32 + AH] = free,"register already allocated");
  120. toVirtual[index MOD 32 + AL] := blocked;
  121. toVirtual[index MOD 32 + AH] := blocked;
  122. END;
  123. ELSIF index DIV 32 = 0 THEN (* 8 bit *)
  124. Assert((toVirtual[index MOD 4 + EAX] = free) OR (toVirtual[index MOD 4 + EAX] = split),"free register blocked");
  125. Assert((toVirtual[index MOD 4 + AX] = free) OR (toVirtual[index MOD 4 + AX] = split),"free register blocked");
  126. toVirtual[index MOD 4 + EAX] := split;
  127. toVirtual[index MOD 4 + AX] := split;
  128. ELSIF (index >= XMM0) & (index <= XMM7) THEN (* vector register *)
  129. ELSIF (index >= YMM0) & (index <= YMM7) THEN (* vector register *)
  130. ELSE Assert( (index >=InstructionSet.regST0) & (index <= InstructionSet.regST7 ),"not a float register"); (* floats *)
  131. END;
  132. END Allocate;
  133. PROCEDURE SetReserved(index: LONGINT; res: BOOLEAN);
  134. BEGIN
  135. IF index DIV 32 <=2 THEN
  136. index := index MOD 16;
  137. reserved[index+AH] := res;
  138. reserved[index+AL] := res;
  139. reserved[index+AX] := res;
  140. reserved[index+EAX] := res;
  141. ELSE
  142. reserved[index] := res;
  143. END;
  144. END SetReserved;
  145. PROCEDURE Reserved(index: LONGINT): BOOLEAN;
  146. BEGIN
  147. RETURN (index>0) & reserved[index]
  148. END Reserved;
  149. PROCEDURE Free(index: LONGINT);
  150. VAR x: Ticket;
  151. BEGIN
  152. (*
  153. D.String("free register x : index="); D.Int(index,1); D.Ln;
  154. *)
  155. x := toVirtual[index];
  156. Assert((toVirtual[index] # NIL),"register not reserved");
  157. toVirtual[index] := free;
  158. IF index DIV 32 =2 THEN (* 32 bit *)
  159. Assert(toVirtual[index MOD 32 + AX] = blocked,"reserved register did not block");
  160. toVirtual[index MOD 32 + AX] := free;
  161. IF index MOD 32 < 4 THEN
  162. Assert(toVirtual[index MOD 32 + AL] = blocked,"reserved register did not block");
  163. Assert(toVirtual[index MOD 32 + AH] = blocked,"reserved register did not block");
  164. toVirtual[index MOD 32 + AL] := free;
  165. toVirtual[index MOD 32 + AH] := free;
  166. END;
  167. ELSIF index DIV 32 = 1 THEN (* 16 bit *)
  168. Assert(toVirtual[index MOD 32 + EAX] = split,"reserved register did not split");
  169. toVirtual[index MOD 32 + EAX] := free;
  170. IF index MOD 32 < 4 THEN
  171. Assert(toVirtual[index MOD 32 + AL] = blocked,"reserved register did not block");
  172. Assert(toVirtual[index MOD 32 + AH] = blocked,"reserved register did not block");
  173. toVirtual[index MOD 32 + AL] := free;
  174. toVirtual[index MOD 32 + AH] := free;
  175. END;
  176. ELSIF index DIV 32 = 0 THEN (* 8 bit *)
  177. IF (toVirtual[index MOD 4 + AL] = free) & (toVirtual[index MOD 4 + AH] = free) THEN
  178. Assert(toVirtual[index MOD 4 + EAX] = split,"reserved register did not split");
  179. Assert(toVirtual[index MOD 4 + AX] = split,"reserved register did not split");
  180. toVirtual[index MOD 4 + EAX] := free;
  181. toVirtual[index MOD 4 + AX] := free;
  182. END;
  183. ELSIF (index >= XMM0) & (index <= XMM7) THEN (* vector register *)
  184. ELSIF (index >= YMM0) & (index <= YMM7) THEN (* vector register *)
  185. ELSE Assert( (index >=InstructionSet.regST0) & (index <= InstructionSet.regST7 ),"not a float register"); (* floats *)
  186. END;
  187. END Free;
  188. PROCEDURE NextFree(CONST type: IntermediateCode.Type):LONGINT;
  189. VAR i,sizeInBits,length, form: LONGINT;
  190. PROCEDURE GetGPHint(offset: LONGINT): LONGINT;
  191. VAR res: LONGINT;
  192. BEGIN
  193. IF (hint # none) & (hint >= AL) & (hint <= EDI) & (toVirtual[hint MOD 32 + offset]=free) & ~Reserved(hint) THEN res := hint MOD 32 + offset ELSE res := none END;
  194. hint := none;
  195. RETURN res
  196. END GetGPHint;
  197. PROCEDURE GetHint(from,to: LONGINT): LONGINT;
  198. VAR res: LONGINT;
  199. BEGIN
  200. IF (hint # none) & (hint >= from) & (hint <= to) & (toVirtual[hint]=free) & ~Reserved(hint) THEN res := hint ELSE res := none END;
  201. hint := none;
  202. RETURN res
  203. END GetHint;
  204. PROCEDURE Get(from,to: LONGINT): LONGINT;
  205. VAR i: LONGINT;
  206. BEGIN
  207. i := from;
  208. IF from <= to THEN
  209. WHILE (i <= to) & ((toVirtual[i]#free) OR Reserved(i)) DO INC(i) END;
  210. IF i > to THEN i := none END;
  211. ELSE
  212. WHILE (i >=to) & ((toVirtual[i]#free) OR Reserved(i)) DO DEC(i) END;
  213. IF i < to THEN i := none END;
  214. END;
  215. RETURN i
  216. END Get;
  217. BEGIN
  218. length := type.length;
  219. sizeInBits := type.sizeInBits;
  220. form := type.form;
  221. IF (type.length > 1) THEN
  222. IF (* (type.form = IntermediateCode.Float) &*) (type.sizeInBits<=32) & (type.length =4) THEN
  223. i := Get(XMM7, XMM0);
  224. ELSIF (* (type.form = IntermediateCode.Float) &*) (type.sizeInBits<=32) & (type.length =8) THEN
  225. i := Get(YMM7, YMM0);
  226. ELSE
  227. HALT(100)
  228. END
  229. ELSIF type.form IN IntermediateCode.Integer THEN
  230. sizeInBits := type.sizeInBits;
  231. IF type.sizeInBits = IntermediateCode.Bits8 THEN
  232. i := GetGPHint(AL);
  233. IF i = none THEN i := Get(BL, AL) END;
  234. IF i = none THEN i := Get(BH, AH) END;
  235. ELSIF type.sizeInBits = IntermediateCode.Bits16 THEN
  236. i := GetGPHint(AX);
  237. IF i = none THEN i := Get(DI, SI) END;
  238. IF i = none THEN i := Get(BX, AX) END;
  239. ELSIF type.sizeInBits = IntermediateCode.Bits32 THEN
  240. i := GetGPHint(EAX);
  241. IF i = none THEN i := Get(EDI,ESI) END;
  242. IF i = none THEN i := Get(EBX,EAX) END;
  243. ELSE HALT(100)
  244. END;
  245. ELSE
  246. ASSERT(type.form = IntermediateCode.Float);
  247. IF useFPU THEN
  248. i := Get(InstructionSet.regST0, InstructionSet.regST6);
  249. (* ST7 unusable as it is overwritten during arithmetic instructions *)
  250. ELSE
  251. i := GetHint(XMM0, XMM7);
  252. IF i = none THEN i := Get(XMM7, XMM0) END
  253. END;
  254. END;
  255. hint := none; (* reset *)
  256. RETURN i
  257. END NextFree;
  258. PROCEDURE Mapped(physical: LONGINT): Ticket;
  259. VAR virtual: Ticket;
  260. BEGIN
  261. virtual := toVirtual[physical];
  262. IF virtual = blocked THEN virtual := Mapped(physical+32)
  263. ELSIF virtual = split THEN
  264. IF physical < 32 THEN virtual := Mapped(physical+16 MOD 32)
  265. ELSE virtual := Mapped(physical-32)
  266. END;
  267. END;
  268. ASSERT((virtual = free) OR (virtual = unusable) OR (toVirtual[virtual.register] = virtual));
  269. RETURN virtual
  270. END Mapped;
  271. PROCEDURE Dump(w: Streams.Writer);
  272. VAR i: LONGINT; virtual: Ticket;
  273. BEGIN
  274. w.String("; ---- registers ----"); w.Ln;
  275. FOR i := 0 TO LEN(toVirtual)-1 DO
  276. virtual := toVirtual[i];
  277. IF virtual # unusable THEN
  278. w.String("reg "); w.Int(i,1); w.String(": ");
  279. IF virtual = free THEN w.String("free")
  280. ELSIF virtual = blocked THEN w.String("blocked")
  281. ELSIF virtual = split THEN w.String("split")
  282. ELSE w.String(" r"); w.Int(virtual.register,1);
  283. END;
  284. IF reserved[i] THEN w.String("reserved") END;
  285. w.Ln;
  286. END;
  287. END;
  288. END Dump;
  289. END PhysicalRegisters32;
  290. PhysicalRegisters64=OBJECT (PhysicalRegisters) (* 64 bit implementation *)
  291. PROCEDURE & InitPhysicalRegisters64(fpu,cooperative: BOOLEAN);
  292. BEGIN
  293. InitPhysicalRegisters(fpu,cooperative);
  294. END InitPhysicalRegisters64;
  295. PROCEDURE SetReserved(index: LONGINT; res: BOOLEAN);
  296. BEGIN
  297. (*
  298. IF res THEN D.String("reserve ") ELSE D.String("unreserve ") END;
  299. D.String("register: index="); D.Int(index,1); D.Ln;
  300. *)
  301. IF index DIV 32 <=2 THEN
  302. index := index MOD 16;
  303. reserved[index+AH] := res;
  304. reserved[index+AL] := res;
  305. reserved[index+AX] := res;
  306. reserved[index+EAX] := res;
  307. reserved[index+RAX] := res;
  308. ELSE
  309. reserved[index] := res
  310. END;
  311. END SetReserved;
  312. PROCEDURE Reserved(index: LONGINT): BOOLEAN;
  313. BEGIN
  314. RETURN reserved[index]
  315. END Reserved;
  316. PROCEDURE Allocate(index: LONGINT; virtualRegister: Ticket);
  317. BEGIN
  318. (*
  319. D.String("allocate register x : index="); D.Int(index,1); D.Ln;
  320. *)
  321. Assert(toVirtual[index] = free,"register already allocated");
  322. toVirtual[index] := virtualRegister;
  323. IF index DIV 32 = 3 THEN (* 64 bit *)
  324. Assert(toVirtual[index MOD 32 + EAX] = free,"free register split");
  325. toVirtual[index MOD 32 + EAX] := blocked;
  326. toVirtual[index MOD 32 + AX] := blocked;
  327. toVirtual[index MOD 32 + AL] := blocked;
  328. ELSIF index DIV 32 = 2 THEN (* 32 bit *)
  329. Assert(toVirtual[index MOD 32 + AX] = free,"free register split");
  330. toVirtual[index MOD 32 + RAX] := split;
  331. toVirtual[index MOD 32 + AX] := blocked;
  332. toVirtual[index MOD 32 + AL] := blocked;
  333. ELSIF index DIV 32 = 1 THEN (* 16 bit *)
  334. toVirtual[index MOD 32 + RAX] := split;
  335. toVirtual[index MOD 32 + EAX] := split;
  336. toVirtual[index MOD 32 + AL] := blocked;
  337. ELSIF index DIV 32 = 0 THEN (* 8 bit *)
  338. toVirtual[index MOD 32 + RAX] := split;
  339. toVirtual[index MOD 32 + EAX] := split;
  340. toVirtual[index MOD 32 + AX] := split;
  341. ELSIF (index >= XMM0) & (index <= XMM7) THEN (* vector register *)
  342. ELSIF (index >= YMM0) & (index <= YMM7) THEN (* vector register *)
  343. ELSE Assert( (index >=InstructionSet.regST0) & (index <= InstructionSet.regST7 ),"not a float register"); (* floats *)
  344. END;
  345. END Allocate;
  346. PROCEDURE Free(index: LONGINT);
  347. BEGIN
  348. (*
  349. D.String("release register x : index="); D.Int(index,1); D.Ln;
  350. *)
  351. Assert(toVirtual[index]#NIL,"register not reserved");
  352. toVirtual[index] := free;
  353. IF index DIV 32 =3 THEN (* 64 bit *)
  354. Assert(toVirtual[index MOD 32 + EAX] = blocked,"reserved register did not block");
  355. toVirtual[index MOD 32 + EAX] := free;
  356. toVirtual[index MOD 32 + AX] := free;
  357. toVirtual[index MOD 32 + AL] := free;
  358. ELSIF index DIV 32 =2 THEN (* 32 bit *)
  359. Assert(toVirtual[index MOD 32 + RAX] = split,"reserved register did not split");
  360. Assert(toVirtual[index MOD 32 + AX] = blocked,"reserved register did not block");
  361. Assert(toVirtual[index MOD 32 + AL] = blocked,"reserved register did not block");
  362. toVirtual[index MOD 32 + RAX] := free;
  363. toVirtual[index MOD 32 + AX] := free;
  364. toVirtual[index MOD 32 + AL] := free;
  365. ELSIF index DIV 32 = 1 THEN (* 16 bit *)
  366. Assert(toVirtual[index MOD 32 + RAX] = split,"reserved register did not split");
  367. Assert(toVirtual[index MOD 32 + EAX] = split,"reserved register did not split");
  368. Assert(toVirtual[index MOD 32 + AL] = blocked,"reserved register did not split");
  369. toVirtual[index MOD 32 + RAX] := free;
  370. toVirtual[index MOD 32 + EAX] := free;
  371. toVirtual[index MOD 32 + AL] := free;
  372. ELSIF index DIV 32 = 0 THEN (* 8 bit *)
  373. Assert(toVirtual[index MOD 32 + RAX] = split,"reserved register did not split");
  374. Assert(toVirtual[index MOD 32 + EAX] = split,"reserved register did not split");
  375. Assert(toVirtual[index MOD 32 + AX] = split,"reserved register did not split");
  376. toVirtual[index MOD 32 + RAX] := free;
  377. toVirtual[index MOD 32 + EAX] := free;
  378. toVirtual[index MOD 32 + AX] := free;
  379. ELSIF (index >= XMM0) & (index <= XMM7) THEN (* vector register *)
  380. ELSIF (index >= YMM0) & (index <= YMM7) THEN (* vector register *)
  381. ELSE Assert( (index >=InstructionSet.regST0) & (index <= InstructionSet.regST7 ),"not a float register"); (* floats *)
  382. END;
  383. END Free;
  384. PROCEDURE NextFree(CONST type: IntermediateCode.Type): LONGINT;
  385. VAR i: LONGINT;
  386. PROCEDURE GetGPHint(offset: LONGINT): LONGINT;
  387. VAR res: LONGINT;
  388. BEGIN
  389. IF (hint # none) & (hint >= AL) & (hint <= R15) & (toVirtual[hint MOD 32 + offset]=free) & ~Reserved(hint) THEN res := hint MOD 32 + offset ELSE res := none END;
  390. hint := none;
  391. RETURN res
  392. END GetGPHint;
  393. PROCEDURE Get(from,to: LONGINT): LONGINT;
  394. VAR i: LONGINT;
  395. BEGIN
  396. i := from;
  397. IF from <= to THEN
  398. WHILE (i <= to) & ((toVirtual[i]#free) OR Reserved(i)) DO INC(i) END;
  399. IF i > to THEN i := none END;
  400. ELSE
  401. WHILE (i >=to) & ((toVirtual[i]#free) OR Reserved(i)) DO DEC(i) END;
  402. IF i < to THEN i := none END;
  403. END;
  404. RETURN i
  405. END Get;
  406. BEGIN
  407. IF type.form IN IntermediateCode.Integer THEN
  408. IF type.sizeInBits = IntermediateCode.Bits8 THEN
  409. i := GetGPHint(AL);
  410. IF i = none THEN i := Get(BL, AL) END;
  411. IF i = none THEN i := Get(BH, AH) END;
  412. IF i = none THEN
  413. i := Get(AL,R15B)
  414. END;
  415. ELSIF type.sizeInBits = IntermediateCode.Bits16 THEN
  416. i := GetGPHint(AX);
  417. IF i = none THEN i := Get(DI, SI) END;
  418. IF i = none THEN i := Get(BX, AX) END;
  419. IF i = none THEN
  420. i := Get(AX,R15W);
  421. END;
  422. ELSIF type.sizeInBits = IntermediateCode.Bits32 THEN
  423. i := GetGPHint(EAX);
  424. IF i = none THEN i := Get(EDI,ESI) END;
  425. IF i = none THEN i := Get(EBX,EAX) END;
  426. IF i = none THEN
  427. i := Get(EAX,R15D);
  428. END;
  429. ELSIF type.sizeInBits = IntermediateCode.Bits64 THEN
  430. i := GetGPHint(RAX);
  431. IF i = none THEN i := Get(RDI,RSI) END;
  432. IF i = none THEN i := Get(RBX,RAX) END;
  433. IF i = none THEN
  434. i := Get(RAX, R15)
  435. END;
  436. ELSE HALT(100)
  437. END;
  438. ELSE
  439. ASSERT(type.form = IntermediateCode.Float);
  440. IF useFPU THEN
  441. i := Get(InstructionSet.regST0, InstructionSet.regST6);
  442. (* ST7 unusable as it is overwritten during arithmetic instructions *)
  443. ELSE
  444. i := Get(XMM7, XMM0)
  445. END;
  446. END;
  447. RETURN i;
  448. END NextFree;
  449. PROCEDURE Mapped(physical: LONGINT): Ticket;
  450. VAR virtual: Ticket;
  451. BEGIN
  452. virtual := toVirtual[physical];
  453. IF virtual = blocked THEN RETURN Mapped(physical+32) END;
  454. IF virtual = split THEN RETURN Mapped(physical-32) END;
  455. RETURN virtual
  456. END Mapped;
  457. END PhysicalRegisters64;
  458. CodeGeneratorAMD64 = OBJECT (CodeGenerators.GeneratorWithTickets)
  459. VAR
  460. (* static generator state variables, considered constant during generation *)
  461. runtimeModuleName: SyntaxTree.IdentifierString;
  462. cpuBits: LONGINT;
  463. opBP, opSP, opRA, opRB, opRC, opRD, opRSI, opRDI, opR8, opR9, opR10, opR11, opR12, opR13, opR14, opR15: Assembler.Operand; (* base pointer, stack pointer, register A, depends on cpuBits*)
  464. BP, SP, RA, RD, RS, RC: LONGINT; (* base pointer and stack pointer register index, depends on cpuBits *)
  465. emitter: Assembler.Emitter; (* assembler generating and containing the machine code *)
  466. backend: BackendAMD64;
  467. (* register spill state *)
  468. stackSize: LONGINT;
  469. spillStackStart: LONGINT;
  470. (* floating point stack state *)
  471. fpStackPointer: LONGINT; (* floating point stack pointer, increases with allocation, decreases with releasing, used to determine current relative position on stack (as is necessary for intel FP instructions) *)
  472. (*
  473. FP register usage scheme:
  474. sp=1> FP0 - temp
  475. sp=0> FP0 - reg0 FP1 - reg0 sp=0> FP0 - reg0
  476. FP1 - reg1 FP2 - reg1 FP1 - reg1
  477. FP2 - reg2 FP3 - reg2 FP2 - reg2
  478. FP3 - reg3 = load op1 => FP4 - reg3 = op => FP3 - reg3
  479. FP4 - reg4 FP5 - reg4 FP4 - reg4
  480. FP5 - reg5 FP6 - reg5 FP5 - reg5
  481. FP6 - reg6 FP7 - reg6 FP6 - reg6
  482. FP7 - reg7 (reg7 lost) FP7 - reg7
  483. *)
  484. ap: Ticket;
  485. (* -------------------------- constructor -------------------------------*)
  486. PROCEDURE &InitGeneratorAMD64(CONST runtime: SyntaxTree.IdentifierString; diagnostics: Diagnostics.Diagnostics; backend: BackendAMD64);
  487. VAR physicalRegisters: PhysicalRegisters; physicalRegisters32: PhysicalRegisters32; physicalRegisters64: PhysicalRegisters64;
  488. BEGIN
  489. SELF.backend := backend;
  490. runtimeModuleName := runtime;
  491. SELF.cpuBits := backend.bits;
  492. NEW(emitter,diagnostics);
  493. IF cpuBits=32 THEN
  494. NEW(physicalRegisters32, backend.forceFPU, backend.cooperative); physicalRegisters := physicalRegisters32; error := ~emitter.SetBits(32);
  495. opBP := opEBP; opSP := opESP; opRA := opEAX; opRB := opEBX; opRD := opEDX; opRDI := opEDI; opRSI := opESI; opRC := opECX;
  496. SP := ESP; BP := EBP; RA := EAX;
  497. RD := EDI; RS := ESI; RC := ECX;
  498. ASSERT(~error);
  499. ELSIF cpuBits=64 THEN
  500. NEW(physicalRegisters64, backend.forceFPU, backend.cooperative); physicalRegisters := physicalRegisters64; error := ~emitter.SetBits(64);
  501. opBP := opRBP; opSP := opRSP;
  502. opRA := registerOperands[RAX]; opRC := registerOperands[RCX];
  503. opRB := registerOperands[RBX]; opRD := registerOperands[RDX];
  504. opRDI := registerOperands[RDI]; opRSI := registerOperands[RSI];
  505. opR8 := registerOperands[R8]; opR9 := registerOperands[R9];
  506. opR10 := registerOperands[R10]; opR11 := registerOperands[R11];
  507. opR12 := registerOperands[R12]; opR13 := registerOperands[R13];
  508. opR14 := registerOperands[R14]; opR15 := registerOperands[R15];
  509. SP := RSP; BP := RBP; RA := RAX;
  510. RD := RDI; RS := RSI; RC := RCX;
  511. ASSERT(~error);
  512. ELSE Halt("no register allocator for bits other than 32 / 64 ");
  513. END;
  514. fpStackPointer := 0;
  515. InitTicketGenerator(diagnostics,backend.optimize,2,physicalRegisters);
  516. END InitGeneratorAMD64;
  517. (*------------------- overwritten methods ----------------------*)
  518. PROCEDURE Section(in: IntermediateCode.Section; out: BinaryCode.Section);
  519. VAR oldSpillStackSize: LONGINT;
  520. PROCEDURE CheckEmptySpillStack;
  521. BEGIN
  522. IF spillStack.Size()#0 THEN Error(Basic.invalidPosition,"implementation error, spill stack not cleared") END;
  523. END CheckEmptySpillStack;
  524. BEGIN
  525. spillStack.Init;
  526. IF backend.cooperative THEN
  527. ap := ReservePhysicalRegister(IntermediateCode.GeneralPurposeRegister,IntermediateCode.UnsignedIntegerType(cpuBits),RC,in.pc);
  528. ap.spillable := FALSE;
  529. END;
  530. emitter.SetCode(out);
  531. Section^(in,out);
  532. IF FrameSpillStack & (spillStack.MaxSize() >0) THEN
  533. oldSpillStackSize := spillStack.MaxSize();
  534. out.Reset;
  535. CheckEmptySpillStack;
  536. Section^(in,out);
  537. ASSERT(spillStack.MaxSize() = oldSpillStackSize);
  538. END;
  539. ASSERT(fpStackPointer = 0);
  540. CheckEmptySpillStack;
  541. IF backend.cooperative THEN
  542. UnmapTicket(ap);
  543. END;
  544. error := error OR emitter.error;
  545. END Section;
  546. PROCEDURE Supported(CONST instruction: IntermediateCode.Instruction; VAR moduleName, procedureName: ARRAY OF CHAR): BOOLEAN;
  547. BEGIN
  548. COPY(runtimeModuleName, moduleName);
  549. IF (cpuBits=32) & (instruction.op2.type.sizeInBits = IntermediateCode.Bits64) & (instruction.op2.type.form IN IntermediateCode.Integer) THEN
  550. CASE instruction.opcode OF
  551. IntermediateCode.div:
  552. procedureName := "DivH"; RETURN FALSE
  553. | IntermediateCode.mul:
  554. procedureName := "MulH"; RETURN FALSE
  555. | IntermediateCode.mod :
  556. procedureName := "ModH"; RETURN FALSE
  557. | IntermediateCode.abs :
  558. procedureName := "AbsH"; RETURN FALSE;
  559. | IntermediateCode.shl :
  560. IF instruction.op1.type.form = IntermediateCode.SignedInteger THEN
  561. procedureName := "AslH"; RETURN FALSE;
  562. ELSE
  563. procedureName := "LslH"; RETURN FALSE;
  564. END;
  565. | IntermediateCode.shr :
  566. IF instruction.op1.type.form = IntermediateCode.SignedInteger THEN
  567. procedureName := "AsrH"; RETURN FALSE;
  568. ELSE
  569. procedureName := "LsrH"; RETURN FALSE;
  570. END;
  571. | IntermediateCode.ror :
  572. procedureName := "RorH"; RETURN FALSE;
  573. | IntermediateCode.rol :
  574. procedureName := "RolH"; RETURN FALSE;
  575. | IntermediateCode.cas :
  576. procedureName := "CasH"; RETURN FALSE;
  577. ELSE RETURN TRUE
  578. END;
  579. ELSIF ~backend.forceFPU & (instruction.opcode = IntermediateCode.conv) & (instruction.op1.type.form IN IntermediateCode.Integer) & (instruction.op2.type.form = IntermediateCode.Float) & IsComplex(instruction.op1) THEN
  580. IF instruction.op2.type.sizeInBits=32 THEN
  581. procedureName := "EntierRH"
  582. ELSE
  583. procedureName := "EntierXH"
  584. END;
  585. RETURN FALSE
  586. END;
  587. RETURN TRUE
  588. END Supported;
  589. (* input: type (such as that of an intermediate operand), output: low and high type (such as in low and high type of an operand) *)
  590. PROCEDURE GetPartType(CONST type: IntermediateCode.Type; part: LONGINT; VAR typePart: IntermediateCode.Type);
  591. BEGIN
  592. ASSERT(type.sizeInBits >0);
  593. IF (type.sizeInBits > cpuBits) & (type.form IN IntermediateCode.Integer) THEN
  594. IntermediateCode.InitType(typePart,type.form,32);
  595. ELSE ASSERT((type.form IN IntermediateCode.Integer) OR (type.form = IntermediateCode.Float));
  596. IF part=Low THEN typePart := type ELSE typePart := IntermediateCode.undef END;
  597. END;
  598. END GetPartType;
  599. (* simple move without conversion *)
  600. PROCEDURE Move(VAR dest, src: Assembler.Operand; CONST type: IntermediateCode.Type);
  601. BEGIN
  602. IF type.length > 1 THEN
  603. IF type.length = 4 THEN
  604. (*ASSERT(type.form = IntermediateCode.Float);*)
  605. IF (*(type.form = IntermediateCode.Float) & *) (type.sizeInBits = 32) THEN
  606. SpecialMove(InstructionSet.opMOVUPS, InstructionSet.opMOVUPS, TRUE, dest, src, type);
  607. ELSIF (type.sizeInBits = 16) THEN
  608. SpecialMove(InstructionSet.opMOVQ, InstructionSet.opMOVQ, TRUE, dest, src, type);
  609. ELSIF (type.sizeInBits = 8) THEN
  610. SpecialMove(InstructionSet.opMOVD, InstructionSet.opMOVD, TRUE, dest, src, type);
  611. END;
  612. ELSIF type.length = 8 THEN
  613. (*ASSERT(type.form = IntermediateCode.Float);*)
  614. IF (*(type.form = IntermediateCode.Float) & *) (type.sizeInBits = 32) THEN
  615. SpecialMove(InstructionSet.opVMOVUPS, InstructionSet.opVMOVUPS, TRUE, dest, src, type);
  616. ELSIF (type.sizeInBits = 16) THEN
  617. SpecialMove(InstructionSet.opVMOVQ, InstructionSet.opVMOVQ, TRUE, dest, src, type);
  618. ELSIF (type.sizeInBits = 8) THEN
  619. SpecialMove(InstructionSet.opVMOVD, InstructionSet.opVMOVD, TRUE, dest, src, type);
  620. END;
  621. ELSE
  622. (*
  623. ASSERT(type.form = IntermediateCode.Float);
  624. *)
  625. ASSERT(type.sizeInBits = 64);
  626. SpecialMove(InstructionSet.opMOVUPD, InstructionSet.opMOVUPS, TRUE, dest, src, type);
  627. END;
  628. ELSIF type.form = IntermediateCode.Float THEN
  629. IF type.sizeInBits = 32 THEN
  630. SpecialMove(InstructionSet.opMOVSS, InstructionSet.opMOVSS, TRUE, dest, src, type);
  631. ELSE
  632. SpecialMove(InstructionSet.opMOVSD, InstructionSet.opMOVSD, TRUE, dest, src, type);
  633. END;
  634. ELSE
  635. SpecialMove(InstructionSet.opMOV, InstructionSet.opMOV, TRUE, dest, src, type);
  636. END;
  637. END Move;
  638. PROCEDURE ToSpillStack(ticket: Ticket);
  639. VAR op: Assembler.Operand;
  640. BEGIN
  641. IF (ticket.type.form = IntermediateCode.Float) & backend.forceFPU THEN
  642. emitter.Emit1(InstructionSet.opFLD,registerOperands[ticket.register]);
  643. INC(fpStackPointer);
  644. GetSpillOperand(ticket,op);
  645. emitter.Emit1(InstructionSet.opFSTP,op);
  646. DEC(fpStackPointer);
  647. ELSE
  648. GetSpillOperand(ticket,op);
  649. Move(op, registerOperands[ticket.register], ticket.type)
  650. END;
  651. END ToSpillStack;
  652. PROCEDURE AllocateSpillStack(size: LONGINT);
  653. BEGIN
  654. IF ~FrameSpillStack THEN
  655. AllocateStack(cpuBits DIV 8*size)
  656. END;
  657. END AllocateSpillStack;
  658. PROCEDURE ToRegister(ticket: Ticket);
  659. VAR op: Assembler.Operand;
  660. BEGIN
  661. GetSpillOperand(ticket,op);
  662. emitter.Emit2(InstructionSet.opMOV,registerOperands[ticket.register],op);
  663. END ToRegister;
  664. PROCEDURE ExchangeTickets(ticket1,ticket2: Ticket);
  665. VAR op1,op2: Assembler.Operand;
  666. BEGIN
  667. TicketToOperand(ticket1, op1);
  668. TicketToOperand(ticket2, op2);
  669. emitter.Emit2(InstructionSet.opXCHG, op1,op2);
  670. END ExchangeTickets;
  671. (*------------------- particular register mappings / operands ----------------------*)
  672. (* returns if a virtual register is mapped to the register set described by virtualRegisterMapping*)
  673. PROCEDURE MappedTo(CONST virtualRegister: LONGINT; part:LONGINT; physicalRegister: LONGINT): BOOLEAN;
  674. VAR ticket: Ticket;
  675. BEGIN
  676. IF (virtualRegister > 0) THEN
  677. ticket := virtualRegisters.Mapped(virtualRegister,part);
  678. RETURN (ticket # NIL) & ~(ticket.spilled) & (ticket.register = physicalRegister)
  679. ELSIF (virtualRegister = IntermediateCode.FP) THEN
  680. RETURN physicalRegister= BP
  681. ELSIF (virtualRegister = IntermediateCode.SP) THEN
  682. RETURN physicalRegister = SP
  683. ELSIF (virtualRegister = IntermediateCode.AP) THEN
  684. ASSERT(backend.cooperative);
  685. RETURN ~(ap.spilled) & (ap.register = physicalRegister)
  686. ELSE
  687. RETURN FALSE
  688. END;
  689. END MappedTo;
  690. PROCEDURE ResultRegister(CONST type: IntermediateCode.Type; part: LONGINT): LONGINT;
  691. BEGIN
  692. IF type.form IN IntermediateCode.Integer THEN
  693. CASE type.sizeInBits OF
  694. | 64:
  695. IF cpuBits = 32 THEN
  696. IF part = Low THEN RETURN EAX
  697. ELSE RETURN EDX
  698. END;
  699. ELSE
  700. ASSERT(part = Low);
  701. RETURN RAX
  702. END;
  703. | 32: ASSERT(part=Low); RETURN EAX
  704. | 16: ASSERT(part=Low); RETURN AX
  705. | 8: ASSERT(part=Low); RETURN AL
  706. END;
  707. ELSIF ~backend.forceFPU THEN
  708. RETURN XMM0
  709. ELSE ASSERT(type.form = IntermediateCode.Float);ASSERT(part=Low);
  710. RETURN ST0
  711. END;
  712. END ResultRegister;
  713. (*------------------- operand reflection ----------------------*)
  714. PROCEDURE IsMemoryOperand(vop: IntermediateCode.Operand; part: LONGINT): BOOLEAN;
  715. VAR ticket: Ticket;
  716. BEGIN
  717. IF vop.mode = IntermediateCode.ModeMemory THEN RETURN TRUE
  718. ELSIF vop.mode = IntermediateCode.ModeRegister THEN
  719. ticket := virtualRegisters.Mapped(vop.register,part);
  720. RETURN (ticket # NIL) & (ticket.spilled);
  721. ELSE RETURN FALSE
  722. END;
  723. END IsMemoryOperand;
  724. PROCEDURE IsRegister(CONST vop: IntermediateCode.Operand): BOOLEAN;
  725. BEGIN
  726. RETURN (vop.mode = IntermediateCode.ModeRegister) & (vop.offset = 0)
  727. END IsRegister;
  728. (* infer intermediate code type from physical operand as far as possible *)
  729. PROCEDURE PhysicalOperandType(CONST op:Assembler.Operand): IntermediateCode.Type;
  730. VAR type:IntermediateCode.Type;
  731. BEGIN
  732. IF op.type = Assembler.sti THEN
  733. IntermediateCode.InitType(type, IntermediateCode.Float, op.sizeInBytes*8)
  734. ELSE
  735. IntermediateCode.InitType(type, IntermediateCode.SignedInteger, op.sizeInBytes*8)
  736. END;
  737. RETURN type
  738. END PhysicalOperandType;
  739. (*------------------- operand generation ----------------------*)
  740. PROCEDURE GetSpillOperand(ticket: Ticket; VAR op: Assembler.Operand);
  741. BEGIN
  742. IF FrameSpillStack THEN
  743. op := Assembler.NewMem(SHORTINT(ticket.type.sizeInBits*ticket.type.length DIV 8), BP , -(spillStackStart + cpuBits DIV 8 + ticket.offset*cpuBits DIV 8));
  744. ELSE
  745. op := Assembler.NewMem(SHORTINT(ticket.type.sizeInBits*ticket.type.length DIV 8),SP , (spillStack.Size()-ticket.offset)*cpuBits DIV 8);
  746. END;
  747. END GetSpillOperand;
  748. PROCEDURE TicketToOperand(ticket: Ticket; VAR op: Assembler.Operand);
  749. BEGIN
  750. IF (ticket = NIL) THEN
  751. Assembler.InitOperand(op)
  752. ELSIF ticket.spilled THEN
  753. GetSpillOperand(ticket,op)
  754. ELSE
  755. IF ticket.register = none THEN physicalRegisters.Dump(D.Log); tickets.Dump(D.Log); virtualRegisters.Dump(D.Log); D.Update; END;
  756. ASSERT(ticket.register # none);
  757. IF (ticket.type.form = IntermediateCode.Float) & backend.forceFPU THEN
  758. op := registerOperands[ticket.register+fpStackPointer]
  759. ELSE
  760. op := registerOperands[ticket.register];
  761. END;
  762. END;
  763. END TicketToOperand;
  764. PROCEDURE GetTemporaryRegister(type: IntermediateCode.Type; VAR op: Assembler.Operand);
  765. BEGIN
  766. TicketToOperand(TemporaryTicket(IntermediateCode.GeneralPurposeRegister,type),op)
  767. END GetTemporaryRegister;
  768. PROCEDURE GetImmediateMem(CONST vop: IntermediateCode.Operand; part: LONGINT; VAR imm: Assembler.Operand);
  769. VAR data: IntermediateCode.Section;pc: LONGINT;
  770. BEGIN
  771. data := GetDataSection();
  772. pc := IntermediateBackend.EnterImmediate(data,vop);
  773. Assembler.InitMem(imm, SHORT(vop.type.sizeInBits DIV 8) , Assembler.none,0);
  774. Assembler.SetSymbol(imm,data.name,0,pc,0);
  775. END GetImmediateMem;
  776. PROCEDURE GetImmediate(CONST virtual: IntermediateCode.Operand; part: LONGINT; VAR physical: Assembler.Operand; forbidden16Bit: BOOLEAN);
  777. VAR type: IntermediateCode.Type; temp: Assembler.Operand; size: SHORTINT; value: HUGEINT;
  778. PROCEDURE IsImm8(value: HUGEINT): BOOLEAN;
  779. BEGIN
  780. RETURN (value >= -80H) & (value < 80H)
  781. END IsImm8;
  782. PROCEDURE IsImm16(value: HUGEINT): BOOLEAN;
  783. BEGIN
  784. RETURN (value >= -8000H) & (value < 10000H)
  785. END IsImm16;
  786. PROCEDURE IsImm32(value: HUGEINT): BOOLEAN;
  787. BEGIN
  788. value := value DIV 10000H DIV 10000H;
  789. RETURN (value = 0) OR (value=-1);
  790. END IsImm32;
  791. BEGIN
  792. ASSERT(virtual.mode = IntermediateCode.ModeImmediate);
  793. GetPartType(virtual.type,part,type);
  794. IF virtual.type.form IN IntermediateCode.Integer THEN
  795. IF IsComplex(virtual) THEN
  796. IF part = High THEN value := SHORT(virtual.intValue DIV 10000H DIV 10000H)
  797. ELSE value := virtual.intValue
  798. END;
  799. ELSE value := virtual.intValue
  800. END;
  801. IF virtual.symbol.name # "" THEN size := SHORT(type.sizeInBits DIV 8);
  802. ELSIF forbidden16Bit & IsImm16(value) & ~(IsImm8(value)) THEN size := Assembler.bits32;
  803. ELSIF (type.sizeInBits = 64) & (type.form = IntermediateCode.UnsignedInteger) & (value > MAX(LONGINT)) THEN
  804. size := 8; (* don't use negative signed 32-bit value to encode 64-bit unsigned value! *)
  805. ELSE size := 0
  806. END;
  807. Assembler.InitImm(physical,size ,value);
  808. IF virtual.symbol.name # "" THEN Assembler.SetSymbol(physical,virtual.symbol.name,virtual.symbol.fingerprint,virtual.symbolOffset,virtual.offset+part*Assembler.bits32) END;
  809. IF (cpuBits=64) & ((physical.sizeInBytes=8) OR ~IsImm32(value)) THEN
  810. ASSERT(cpuBits=64);
  811. GetTemporaryRegister(IntermediateCode.int64,temp);
  812. emitter.Emit2(InstructionSet.opMOV,temp,physical);
  813. physical := temp;
  814. END;
  815. ELSE
  816. GetImmediateMem(virtual,part,physical);
  817. END;
  818. END GetImmediate;
  819. PROCEDURE GetMemory(CONST virtual: IntermediateCode.Operand; part: LONGINT; VAR physical: Assembler.Operand);
  820. VAR type: IntermediateCode.Type; virtualRegister, physicalRegister,offset: LONGINT; ticket,orig: Ticket; dest, source: Assembler.Operand;
  821. BEGIN
  822. ASSERT(virtual.mode = IntermediateCode.ModeMemory);
  823. GetPartType(virtual.type,part,type);
  824. IF virtual.register # IntermediateCode.None THEN
  825. virtualRegister := virtual.register;
  826. IF virtualRegister = IntermediateCode.FP THEN physicalRegister := BP;
  827. ELSIF virtualRegister = IntermediateCode.SP THEN physicalRegister := SP;
  828. ELSE
  829. IF virtualRegister = IntermediateCode.AP THEN
  830. ticket := ap;
  831. ELSE
  832. ticket := virtualRegisters.Mapped(virtualRegister,Low);
  833. END;
  834. IF ticket.spilled THEN
  835. IF physicalRegisters.Reserved(ticket.register) THEN
  836. orig := ticket;
  837. ticket := TemporaryTicket(IntermediateCode.GeneralPurposeRegister,IntermediateBackend.GetType(module.system,module.system.addressType));
  838. TicketToOperand(orig,source);
  839. TicketToOperand(ticket,dest);
  840. Move(dest,source,PhysicalOperandType(dest));
  841. physicalRegister := ticket.register;
  842. ELSE
  843. UnSpill(ticket);
  844. physicalRegister := ticket.register;
  845. END;
  846. ELSE
  847. physicalRegister := ticket.register;
  848. END;
  849. END;
  850. offset := virtual.offset;
  851. ASSERT(virtual.intValue = 0);
  852. ELSIF virtual.symbol.name # "" THEN
  853. physicalRegister := Assembler.none;
  854. offset := virtual.offset;
  855. ASSERT(virtual.intValue = 0);
  856. ELSE
  857. physicalRegister := Assembler.none;
  858. offset := SHORT(virtual.intValue);
  859. ASSERT(virtual.offset = 0);
  860. END;
  861. Assembler.InitMem(physical, SHORTINT(type.length * type.sizeInBits DIV 8) , physicalRegister, offset+4*part);
  862. IF virtual.symbol.name # "" THEN
  863. Assembler.SetSymbol(physical,virtual.symbol.name,virtual.symbol.fingerprint,virtual.symbolOffset,virtual.offset+4*part);
  864. END;
  865. END GetMemory;
  866. PROCEDURE GetRegister(CONST virtual: IntermediateCode.Operand; part:LONGINT; VAR physical: Assembler.Operand; VAR ticket: Ticket);
  867. VAR type: IntermediateCode.Type; virtualRegister, tempReg: LONGINT;
  868. tmp,imm: Assembler.Operand; index: LONGINT;
  869. BEGIN
  870. ASSERT(virtual.mode = IntermediateCode.ModeRegister);
  871. GetPartType(virtual.type,part,type);
  872. virtualRegister := virtual.register;
  873. IF (virtual.register > 0) THEN
  874. TicketToOperand(virtualRegisters.Mapped(virtual.register,part), physical);
  875. ELSIF virtual.register = IntermediateCode.FP THEN
  876. Assert(part=Low,"forbidden partitioned register on BP");
  877. physical := opBP;
  878. ELSIF virtual.register = IntermediateCode.SP THEN
  879. Assert(part=Low,"forbidden partitioned register on SP");
  880. physical := opSP;
  881. ELSIF virtual.register = IntermediateCode.AP THEN
  882. ASSERT(backend.cooperative);
  883. Assert(part=Low,"forbidden partitioned register on AP");
  884. TicketToOperand(ap, physical);
  885. ELSE HALT(100);
  886. END;
  887. IF virtual.offset # 0 THEN
  888. Assert(type.form # IntermediateCode.Float,"forbidden offset on float");
  889. IF ticket = NIL THEN
  890. tempReg := ForceFreeRegister(type);
  891. TicketToOperand(ReservePhysicalRegister(IntermediateCode.GeneralPurposeRegister,type,tempReg,inPC),tmp);
  892. ELSE
  893. TicketToOperand(ticket, tmp);
  894. ticket := NIL;
  895. END;
  896. IF Assembler.IsRegisterOperand(physical) & (type.sizeInBits > 8) THEN
  897. Assembler.InitMem(physical,SHORTINT(type.length * type.sizeInBits DIV 8) , physical.register, virtual.offset);
  898. emitter.Emit2(InstructionSet.opLEA, tmp,physical);
  899. ELSE
  900. emitter.Emit2(InstructionSet.opMOV,tmp,physical);
  901. Assembler.InitImm(imm,0 ,virtual.offset);
  902. emitter.Emit2(InstructionSet.opADD,tmp,imm);
  903. END;
  904. physical := tmp;
  905. END;
  906. END GetRegister;
  907. (* make physical operand from virtual operand, if ticket given then write result into phyiscal register represented by ticket *)
  908. PROCEDURE MakeOperand(CONST vop: IntermediateCode.Operand; part: LONGINT; VAR op: Assembler.Operand; ticket: Ticket);
  909. VAR tmp: Assembler.Operand;
  910. BEGIN
  911. TryAllocate(vop,part);
  912. CASE vop.mode OF
  913. IntermediateCode.ModeMemory: GetMemory(vop,part,op);
  914. |IntermediateCode.ModeRegister: GetRegister(vop,part,op,ticket);
  915. |IntermediateCode.ModeImmediate: GetImmediate(vop,part,op,FALSE);
  916. END;
  917. IF ticket # NIL THEN
  918. TicketToOperand(ticket, tmp);
  919. emitter.Emit2(InstructionSet.opMOV, tmp, op);
  920. (* should work but does not
  921. IF Assembler.IsRegisterOperand(op) THEN ReleaseHint(op.register) END;
  922. *)
  923. op := tmp;
  924. END;
  925. END MakeOperand;
  926. (* make physical register operand from virtual operand *)
  927. PROCEDURE MakeRegister(CONST vop: IntermediateCode.Operand; part: LONGINT; VAR op: Assembler.Operand);
  928. VAR previous: Assembler.Operand; temp: Ticket;
  929. BEGIN
  930. MakeOperand(vop,part,op,NIL);
  931. IF ~Assembler.IsRegisterOperand(op) THEN
  932. previous := op;
  933. temp := TemporaryTicket(vop.registerClass,vop.type);
  934. TicketToOperand(temp,op);
  935. Move(op, previous, vop.type);
  936. END;
  937. END MakeRegister;
  938. (*------------------- helpers for code generation ----------------------*)
  939. (* move, potentially with conversion. parameter back used for moving back from temporary operand*)
  940. PROCEDURE SpecialMove(op, back: LONGINT; canStoreToMemory: BOOLEAN; VAR dest,src: Assembler.Operand; type: IntermediateCode.Type);
  941. VAR temp: Assembler.Operand; ticket: Ticket;
  942. BEGIN
  943. IF Assembler.SameOperand(src,dest) THEN (* do nothing *)
  944. ELSIF ~Assembler.IsMemoryOperand(dest) OR (~Assembler.IsMemoryOperand(src) & canStoreToMemory) THEN
  945. emitter.Emit2(op,dest,src);
  946. ELSE
  947. ticket := TemporaryTicket(IntermediateCode.GeneralPurposeRegister,type);
  948. TicketToOperand(ticket,temp);
  949. emitter.Emit2(op,temp,src);
  950. emitter.Emit2(back,dest,temp);
  951. UnmapTicket(ticket);
  952. END;
  953. END SpecialMove;
  954. PROCEDURE AllocateStack(sizeInBytes: LONGINT);
  955. VAR sizeOp: Assembler.Operand; opcode: LONGINT;
  956. BEGIN
  957. ASSERT(sizeInBytes MOD 4 (* (cpuBits DIV 8) *) = 0);
  958. IF sizeInBytes < 0 THEN
  959. sizeInBytes := -sizeInBytes; opcode := InstructionSet.opADD;
  960. ELSIF sizeInBytes > 0 THEN
  961. opcode := InstructionSet.opSUB;
  962. ELSE RETURN
  963. END;
  964. IF sizeInBytes < 128 THEN sizeOp := Assembler.NewImm8(sizeInBytes);
  965. ELSE sizeOp := Assembler.NewImm32(sizeInBytes);
  966. END;
  967. emitter.Emit2(opcode,opSP,sizeOp);
  968. END AllocateStack;
  969. (*------------------- generation = emit dispatch / emit procedures ----------------------*)
  970. PROCEDURE IsFloat(CONST operand: IntermediateCode.Operand): BOOLEAN;
  971. BEGIN RETURN operand.type.form = IntermediateCode.Float
  972. END IsFloat;
  973. PROCEDURE IsComplex(CONST operand: IntermediateCode.Operand): BOOLEAN;
  974. BEGIN RETURN (operand.type.form IN IntermediateCode.Integer) & (operand.type.sizeInBits > cpuBits)
  975. END IsComplex;
  976. PROCEDURE Generate(VAR instruction: IntermediateCode.Instruction);
  977. VAR opcode: SHORTINT; ticket: Ticket; hwreg, lastUse, i, part: LONGINT;
  978. BEGIN
  979. (*!IF ((instruction.opcode = IntermediateCode.mov) OR (instruction.opcode = IntermediateCode.pop)) & (instruction.op1.register <= IntermediateCode.ParameterRegister) THEN
  980. hwreg := ParameterRegister(IntermediateCode.ParameterRegister-instruction.op1.register, instruction.op1.type);
  981. Spill(physicalRegisters.Mapped(hwreg));
  982. lastUse := inPC+1;
  983. WHILE (lastUse < in.pc) &
  984. ((in.instructions[lastUse].opcode # IntermediateCode.push) OR (in.instructions[lastUse].op1.register # instruction.op1.register)) & (in.instructions[lastUse].opcode # IntermediateCode.call) DO
  985. INC(lastUse)
  986. END;
  987. ticket := ReservePhysicalRegister(instruction.op1.type,hwreg,lastUse);
  988. END;
  989. *)
  990. ReserveOperandRegisters(instruction.op1,TRUE); ReserveOperandRegisters(instruction.op2,TRUE);ReserveOperandRegisters(instruction.op3,TRUE);
  991. (*TryAllocate(instruction.op1,Low);
  992. IF IsComplex(instruction.op1) THEN TryAllocate(instruction.op1,High) END;
  993. *)
  994. opcode := instruction.opcode;
  995. CASE opcode OF
  996. IntermediateCode.nop: (* do nothing *)
  997. |IntermediateCode.mov:
  998. IF IsFloat(instruction.op1) OR IsFloat(instruction.op2) THEN
  999. EmitMovFloat(instruction.op1,instruction.op2)
  1000. ELSE EmitMov(instruction.op1,instruction.op2,Low);
  1001. IF IsComplex(instruction.op1) THEN EmitMov(instruction.op1,instruction.op2, High) END;
  1002. END;
  1003. |IntermediateCode.conv:
  1004. IF IsFloat(instruction.op1) OR IsFloat(instruction.op2) THEN
  1005. EmitConvertFloat(instruction)
  1006. ELSE
  1007. EmitConvert(instruction.op1,instruction.op2,Low);
  1008. IF IsComplex(instruction.op1) THEN EmitConvert(instruction.op1,instruction.op2,High) END;
  1009. END;
  1010. |IntermediateCode.call: EmitCall(instruction);
  1011. |IntermediateCode.enter: EmitEnter(instruction);
  1012. |IntermediateCode.leave: EmitLeave(instruction);
  1013. |IntermediateCode.exit: EmitExit(instruction);
  1014. |IntermediateCode.result:
  1015. IF IsFloat(instruction.op1) & backend.forceFPU THEN
  1016. EmitResultFPU(instruction)
  1017. ELSE
  1018. EmitResult(instruction);
  1019. END;
  1020. |IntermediateCode.return:
  1021. IF IsFloat(instruction.op1) & backend.forceFPU THEN
  1022. EmitReturnFPU(instruction)
  1023. ELSE
  1024. EmitReturn(instruction,Low);
  1025. IF IsComplex(instruction.op1) THEN EmitReturn(instruction, High) END;
  1026. END;
  1027. |IntermediateCode.trap: EmitTrap(instruction);
  1028. |IntermediateCode.br .. IntermediateCode.brlt: EmitBr(instruction)
  1029. |IntermediateCode.pop:
  1030. IF IsFloat(instruction.op1) THEN
  1031. EmitPopFloat(instruction.op1)
  1032. ELSE
  1033. EmitPop(instruction.op1,Low);
  1034. IF IsComplex(instruction.op1) THEN
  1035. EmitPop(instruction.op1,High)
  1036. END;
  1037. END;
  1038. |IntermediateCode.push:
  1039. IF IsFloat(instruction.op1) THEN
  1040. EmitPushFloat(instruction.op1)
  1041. ELSE
  1042. IF IsComplex(instruction.op1) THEN
  1043. EmitPush(instruction.op1,High);
  1044. END;
  1045. EmitPush(instruction.op1,Low)
  1046. END;
  1047. |IntermediateCode.neg:
  1048. IF IsFloat(instruction.op1) THEN
  1049. IF backend.forceFPU THEN
  1050. EmitArithmetic2FPU(instruction,InstructionSet.opFCHS)
  1051. ELSE
  1052. EmitNegXMM(instruction)
  1053. END;
  1054. ELSE EmitNeg(instruction);
  1055. END;
  1056. |IntermediateCode.not:
  1057. Assert(~IsFloat(instruction.op1),"instruction not supported for float");
  1058. EmitArithmetic2(instruction,Low,InstructionSet.opNOT);
  1059. IF IsComplex(instruction.op1) THEN EmitArithmetic2(instruction, High, InstructionSet.opNOT) END;
  1060. |IntermediateCode.abs:
  1061. IF IsFloat(instruction.op1) THEN
  1062. IF backend.forceFPU THEN
  1063. EmitArithmetic2FPU(instruction,InstructionSet.opFABS)
  1064. ELSE
  1065. EmitAbsXMM(instruction)
  1066. END;
  1067. ELSE EmitAbs(instruction);
  1068. END;
  1069. |IntermediateCode.mul:
  1070. IF IsFloat(instruction.op1) THEN
  1071. IF backend.forceFPU THEN
  1072. EmitArithmetic3FPU(instruction,InstructionSet.opFMUL)
  1073. ELSE
  1074. EmitArithmetic3XMM(instruction, InstructionSet.opMULSS, InstructionSet.opMULSD)
  1075. END;
  1076. ELSE
  1077. EmitMul(instruction);
  1078. END;
  1079. |IntermediateCode.div:
  1080. IF IsFloat(instruction.op1 )THEN
  1081. IF backend.forceFPU THEN
  1082. EmitArithmetic3FPU(instruction,InstructionSet.opFDIV)
  1083. ELSE
  1084. EmitArithmetic3XMM(instruction, InstructionSet.opDIVSS, InstructionSet.opDIVSD)
  1085. END;
  1086. ELSE
  1087. EmitDivMod(instruction);
  1088. END;
  1089. |IntermediateCode.mod:
  1090. Assert(~IsFloat(instruction.op1),"instruction not supported for float");
  1091. EmitDivMod(instruction);
  1092. |IntermediateCode.sub:
  1093. IF IsFloat(instruction.op1) THEN
  1094. IF backend.forceFPU THEN
  1095. EmitArithmetic3FPU(instruction,InstructionSet.opFSUB)
  1096. ELSE
  1097. EmitArithmetic3XMM(instruction, InstructionSet.opSUBSS, InstructionSet.opSUBSD)
  1098. END;
  1099. ELSE EmitArithmetic3Part(instruction,Low,InstructionSet.opSUB);
  1100. IF IsComplex(instruction.op1) THEN EmitArithmetic3Part(instruction, High, InstructionSet.opSBB) END;
  1101. END;
  1102. |IntermediateCode.add:
  1103. IF IsFloat(instruction.op1) THEN
  1104. IF backend.forceFPU THEN
  1105. EmitArithmetic3FPU(instruction,InstructionSet.opFADD)
  1106. ELSE
  1107. EmitArithmetic3XMM(instruction, InstructionSet.opADDSS, InstructionSet.opADDSD)
  1108. END;
  1109. ELSE EmitArithmetic3Part(instruction,Low,InstructionSet.opADD);
  1110. IF IsComplex(instruction.op1) THEN EmitArithmetic3Part(instruction, High, InstructionSet.opADC) END;
  1111. END;
  1112. |IntermediateCode.and:
  1113. Assert(~IsFloat(instruction.op1),"operation not defined on float");
  1114. EmitArithmetic3(instruction,InstructionSet.opAND);
  1115. |IntermediateCode.or:
  1116. Assert(~IsFloat(instruction.op1),"operation not defined on float");
  1117. EmitArithmetic3(instruction,InstructionSet.opOR);
  1118. |IntermediateCode.xor:
  1119. Assert(~IsFloat(instruction.op1),"operation not defined on float");
  1120. EmitArithmetic3(instruction,InstructionSet.opXOR);
  1121. |IntermediateCode.shl: EmitShift(instruction);
  1122. |IntermediateCode.shr: EmitShift(instruction);
  1123. |IntermediateCode.rol: EmitShift(instruction);
  1124. |IntermediateCode.ror: EmitShift(instruction);
  1125. |IntermediateCode.cas: EmitCas(instruction);
  1126. |IntermediateCode.copy: EmitCopy(instruction);
  1127. |IntermediateCode.fill: EmitFill(instruction,FALSE);
  1128. |IntermediateCode.asm: EmitAsm(instruction);
  1129. END;
  1130. ReserveOperandRegisters(instruction.op3,FALSE); ReserveOperandRegisters(instruction.op2,FALSE); ReserveOperandRegisters(instruction.op1,FALSE);
  1131. END Generate;
  1132. PROCEDURE PostGenerate(CONST instruction: IntermediateCode.Instruction);
  1133. VAR ticket: Ticket;
  1134. BEGIN
  1135. TryUnmap(instruction.op3); TryUnmap(instruction.op2); TryUnmap(instruction.op1);
  1136. ticket := tickets.live;
  1137. WHILE (ticket # NIL) & (ticket.lastuse = inPC) DO
  1138. UnmapTicket(ticket);
  1139. ticket := tickets.live
  1140. END;
  1141. END PostGenerate;
  1142. (* enter procedure: generate PAF and clear stack *)
  1143. PROCEDURE EmitEnter(CONST instruction: IntermediateCode.Instruction);
  1144. VAR op1,imm,target: Assembler.Operand; cc,size,numberMachineWords,destPC,firstPC,secondPC,x: LONGINT; body: SyntaxTree.Body; name: Basic.SegmentedName;
  1145. parametersSize: SIZE;
  1146. CONST initialize=TRUE; FirstOffset = 5; SecondOffset = 11;
  1147. BEGIN
  1148. stackSize := SHORT(instruction.op2.intValue);
  1149. size := stackSize;
  1150. INC(traceStackSize, stackSize);
  1151. IF initialize THEN
  1152. (* always including this instruction make trace insertion possible *)
  1153. IF backend.traceable THEN
  1154. emitter.Emit2(InstructionSet.opXOR,opRA,opRA);
  1155. END;
  1156. ASSERT(size MOD opRA.sizeInBytes = 0);
  1157. numberMachineWords := size DIV opRA.sizeInBytes;
  1158. IF numberMachineWords >0 THEN
  1159. IF ~backend.traceable THEN
  1160. emitter.Emit2(InstructionSet.opXOR,opRA,opRA);
  1161. END;
  1162. WHILE numberMachineWords MOD 4 # 0 DO
  1163. emitter.Emit1(InstructionSet.opPUSH, opRA);
  1164. DEC(numberMachineWords);
  1165. END;
  1166. IF numberMachineWords >4 THEN
  1167. Assembler.InitImm(imm, 0, numberMachineWords DIV 4);
  1168. (* do not use EBX because it is not volative in WINAPI, do not use ECX: special register in COOP *)
  1169. emitter.Emit2(InstructionSet.opMOV, opRD, imm);
  1170. destPC := out.pc;
  1171. emitter.Emit1(InstructionSet.opDEC, opRD);
  1172. emitter.Emit1(InstructionSet.opPUSH, opRA);
  1173. emitter.Emit1(InstructionSet.opPUSH, opRA);
  1174. emitter.Emit1(InstructionSet.opPUSH, opRA);
  1175. emitter.Emit1(InstructionSet.opPUSH, opRA);
  1176. Assembler.InitOffset8(target,destPC);
  1177. emitter.Emit1(InstructionSet.opJNZ, target)
  1178. ELSE
  1179. WHILE numberMachineWords >0 DO
  1180. emitter.Emit1(InstructionSet.opPUSH, opRA);
  1181. DEC(numberMachineWords);
  1182. END;
  1183. END;
  1184. END;
  1185. IF spillStack.MaxSize()>0 THEN (* register spill stack, does not have to be initialized *)
  1186. op1 := Assembler.NewImm32(spillStack.MaxSize()*cpuBits DIV 8);
  1187. emitter.Emit2(InstructionSet.opSUB,opSP,op1);
  1188. END;
  1189. ELSE
  1190. op1 := Assembler.NewImm32(size+ spillStack.MaxSize());
  1191. emitter.Emit2(InstructionSet.opSUB,opSP,op1);
  1192. END;
  1193. cc := SHORT(instruction.op1.intValue);
  1194. IF (cc = SyntaxTree.WinAPICallingConvention) OR (cc = SyntaxTree.CCallingConvention) THEN
  1195. IF cpuBits = 32 THEN
  1196. (* the winapi calling convention presumes that all registers except EAX, EDX and ECX are retained by the callee *)
  1197. emitter.Emit1(InstructionSet.opPUSH,opEBX);
  1198. emitter.Emit1(InstructionSet.opPUSH,opEDI);
  1199. emitter.Emit1(InstructionSet.opPUSH,opESI);
  1200. ELSE ASSERT(cpuBits =64);
  1201. emitter.Emit1(InstructionSet.opPUSH,opRB);
  1202. emitter.Emit1(InstructionSet.opPUSH,opRDI);
  1203. emitter.Emit1(InstructionSet.opPUSH,opRSI);
  1204. emitter.Emit1(InstructionSet.opPUSH,opR12);
  1205. emitter.Emit1(InstructionSet.opPUSH,opR13);
  1206. emitter.Emit1(InstructionSet.opPUSH,opR14);
  1207. emitter.Emit1(InstructionSet.opPUSH,opR15);
  1208. END;
  1209. END;
  1210. spillStackStart := stackSize;
  1211. END EmitEnter;
  1212. PROCEDURE EmitLeave(CONST instruction: IntermediateCode.Instruction);
  1213. VAR cc: LONGINT; offset: Assembler.Operand;
  1214. BEGIN
  1215. cc := SHORT(instruction.op1.intValue);
  1216. IF (cc = SyntaxTree.WinAPICallingConvention) OR (cc = SyntaxTree.CCallingConvention) THEN
  1217. IF cpuBits = 32 THEN
  1218. emitter.Emit1(InstructionSet.opPOP,opESI);
  1219. emitter.Emit1(InstructionSet.opPOP,opEDI);
  1220. emitter.Emit1(InstructionSet.opPOP,opEBX);
  1221. ELSE ASSERT(cpuBits =64);
  1222. emitter.Emit1(InstructionSet.opPOP,opR15);
  1223. emitter.Emit1(InstructionSet.opPOP,opR14);
  1224. emitter.Emit1(InstructionSet.opPOP,opR13);
  1225. emitter.Emit1(InstructionSet.opPOP,opR12);
  1226. emitter.Emit1(InstructionSet.opPOP,opRSI);
  1227. emitter.Emit1(InstructionSet.opPOP,opRDI);
  1228. emitter.Emit1(InstructionSet.opPOP,opRB);
  1229. END;
  1230. END;
  1231. END EmitLeave;
  1232. PROCEDURE EmitExit(CONST instruction: IntermediateCode.Instruction);
  1233. VAR parSize,cc: LONGINT; operand: Assembler.Operand;
  1234. BEGIN
  1235. cc := SHORT(instruction.op2.intValue);
  1236. parSize := SHORT(instruction.op3.intValue);
  1237. IF (parSize = 0) OR (cc = SyntaxTree.WinAPICallingConvention) & (cpuBits = 64) THEN
  1238. emitter.Emit0(InstructionSet.opRET)
  1239. ELSE (* e.g. for WINAPI calling convention *)
  1240. operand := Assembler.NewImm16(parSize);
  1241. emitter.Emit1(InstructionSet.opRET,operand)
  1242. END;
  1243. IF fpStackPointer # 0 THEN Error(instruction.textPosition,"compiler implementation error: fp stack not cleared") END;
  1244. END EmitExit;
  1245. PROCEDURE EmitReturnFPU(CONST instruction: IntermediateCode.Instruction);
  1246. VAR operand: Assembler.Operand;
  1247. BEGIN
  1248. IF IsRegister(instruction.op1) & MappedTo(instruction.op1.register,Low, ST0) THEN
  1249. (* nothing to do: result is already in return register *)
  1250. ELSE
  1251. MakeOperand(instruction.op1, Low, operand,NIL);
  1252. emitter.Emit1(InstructionSet.opFLD,operand);
  1253. (*
  1254. not necessary to clear from top of stack as callee will clear
  1255. INC(fpStackPointer);
  1256. emitter.Emit1(InstructionSet.opFSTP,registerOperands[ST0+1]);
  1257. DEC(fpStackPointer);
  1258. *)
  1259. END;
  1260. END EmitReturnFPU;
  1261. (* return operand
  1262. store operand in return register or on fp stack
  1263. *)
  1264. PROCEDURE EmitReturn(CONST instruction: IntermediateCode.Instruction; part: LONGINT);
  1265. VAR return,operand: Assembler.Operand; register: LONGINT; ticket: Ticket; type: IntermediateCode.Type;
  1266. BEGIN
  1267. register := ResultRegister(instruction.op1.type, part);
  1268. IF IsRegister(instruction.op1) & MappedTo(instruction.op1.register,part, register) THEN
  1269. (* nothing to do: result is already in return register *)
  1270. ELSE
  1271. GetPartType(instruction.op1.type,part, type);
  1272. MakeOperand(instruction.op1, part, operand,NIL);
  1273. Spill(physicalRegisters.Mapped(register));
  1274. ticket := ReservePhysicalRegister(IntermediateCode.GeneralPurposeRegister,type,register,inPC);
  1275. TicketToOperand(ticket, return);
  1276. (* Mov takes care of potential register overlaps *)
  1277. Move(return, operand, type);
  1278. UnmapTicket(ticket);
  1279. END;
  1280. END EmitReturn;
  1281. PROCEDURE EmitMovFloat(CONST vdest,vsrc:IntermediateCode.Operand);
  1282. VAR dest,src, espm: Assembler.Operand; sizeInBytes: SHORTINT; vcopy: IntermediateCode.Operand;
  1283. BEGIN
  1284. sizeInBytes := SHORTINT(vdest.type.sizeInBits DIV 8);
  1285. IF vdest.type.form IN IntermediateCode.Integer THEN
  1286. (* e.g. in SYSTEM.VAL(LONGINT, r) *)
  1287. IF vsrc.mode = IntermediateCode.ModeMemory THEN
  1288. vcopy := vsrc; IntermediateCode.SetType(vcopy,vdest.type);
  1289. EmitMov(vdest, vcopy,Low);
  1290. IF IsComplex(vdest) THEN
  1291. EmitMov(vdest,vcopy,High);
  1292. END;
  1293. ELSE
  1294. IF backend.forceFPU THEN
  1295. MakeOperand(vsrc,Low,src,NIL);
  1296. emitter.Emit1(InstructionSet.opFLD,src);
  1297. INC(fpStackPointer);
  1298. IF vdest.mode = IntermediateCode.ModeMemory THEN
  1299. MakeOperand(vdest,Low,dest,NIL);
  1300. Assembler.SetSize(dest,sizeInBytes);
  1301. emitter.Emit1(InstructionSet.opFSTP,dest);
  1302. DEC(fpStackPointer);
  1303. ELSE
  1304. AllocateStack(sizeInBytes);
  1305. Assembler.InitMem(espm, sizeInBytes,SP,0);
  1306. emitter.Emit1(InstructionSet.opFSTP,espm);
  1307. DEC(fpStackPointer);
  1308. MakeOperand(vdest,Low,dest,NIL);
  1309. EmitPop(vdest,Low);
  1310. IF IsComplex(vdest) THEN
  1311. EmitPop(vdest,High);
  1312. END;
  1313. END;
  1314. ELSE
  1315. MakeOperand(vsrc, Low, src, NIL);
  1316. IF vdest.mode = IntermediateCode.ModeMemory THEN
  1317. MakeOperand(vdest, Low, dest, NIL);
  1318. Move(dest, src, vsrc.type);
  1319. ELSE (* need temporary stack argument *)
  1320. AllocateStack(sizeInBytes);
  1321. Assembler.InitMem(espm, sizeInBytes,SP,0);
  1322. Move(espm, src, vsrc.type);
  1323. MakeOperand(vdest,Low,dest,NIL);
  1324. EmitPop(vdest,Low);
  1325. IF IsComplex(vdest) THEN
  1326. EmitPop(vdest,High);
  1327. END;
  1328. END;
  1329. END;
  1330. END;
  1331. ELSIF vsrc.type.form IN IntermediateCode.Integer THEN
  1332. (* e.g. in SYSTEM.VAL(REAL, i) *)
  1333. IF vdest.mode = IntermediateCode.ModeMemory THEN
  1334. vcopy := vdest; IntermediateCode.SetType(vcopy,vsrc.type);
  1335. EmitMov(vcopy, vsrc,Low);
  1336. IF IsComplex(vsrc) THEN
  1337. EmitMov(vcopy,vsrc,High);
  1338. END;
  1339. ELSE
  1340. IF backend.forceFPU THEN
  1341. IF vsrc.mode = IntermediateCode.ModeMemory THEN
  1342. MakeOperand(vsrc,Low,src,NIL);
  1343. Assembler.SetSize(src,sizeInBytes);
  1344. emitter.Emit1(InstructionSet.opFLD,src);
  1345. ELSE
  1346. IF IsComplex(vsrc) THEN
  1347. EmitPush(vsrc,High);
  1348. END;
  1349. EmitPush(vsrc,Low);
  1350. Assembler.InitMem(espm, sizeInBytes,SP,0);
  1351. emitter.Emit1(InstructionSet.opFLD,espm);
  1352. ASSERT(sizeInBytes >0);
  1353. AllocateStack(-sizeInBytes);
  1354. END;
  1355. INC(fpStackPointer);
  1356. MakeOperand(vdest,Low,dest,NIL);
  1357. emitter.Emit1(InstructionSet.opFSTP,dest);
  1358. DEC(fpStackPointer);
  1359. ELSE
  1360. IF vsrc.mode = IntermediateCode.ModeMemory THEN
  1361. MakeOperand(vsrc,Low,src,NIL);
  1362. Assembler.SetSize(src,sizeInBytes);
  1363. MakeOperand(vdest,Low,dest,NIL);
  1364. Move(dest, src, vdest.type);
  1365. ELSE
  1366. IF IsComplex(vsrc) THEN
  1367. EmitPush(vsrc,High);
  1368. END;
  1369. EmitPush(vsrc,Low);
  1370. Assembler.InitMem(espm, sizeInBytes,SP,0);
  1371. MakeOperand(vdest, Low, dest, NIL);
  1372. Move(dest, espm, vdest.type);
  1373. AllocateStack(-sizeInBytes);
  1374. END;
  1375. END;
  1376. END;
  1377. ELSE
  1378. IF backend.forceFPU THEN
  1379. MakeOperand(vsrc,Low,src,NIL);
  1380. emitter.Emit1(InstructionSet.opFLD,src);
  1381. INC(fpStackPointer);
  1382. MakeOperand(vdest,Low,dest,NIL);
  1383. emitter.Emit1(InstructionSet.opFSTP,dest);
  1384. DEC(fpStackPointer);
  1385. ELSE
  1386. MakeOperand(vsrc, Low, src, NIL);
  1387. MakeOperand(vdest, Low, dest, NIL);
  1388. Move(dest, src, vdest.type)
  1389. END;
  1390. END;
  1391. END EmitMovFloat;
  1392. PROCEDURE EmitMov(CONST vdest,vsrc: IntermediateCode.Operand; part: LONGINT);
  1393. VAR op1,op2: Assembler.Operand; tmp: IntermediateCode.Operand;
  1394. t: CodeGenerators.Ticket;
  1395. type: IntermediateCode.Type;
  1396. offset: LONGINT;
  1397. BEGIN
  1398. IF (vdest.mode = IntermediateCode.ModeRegister) & (vsrc.mode = IntermediateCode.ModeRegister) & (vsrc.type.sizeInBits > 8) & (vsrc.offset # 0)THEN
  1399. (* MOV R1, R2+offset => LEA EAX, [EBX+offset] *)
  1400. tmp := vsrc;
  1401. IntermediateCode.MakeMemory(tmp,vsrc.type);
  1402. MakeOperand(tmp,part,op2,NIL);
  1403. (*
  1404. ReleaseHint(op2.register);
  1405. *)
  1406. MakeOperand(vdest,part,op1,NIL);
  1407. t := virtualRegisters.Mapped(vdest.register,part);
  1408. IF (t # NIL) & (t.spilled) THEN
  1409. UnSpill(t); (* make sure this has not spilled *)
  1410. MakeOperand(vdest,part, op1,NIL);
  1411. END;
  1412. emitter.Emit2(InstructionSet.opLEA,op1,op2);
  1413. ELSE
  1414. MakeOperand(vsrc,part,op2,NIL);
  1415. MakeOperand(vdest,part,op1,NIL);
  1416. GetPartType(vsrc.type, part, type);
  1417. Move(op1,op2, type);
  1418. END;
  1419. END EmitMov;
  1420. PROCEDURE EmitConvertFloat(CONST instruction: IntermediateCode.Instruction);
  1421. VAR destType, srcType, dtype: IntermediateCode.Type; dest,src,espm,imm: Assembler.Operand; sizeInBytes, index: LONGINT;
  1422. temp, temp2, temp3, temp4: Assembler.Operand; ticket: Ticket; vdest, vsrc: IntermediateCode.Operand;
  1423. BEGIN
  1424. vdest := instruction.op1; vsrc := instruction.op2;
  1425. srcType := vsrc.type;
  1426. destType := vdest.type;
  1427. IF destType.form = IntermediateCode.Float THEN
  1428. CASE srcType.form OF
  1429. |IntermediateCode.Float: (* just a move *)
  1430. IF backend.forceFPU THEN
  1431. EmitMovFloat(vdest, vsrc);
  1432. ELSE
  1433. MakeOperand(vsrc,Low,src,NIL);
  1434. MakeOperand(vdest, Low, dest, NIL);
  1435. IF srcType.sizeInBits = 32 THEN
  1436. SpecialMove(InstructionSet.opCVTSS2SD, InstructionSet.opMOVSS, FALSE, dest, src, destType)
  1437. ELSE
  1438. SpecialMove(InstructionSet.opCVTSD2SS, InstructionSet.opMOVSD, FALSE, dest, src, destType)
  1439. END;
  1440. END;
  1441. |IntermediateCode.SignedInteger:
  1442. (* put value to stack and then read from stack via Float *)
  1443. IF vsrc.type.sizeInBits < IntermediateCode.Bits32 THEN
  1444. MakeOperand(vsrc,Low,src,NIL);
  1445. ticket := TemporaryTicket(IntermediateCode.GeneralPurposeRegister,IntermediateCode.int32);
  1446. TicketToOperand(ticket,temp);
  1447. emitter.Emit2(InstructionSet.opMOVSX,temp,src);
  1448. IF backend.forceFPU THEN (* via stack *)
  1449. emitter.Emit1(InstructionSet.opPUSH,temp);
  1450. UnmapTicket(ticket);
  1451. sizeInBytes := temp.sizeInBytes;
  1452. ELSE (* via register *)
  1453. espm := temp;
  1454. sizeInBytes := 0
  1455. END;
  1456. ELSIF IsComplex(vsrc) THEN (* via stack *)
  1457. EmitPush(vsrc,High);
  1458. EmitPush(vsrc,Low);
  1459. sizeInBytes := 8
  1460. ELSE
  1461. IF backend.forceFPU THEN (* via stack *)
  1462. EmitPush(vsrc,Low);
  1463. sizeInBytes := SHORTINT(4 (* cpuBits DIV 8*)) (*SHORT(srcType.sizeInBits DIV 8)*);
  1464. ELSE (* via memory or register *)
  1465. sizeInBytes := 0;
  1466. MakeOperand(vsrc,Low,src,NIL);
  1467. IF Assembler.IsImmediateOperand(src) THEN (* use temporary register *)
  1468. ticket := TemporaryTicket(IntermediateCode.GeneralPurposeRegister,IntermediateCode.int32);
  1469. TicketToOperand(ticket,temp);
  1470. emitter.Emit2(InstructionSet.opMOVSX,temp,src);
  1471. espm := temp
  1472. ELSE
  1473. espm := src
  1474. END;
  1475. END
  1476. END;
  1477. IF sizeInBytes > 0 THEN
  1478. Assembler.InitMem(espm, SHORTINT(sizeInBytes),SP,0);
  1479. END;
  1480. IF backend.forceFPU THEN
  1481. emitter.Emit1(InstructionSet.opFILD,espm);
  1482. INC(fpStackPointer);
  1483. ASSERT(sizeInBytes >0);
  1484. Basic.Align(sizeInBytes, 4 (* cpuBits DIV 8*));
  1485. AllocateStack(-sizeInBytes);
  1486. MakeOperand(vdest,Low,dest,NIL);
  1487. emitter.Emit1(InstructionSet.opFSTP,dest);
  1488. DEC(fpStackPointer);
  1489. ELSIF IsComplex(vsrc) THEN
  1490. emitter.Emit1(InstructionSet.opFILD,espm);
  1491. MakeOperand(vdest,Low,dest,NIL);
  1492. IF Assembler.IsMemoryOperand(dest) THEN
  1493. emitter.Emit1(InstructionSet.opFSTP,dest);
  1494. ELSE (* must be register *)
  1495. emitter.Emit1(InstructionSet.opFSTP,espm);
  1496. emitter.Emit2(InstructionSet.opMOVQ,dest,espm);
  1497. IF destType.sizeInBits = 32 THEN
  1498. emitter.Emit2(InstructionSet.opCVTSD2SS, dest,dest);
  1499. END;
  1500. END;
  1501. AllocateStack(-sizeInBytes);
  1502. ELSE
  1503. MakeOperand(vdest,Low,dest,NIL);
  1504. IF destType.sizeInBits = 32 THEN
  1505. emitter.Emit2(InstructionSet.opCVTSI2SS, dest, espm)
  1506. ELSE
  1507. emitter.Emit2(InstructionSet.opCVTSI2SD, dest, espm)
  1508. END;
  1509. AllocateStack(-sizeInBytes);
  1510. END;
  1511. END;
  1512. ELSE
  1513. ASSERT(destType.form IN IntermediateCode.Integer);
  1514. ASSERT(srcType.form = IntermediateCode.Float);
  1515. Assert(vdest.type.form = IntermediateCode.SignedInteger, "no entier as result for unsigned integer");
  1516. MakeOperand(vsrc,Low,src,NIL);
  1517. IF ~backend.forceFPU THEN
  1518. MakeOperand(vdest,Low,dest,ticket);
  1519. GetTemporaryRegister(srcType, temp);
  1520. GetTemporaryRegister(srcType, temp3);
  1521. IF destType.sizeInBits < 32 THEN
  1522. IntermediateCode.InitType(dtype, destType.form, 32);
  1523. GetTemporaryRegister(dtype, temp4);
  1524. ELSE
  1525. dtype := destType;
  1526. temp4 := dest;
  1527. END;
  1528. GetTemporaryRegister(dtype, temp2);
  1529. IF srcType.sizeInBits = 32 THEN
  1530. (* convert truncated -> negative numbers round up !*)
  1531. emitter.Emit2(InstructionSet.opCVTTSS2SI, temp4, src);
  1532. (* back to temporary mmx register *)
  1533. emitter.Emit2(InstructionSet.opCVTSI2SS, temp, temp4);
  1534. (* subtract *)
  1535. emitter.Emit2(InstructionSet.opMOVSS, temp3, src);
  1536. emitter.Emit2(InstructionSet.opSUBSS, temp3, temp);
  1537. (* back to a GP register in order to determine the sign bit *)
  1538. ELSE
  1539. emitter.Emit2(InstructionSet.opCVTTSD2SI, temp4, src);
  1540. emitter.Emit2(InstructionSet.opCVTSI2SD, temp, temp4);
  1541. emitter.Emit2(InstructionSet.opMOVSD, temp3, src);
  1542. emitter.Emit2(InstructionSet.opSUBSD, temp3, temp);
  1543. emitter.Emit2(InstructionSet.opCVTSD2SS, temp3, temp3);
  1544. END;
  1545. emitter.Emit2(InstructionSet.opMOVD, temp2, temp3);
  1546. Assembler.InitImm(imm, 0 ,srcType.sizeInBits-1);
  1547. emitter.Emit2(InstructionSet.opBT, temp2, imm);
  1548. Assembler.InitImm(imm, 0 ,0);
  1549. emitter.Emit2(InstructionSet.opSBB, temp4, imm);
  1550. IF dtype.sizeInBits # destType.sizeInBits THEN
  1551. index := temp4.register;
  1552. CASE destType.sizeInBits OF (* choose low part accordingly *)
  1553. IntermediateCode.Bits8: index := index MOD 32 + AL;
  1554. |IntermediateCode.Bits16: index := index MOD 32 + AX;
  1555. |IntermediateCode.Bits32: index := index MOD 32 + EAX;
  1556. END;
  1557. temp4 := registerOperands[index];
  1558. emitter.Emit2(InstructionSet.opMOV, dest, temp4);
  1559. END
  1560. ELSE
  1561. emitter.Emit1(InstructionSet.opFLD,src); INC(fpStackPointer);
  1562. MakeOperand(vdest,Low,dest,NIL);
  1563. IF destType.sizeInBits = IntermediateCode.Bits64 THEN AllocateStack(12) ELSE AllocateStack(8) END;
  1564. Assembler.InitMem(espm,IntermediateCode.Bits16 DIV 8,SP,0);
  1565. emitter.Emit1(InstructionSet.opFNSTCW,espm);
  1566. emitter.Emit0(InstructionSet.opFWAIT);
  1567. Assembler.InitMem(espm,IntermediateCode.Bits32 DIV 8,SP,0);
  1568. ticket := TemporaryTicket(IntermediateCode.GeneralPurposeRegister,IntermediateCode.int32);
  1569. TicketToOperand(ticket,temp);
  1570. emitter.Emit2(InstructionSet.opMOV,temp,espm);
  1571. imm := Assembler.NewImm32(0F3FFH);
  1572. emitter.Emit2(InstructionSet.opAND,temp,imm);
  1573. imm := Assembler.NewImm32(0400H);
  1574. emitter.Emit2(InstructionSet.opOR,temp,imm);
  1575. Assembler.InitMem(espm,IntermediateCode.Bits32 DIV 8,SP,4);
  1576. emitter.Emit2(InstructionSet.opMOV,espm,temp);
  1577. Assembler.InitMem(espm,IntermediateCode.Bits16 DIV 8,SP,4);
  1578. emitter.Emit1(InstructionSet.opFLDCW,espm);
  1579. IF destType.sizeInBits = IntermediateCode.Bits64 THEN
  1580. Assembler.InitMem(espm,IntermediateCode.Bits64 DIV 8,SP,4);
  1581. emitter.Emit1(InstructionSet.opFISTP,espm);DEC(fpStackPointer);
  1582. emitter.Emit0(InstructionSet.opFWAIT);
  1583. ELSE
  1584. Assembler.InitMem(espm,IntermediateCode.Bits32 DIV 8,SP,4);
  1585. emitter.Emit1(InstructionSet.opFISTP,espm); DEC(fpStackPointer);
  1586. emitter.Emit0(InstructionSet.opFWAIT);
  1587. END;
  1588. Assembler.InitMem(espm,IntermediateCode.Bits16 DIV 8,SP,0);
  1589. emitter.Emit1(InstructionSet.opFLDCW,espm);
  1590. emitter.Emit1(InstructionSet.opPOP,temp);
  1591. UnmapTicket(ticket);
  1592. emitter.Emit1(InstructionSet.opPOP,dest);
  1593. IF IsComplex(vdest) THEN
  1594. MakeOperand(vdest,High,dest,NIL);
  1595. emitter.Emit1(InstructionSet.opPOP,dest);
  1596. END;
  1597. END;
  1598. END;
  1599. END EmitConvertFloat;
  1600. PROCEDURE EmitConvert(CONST vdest, vsrc: IntermediateCode.Operand; part: LONGINT);
  1601. VAR destType, srcType: IntermediateCode.Type; op1,op2: Assembler.Operand; index: LONGINT; nul: Assembler.Operand;
  1602. ticket: Ticket; vop: IntermediateCode.Operand; ediReserved, esiReserved: BOOLEAN;
  1603. eax, edx: Ticket; symbol: ObjectFile.Identifier; offset: LONGINT;
  1604. BEGIN
  1605. GetPartType(vdest.type,part, destType);
  1606. GetPartType(vsrc.type,part,srcType);
  1607. ASSERT(vdest.type.form IN IntermediateCode.Integer);
  1608. ASSERT(destType.form IN IntermediateCode.Integer);
  1609. IF destType.sizeInBits < srcType.sizeInBits THEN (* SHORT *)
  1610. ASSERT(part # High);
  1611. MakeOperand(vdest,part,op1,NIL);
  1612. IF vsrc.mode = IntermediateCode.ModeImmediate THEN
  1613. vop := vsrc;
  1614. IntermediateCode.SetType(vop,destType);
  1615. MakeOperand(vop,part,op2,NIL);
  1616. ELSE
  1617. MakeOperand(vsrc,part,op2,NIL);
  1618. IF Assembler.IsRegisterOperand(op1) & ((op1.register DIV 32 >0) (* not 8 bit register *) OR (op1.register DIV 16 = 0) & (physicalRegisters.Mapped(op1.register MOD 16 + AH)=free) (* low 8 bit register with free upper part *)) THEN
  1619. (* try EAX <- EDI for dest = AL or AX, src=EDI *)
  1620. index := op1.register;
  1621. CASE srcType.sizeInBits OF
  1622. IntermediateCode.Bits16: index := index MOD 32 + AX;
  1623. |IntermediateCode.Bits32: index := index MOD 32 + EAX;
  1624. |IntermediateCode.Bits64: index := index MOD 32 + RAX;
  1625. END;
  1626. op1 := registerOperands[index];
  1627. ELSE
  1628. (* reserve register with a low part *)
  1629. IF destType.sizeInBits=8 THEN (* make sure that allocated temporary register has a low part with 8 bits, i.e. exclude ESI or EDI *)
  1630. ediReserved := physicalRegisters.Reserved(EDI);
  1631. esiReserved := physicalRegisters.Reserved(ESI);
  1632. physicalRegisters.SetReserved(EDI,TRUE); physicalRegisters.SetReserved(ESI,TRUE);
  1633. ticket := TemporaryTicket(IntermediateCode.GeneralPurposeRegister,srcType); (* register with low part *)
  1634. physicalRegisters.SetReserved(EDI,ediReserved); physicalRegisters.SetReserved(ESI,esiReserved);
  1635. ELSE
  1636. ticket := TemporaryTicket(IntermediateCode.GeneralPurposeRegister,srcType); (* any register with low part *)
  1637. END;
  1638. MakeOperand(vsrc,part,op2,ticket); (* stores op2 in ticket register *)
  1639. index := op2.register;
  1640. CASE destType.sizeInBits OF (* choose low part accordingly *)
  1641. IntermediateCode.Bits8: index := index MOD 32 + AL;
  1642. |IntermediateCode.Bits16: index := index MOD 32 + AX;
  1643. |IntermediateCode.Bits32: index := index MOD 32 + EAX;
  1644. END;
  1645. op2 := registerOperands[index];
  1646. END;
  1647. Move(op1,op2,PhysicalOperandType(op1));
  1648. END;
  1649. ELSIF destType.sizeInBits > srcType.sizeInBits THEN (* (implicit) LONG *)
  1650. IF part = High THEN
  1651. IF destType.form = IntermediateCode.SignedInteger THEN
  1652. Spill(physicalRegisters.Mapped(EAX));
  1653. eax := ReservePhysicalRegister(IntermediateCode.GeneralPurposeRegister,IntermediateCode.int32,EAX,inPC);
  1654. Spill(physicalRegisters.Mapped(EDX));
  1655. edx := ReservePhysicalRegister(IntermediateCode.GeneralPurposeRegister,IntermediateCode.int32,EDX,inPC);
  1656. IF vsrc.type.sizeInBits < 32 THEN
  1657. MakeOperand(vsrc,Low,op2,NIL);
  1658. SpecialMove(InstructionSet.opMOVSX,InstructionSet.opMOV, FALSE, opEAX,op2,PhysicalOperandType(opEAX));
  1659. ELSE
  1660. MakeOperand(vsrc,Low,op2,eax);
  1661. END;
  1662. emitter.Emit0(InstructionSet.opCDQ);
  1663. MakeOperand(vdest,High,op1,NIL);
  1664. emitter.Emit2(InstructionSet.opMOV,op1,opEDX);
  1665. UnmapTicket(eax); UnmapTicket(edx);
  1666. ELSE
  1667. MakeOperand(vdest,part,op1,NIL);
  1668. IF (vdest.mode = IntermediateCode.ModeRegister) THEN
  1669. emitter.Emit2(InstructionSet.opXOR,op1,op1)
  1670. ELSE
  1671. Assembler.InitImm(nul,0,0);
  1672. emitter.Emit2(InstructionSet.opMOV,op1,nul);
  1673. END;
  1674. END;
  1675. ELSE
  1676. ASSERT(part=Low);
  1677. MakeOperand(vdest,part,op1,NIL);
  1678. MakeOperand(vsrc,part,op2,NIL);
  1679. IF srcType.sizeInBits = destType.sizeInBits THEN
  1680. Move(op1,op2,PhysicalOperandType(op1));
  1681. ELSIF srcType.form = IntermediateCode.SignedInteger THEN
  1682. IF srcType.sizeInBits=32 THEN (* 64 bits only *)
  1683. ASSERT(cpuBits=64);
  1684. SpecialMove(InstructionSet.opMOVSXD,InstructionSet.opMOV, FALSE, op1,op2,PhysicalOperandType(op1));
  1685. ELSE
  1686. SpecialMove(InstructionSet.opMOVSX,InstructionSet.opMOV, FALSE, op1,op2,PhysicalOperandType(op1));
  1687. END;
  1688. ELSE
  1689. ASSERT(srcType.form = IntermediateCode.UnsignedInteger);
  1690. IF srcType.sizeInBits=32 THEN (* 64 bits only *)
  1691. ASSERT(cpuBits=64);
  1692. IF Assembler.IsRegisterOperand(op1) THEN
  1693. Move( registerOperands[op1.register MOD 32 + EAX], op2,srcType);
  1694. ELSE
  1695. ASSERT(Assembler.IsMemoryOperand(op1));
  1696. symbol := op1.symbol; offset := op1.offset;
  1697. Assembler.InitMem(op1,Assembler.bits32,op1.register, op1.displacement);
  1698. Assembler.SetSymbol(op1,symbol.name,symbol.fingerprint,offset,op1.displacement);
  1699. Move( op1, op2, srcType);
  1700. Assembler.InitMem(op1,Assembler.bits32,op1.register, op1.displacement+Assembler.bits32);
  1701. Assembler.SetSymbol(op1,symbol.name, symbol.fingerprint,offset,op1.displacement);
  1702. Assembler.InitImm(op2,0,0);
  1703. Move( op1, op2,srcType);
  1704. END;
  1705. ELSE
  1706. SpecialMove(InstructionSet.opMOVZX, InstructionSet.opMOV, FALSE, op1, op2,PhysicalOperandType(op1))
  1707. END;
  1708. END;
  1709. END;
  1710. ELSE (* destType.sizeInBits = srcType.sizeInBits) *)
  1711. EmitMov(vdest,vsrc,part);
  1712. END;
  1713. END EmitConvert;
  1714. PROCEDURE EmitResult(CONST instruction: IntermediateCode.Instruction);
  1715. VAR result, resultHigh, op, opHigh: Assembler.Operand; register, highRegister: LONGINT; lowReserved, highReserved: BOOLEAN; type: IntermediateCode.Type;
  1716. BEGIN
  1717. IF ~IsComplex(instruction.op1) THEN
  1718. register := ResultRegister(instruction.op1.type,Low);
  1719. result := registerOperands[register];
  1720. MakeOperand(instruction.op1,Low,op,NIL);
  1721. GetPartType(instruction.op1.type, Low, type);
  1722. Move(op,result,type);
  1723. ELSE
  1724. register := ResultRegister(instruction.op1.type,Low);
  1725. result := registerOperands[register];
  1726. highRegister := ResultRegister(instruction.op1.type, High);
  1727. resultHigh := registerOperands[highRegister];
  1728. (* make sure that result registers are not used during emission of Low / High *)
  1729. lowReserved := physicalRegisters.Reserved(register);
  1730. physicalRegisters.SetReserved(register, TRUE);
  1731. highReserved := physicalRegisters.Reserved(highRegister);
  1732. physicalRegisters.SetReserved(highRegister,TRUE);
  1733. MakeOperand(instruction.op1,Low,op, NIL);
  1734. IF Assembler.SameOperand(op, resultHigh) THEN
  1735. emitter.Emit2(InstructionSet.opXCHG, result, resultHigh); (* low register already mapped ok *)
  1736. MakeOperand(instruction.op1, High, opHigh, NIL);
  1737. GetPartType(instruction.op1.type, High, type);
  1738. Move(opHigh, result, type);
  1739. ELSE
  1740. GetPartType(instruction.op1.type, Low, type);
  1741. Move(op, result, type);
  1742. MakeOperand(instruction.op1,High, opHigh, NIL);
  1743. GetPartType(instruction.op1.type, High, type);
  1744. Move(opHigh, resultHigh, type);
  1745. END;
  1746. physicalRegisters.SetReserved(register, lowReserved);
  1747. physicalRegisters.SetReserved(highRegister, highReserved);
  1748. END;
  1749. END EmitResult;
  1750. PROCEDURE EmitResultFPU(CONST instruction: IntermediateCode.Instruction);
  1751. VAR op: Assembler.Operand;
  1752. BEGIN
  1753. INC(fpStackPointer); (* callee has left the result on top of stack, don't have to allocate here *)
  1754. MakeOperand(instruction.op1,Low,op,NIL);
  1755. emitter.Emit1(InstructionSet.opFSTP,op);
  1756. DEC(fpStackPointer);
  1757. (*
  1758. UnmapTicket(ticket);
  1759. *)
  1760. END EmitResultFPU;
  1761. PROCEDURE EmitCall(CONST instruction: IntermediateCode.Instruction);
  1762. VAR fixup: Sections.Section; target, op, parSize: Assembler.Operand;
  1763. code: SyntaxTree.Code; emitterFixup,newFixup: BinaryCode.Fixup; resolved: BinaryCode.Section; pc: LONGINT;
  1764. BEGIN
  1765. IF fpStackPointer # 0 THEN Error(instruction.textPosition,"compiler implementation error: fp stack not cleared before call") END;
  1766. IF instruction.op1.mode = IntermediateCode.ModeImmediate THEN
  1767. fixup := module.allSections.FindByName(instruction.op1.symbol.name);
  1768. IF (fixup # NIL) & (fixup.type = Sections.InlineCodeSection) THEN
  1769. pc := out.pc;
  1770. (* resolved must be available at this point ! *)
  1771. resolved := fixup(IntermediateCode.Section).resolved;
  1772. IF resolved # NIL THEN
  1773. emitter.code.CopyBits(resolved.os.bits,0,resolved.os.bits.GetSize());
  1774. emitterFixup := resolved.fixupList.firstFixup;
  1775. WHILE (emitterFixup # NIL) DO
  1776. newFixup := BinaryCode.NewFixup(emitterFixup.mode,emitterFixup.offset+pc,emitterFixup.symbol,emitterFixup.symbolOffset,emitterFixup.displacement,emitterFixup.scale,emitterFixup.pattern);
  1777. out.fixupList.AddFixup(newFixup);
  1778. emitterFixup := emitterFixup.nextFixup;
  1779. END;
  1780. END;
  1781. ELSE
  1782. Assembler.InitOffset32(target,instruction.op1.intValue);
  1783. Assembler.SetSymbol(target,instruction.op1.symbol.name,instruction.op1.symbol.fingerprint,instruction.op1.offset,0);
  1784. emitter.Emit1(InstructionSet.opCALL,target);
  1785. Assembler.InitOffset32(parSize,instruction.op2.intValue);
  1786. IF parSize.val # 0 THEN emitter.Emit2(InstructionSet.opADD,opSP,parSize) END;
  1787. END;
  1788. ELSE
  1789. MakeOperand(instruction.op1,Low,op,NIL);
  1790. emitter.Emit1(InstructionSet.opCALL,op);
  1791. Assembler.InitOffset32(parSize,instruction.op2.intValue);
  1792. IF parSize.val # 0 THEN emitter.Emit2(InstructionSet.opADD,opSP,parSize) END;
  1793. END;
  1794. END EmitCall;
  1795. (*
  1796. register allocation
  1797. instruction dest, src1, src2
  1798. preconditions
  1799. dest is memory operand or dest is register with offset = 0
  1800. src1 and src2 may be immediates, registers with or without offset and memory operands
  1801. 1.) translation into two-operand code
  1802. a) dest = src1 (no assumption on src2, src2=src1 is permitted )
  1803. i) dest and src2 are both memory operands or src2 is a register with offset # 0
  1804. alloc temp register
  1805. mov temp, src2
  1806. instruction2 dest, temp
  1807. ii) dest or src2 is not a memory operand
  1808. instruction2 dest, src2
  1809. b) dest = src2
  1810. => src2 is not a register with offset # 0
  1811. alloc temp register
  1812. mov dest, src1
  1813. mov temp, src2
  1814. instruction2 dest, temp
  1815. c) dest # src2
  1816. mov dest, src1
  1817. i) dest and src2 are both memory operands or src2 is a register with offset # 0
  1818. allocate temp register
  1819. mov temp, src2
  1820. instruction2 dest, temp
  1821. ii)
  1822. instruction2 dest, src2
  1823. 1'.) translation into one operand code
  1824. instruction dest, src1
  1825. a) dest = src1
  1826. => src1 is not a register with offset # 0
  1827. instruction1 dest
  1828. b) dest # src1
  1829. mov dest, src1
  1830. instruction1 dest
  1831. 2.) register allocation
  1832. precondition: src1 and src2 are already allocated
  1833. a) dest is already allocated
  1834. go on according to 1.
  1835. b) dest needs to be allocated
  1836. check if register is free
  1837. i) yes: allocate free register and go on with 1.
  1838. ii) no: spill last register in livelist, map register and go on with 1.
  1839. *)
  1840. PROCEDURE PrepareOp3(CONST instruction: IntermediateCode.Instruction;part: LONGINT; VAR left, right: Assembler.Operand; VAR ticket: Ticket);
  1841. VAR vop1,vop2, vop3: IntermediateCode.Operand; op1,op2,op3,temp: Assembler.Operand; type: IntermediateCode.Type;
  1842. t: Ticket;
  1843. BEGIN
  1844. ticket := NIL;
  1845. GetPartType(instruction.op1.type,part,type);
  1846. vop1 := instruction.op1; vop2 := instruction.op2; vop3 := instruction.op3;
  1847. IF IntermediateCode.OperandEquals(vop1,vop3) & (IntermediateCode.Commute23 IN IntermediateCode.instructionFormat[instruction.opcode].flags) THEN
  1848. vop3 := instruction.op2; vop2 := instruction.op3;
  1849. END;
  1850. MakeOperand(vop3,part, op3,NIL);
  1851. IF (vop1.mode = IntermediateCode.ModeRegister) & (~IsMemoryOperand(vop1,part)) & (vop1.register # vop3.register) THEN
  1852. IF (vop2.mode = IntermediateCode.ModeRegister) & (vop2.register = vop1.register) & (vop2.offset = 0) THEN
  1853. (* same register *)
  1854. MakeOperand(vop1,part, op1,NIL);
  1855. ELSE
  1856. MakeOperand(vop2,part, op2,NIL);
  1857. (*
  1858. ReleaseHint(op2.register);
  1859. *)
  1860. MakeOperand(vop1,part, op1,NIL);
  1861. Move(op1, op2, type);
  1862. t := virtualRegisters.Mapped(vop1.register,part);
  1863. IF (t # NIL) & (t.spilled) THEN
  1864. UnSpill(t); (* make sure this has not spilled *)
  1865. MakeOperand(vop1,part, op1,NIL);
  1866. END;
  1867. END;
  1868. left := op1; right := op3;
  1869. ELSIF IntermediateCode.OperandEquals(vop1,vop2) & (~IsMemoryOperand(vop1,part) OR ~IsMemoryOperand(vop3,part)) THEN
  1870. MakeOperand(vop1,part, op1,NIL);
  1871. left := op1; right := op3;
  1872. ELSE
  1873. MakeOperand(vop1,part, op1,NIL);
  1874. MakeOperand(vop2,part, op2,NIL);
  1875. (*ReleaseHint(op2.register);*)
  1876. ticket := TemporaryTicket(IntermediateCode.GeneralPurposeRegister,type);
  1877. TicketToOperand(ticket,temp);
  1878. Move(temp, op2, type);
  1879. left := temp; right := op3;
  1880. END;
  1881. END PrepareOp3;
  1882. PROCEDURE PrepareOp2(CONST instruction: IntermediateCode.Instruction; part: LONGINT; VAR left: Assembler.Operand;VAR ticket: Ticket);
  1883. VAR op2: Assembler.Operand; imm: Assembler.Operand; sizeInBits: INTEGER; type: IntermediateCode.Type;
  1884. BEGIN
  1885. ticket := NIL;
  1886. GetPartType(instruction.op1.type,part,type);
  1887. IF (instruction.op1.mode = IntermediateCode.ModeRegister) THEN
  1888. MakeOperand(instruction.op1,part,left,NIL);
  1889. MakeOperand(instruction.op2,part,op2,NIL);
  1890. IF (instruction.op2.mode = IntermediateCode.ModeRegister) & (instruction.op2.register = instruction.op1.register) & (instruction.op2.offset = 0) THEN
  1891. ELSE
  1892. Move(left, op2, type);
  1893. IF (instruction.op2.offset # 0) & ~IsMemoryOperand(instruction.op2,part) THEN
  1894. GetPartType(instruction.op2.type,part,type);
  1895. sizeInBits := type.sizeInBits;
  1896. Assembler.InitImm(imm,0,instruction.op2.offset);
  1897. emitter.Emit2(InstructionSet.opADD,left,imm);
  1898. END;
  1899. END;
  1900. ELSIF IntermediateCode.OperandEquals(instruction.op1,instruction.op2) & ((instruction.op1.mode # IntermediateCode.ModeMemory) OR (instruction.op3.mode # IntermediateCode.ModeMemory)) THEN
  1901. MakeOperand(instruction.op1,part,left,NIL);
  1902. ELSE
  1903. MakeOperand(instruction.op2,part, op2,NIL);
  1904. ticket := TemporaryTicket(IntermediateCode.GeneralPurposeRegister,type);
  1905. TicketToOperand(ticket,left);
  1906. Move(left, op2, type);
  1907. END;
  1908. END PrepareOp2;
  1909. PROCEDURE FinishOp(CONST vop: IntermediateCode.Operand; part: LONGINT; left: Assembler.Operand; ticket: Ticket);
  1910. VAR op1: Assembler.Operand;
  1911. BEGIN
  1912. IF ticket # NIL THEN
  1913. MakeOperand(vop,part, op1,NIL);
  1914. Move(op1,left,vop.type);
  1915. UnmapTicket(ticket);
  1916. END;
  1917. END FinishOp;
  1918. PROCEDURE EmitArithmetic3Part(CONST instruction: IntermediateCode.Instruction; part: LONGINT; opcode: LONGINT);
  1919. VAR left,right: Assembler.Operand; ticket: Ticket;
  1920. BEGIN
  1921. PrepareOp3(instruction, part, left,right,ticket);
  1922. emitter.Emit2(opcode,left,right);
  1923. FinishOp(instruction.op1,part,left,ticket);
  1924. END EmitArithmetic3Part;
  1925. PROCEDURE EmitArithmetic3(CONST instruction: IntermediateCode.Instruction; opcode: LONGINT);
  1926. BEGIN
  1927. EmitArithmetic3Part(instruction,Low,opcode);
  1928. IF IsComplex(instruction.op1) THEN EmitArithmetic3Part(instruction, High, opcode) END;
  1929. END EmitArithmetic3;
  1930. PROCEDURE EmitArithmetic3XMM(CONST instruction: IntermediateCode.Instruction; op32, op64: LONGINT);
  1931. VAR op: LONGINT;
  1932. BEGIN
  1933. IF instruction.op1.type.sizeInBits = 32 THEN op := op32 ELSE op := op64 END;
  1934. EmitArithmetic3Part(instruction, Low, op);
  1935. END EmitArithmetic3XMM;
  1936. PROCEDURE EmitArithmetic2(CONST instruction: IntermediateCode.Instruction; part: LONGINT; opcode: LONGINT);
  1937. VAR left:Assembler.Operand;ticket: Ticket;
  1938. BEGIN
  1939. PrepareOp2(instruction,part,left,ticket);
  1940. emitter.Emit1(opcode,left);
  1941. FinishOp(instruction.op1,part,left,ticket);
  1942. END EmitArithmetic2;
  1943. PROCEDURE EmitArithmetic2XMM(CONST instruction: IntermediateCode.Instruction; op32, op64: LONGINT);
  1944. VAR op: LONGINT;
  1945. BEGIN
  1946. IF instruction.op1.type.sizeInBits = 32 THEN op := op32 ELSE op := op64 END;
  1947. EmitArithmetic2(instruction, Low, op);
  1948. END EmitArithmetic2XMM;
  1949. PROCEDURE EmitArithmetic3FPU(CONST instruction: IntermediateCode.Instruction; op: LONGINT);
  1950. VAR op1,op2,op3: Assembler.Operand;
  1951. BEGIN
  1952. MakeOperand(instruction.op2,Low,op2,NIL);
  1953. emitter.Emit1(InstructionSet.opFLD,op2);
  1954. INC(fpStackPointer);
  1955. MakeOperand(instruction.op3,Low,op3,NIL);
  1956. IF instruction.op3.mode = IntermediateCode.ModeRegister THEN
  1957. emitter.Emit2(op,opST0,op3);
  1958. ELSE
  1959. emitter.Emit1(op,op3);
  1960. END;
  1961. MakeOperand(instruction.op1,Low,op1,NIL);
  1962. emitter.Emit1(InstructionSet.opFSTP,op1);
  1963. DEC(fpStackPointer);
  1964. END EmitArithmetic3FPU;
  1965. PROCEDURE EmitArithmetic2FPU(CONST instruction: IntermediateCode.Instruction; opcode: LONGINT);
  1966. VAR op1,op2: Assembler.Operand;
  1967. BEGIN
  1968. MakeOperand(instruction.op2,Low,op2,NIL);
  1969. emitter.Emit1(InstructionSet.opFLD,op2);
  1970. INC(fpStackPointer);
  1971. emitter.Emit0(opcode);
  1972. MakeOperand(instruction.op1,Low,op1,NIL);
  1973. emitter.Emit1(InstructionSet.opFSTP,op1);
  1974. DEC(fpStackPointer);
  1975. END EmitArithmetic2FPU;
  1976. PROCEDURE EmitMul(CONST instruction: IntermediateCode.Instruction);
  1977. VAR op1,op2,op3,temp: Assembler.Operand; ra,rd: Ticket;
  1978. value: HUGEINT; exp: LONGINT; iop3: IntermediateCode.Operand;
  1979. inst: IntermediateCode.Instruction;
  1980. BEGIN
  1981. IF IntermediateCode.IsConstantInteger(instruction.op3,value) & IntermediateBackend.PowerOf2(value,exp) THEN
  1982. IntermediateCode.InitImmediate(iop3, IntermediateCode.uint32, exp);
  1983. IntermediateCode.InitInstruction(inst, Basic.invalidPosition, IntermediateCode.shl, instruction.op1, instruction.op2, iop3);
  1984. EmitShift(inst);
  1985. RETURN;
  1986. END;
  1987. ASSERT(~IsComplex(instruction.op1));
  1988. ASSERT(instruction.op1.type.form IN IntermediateCode.Integer);
  1989. IF (instruction.op1.type.sizeInBits = IntermediateCode.Bits8) THEN
  1990. Spill(physicalRegisters.Mapped(AL));
  1991. Spill(physicalRegisters.Mapped(AH));
  1992. ra := ReservePhysicalRegister(IntermediateCode.GeneralPurposeRegister,IntermediateCode.int8,AL,inPC);
  1993. rd := ReservePhysicalRegister(IntermediateCode.GeneralPurposeRegister,IntermediateCode.int8,AH,inPC);
  1994. MakeOperand(instruction.op1,Low,op1,NIL);
  1995. MakeOperand(instruction.op2,Low,op2,ra);
  1996. IF instruction.op3.mode = IntermediateCode.ModeImmediate THEN
  1997. MakeOperand(instruction.op3,Low,op3,rd);
  1998. ELSE
  1999. MakeOperand(instruction.op3,Low,op3,NIL);
  2000. END;
  2001. emitter.Emit1(InstructionSet.opIMUL,op3);
  2002. emitter.Emit2(InstructionSet.opMOV,op1,opAL);
  2003. UnmapTicket(ra);
  2004. UnmapTicket(rd);
  2005. ELSE
  2006. MakeOperand(instruction.op1,Low,op1,NIL);
  2007. MakeOperand(instruction.op2,Low,op2,NIL);
  2008. MakeOperand(instruction.op3,Low,op3,NIL);
  2009. IF ~Assembler.IsRegisterOperand(op1) THEN
  2010. temp := op1;
  2011. ra := TemporaryTicket(instruction.op1.registerClass,instruction.op1.type);
  2012. TicketToOperand(ra,op1);
  2013. END;
  2014. IF Assembler.SameOperand(op1,op3) THEN temp := op2; op2 := op3; op3 := temp END;
  2015. IF Assembler.IsRegisterOperand(op2) OR Assembler.IsMemoryOperand(op2) THEN
  2016. IF Assembler.IsImmediateOperand(op3) THEN
  2017. emitter.Emit3(InstructionSet.opIMUL,op1,op2,op3);
  2018. ELSIF Assembler.IsRegisterOperand(op2) & (op2.register = op1.register) THEN
  2019. IF Assembler.IsRegisterOperand(op3) OR Assembler.IsMemoryOperand(op3) THEN
  2020. emitter.Emit2(InstructionSet.opIMUL,op1,op3);
  2021. ELSE
  2022. rd := TemporaryTicket(instruction.op1.registerClass,instruction.op1.type);
  2023. TicketToOperand(rd,temp);
  2024. Move(temp,op3,instruction.op1.type);
  2025. emitter.Emit2(InstructionSet.opIMUL,op1,temp);
  2026. UnmapTicket(rd);
  2027. END;
  2028. ELSE
  2029. Move(op1,op3,PhysicalOperandType(op1));
  2030. emitter.Emit2(InstructionSet.opIMUL,op1,op2);
  2031. END
  2032. ELSIF Assembler.IsRegisterOperand(op3) OR Assembler.IsMemoryOperand(op3) THEN
  2033. IF Assembler.IsImmediateOperand(op2) THEN
  2034. emitter.Emit3(InstructionSet.opIMUL,op1,op3,op2);
  2035. ELSIF Assembler.IsRegisterOperand(op3) & (op2.register = op1.register) THEN
  2036. IF Assembler.IsRegisterOperand(op2) OR Assembler.IsMemoryOperand(op2) THEN
  2037. emitter.Emit2(InstructionSet.opIMUL,op1,op2);
  2038. ELSE
  2039. rd := TemporaryTicket(instruction.op1.registerClass,instruction.op1.type);
  2040. TicketToOperand(rd,temp);
  2041. Move(temp,op2,instruction.op1.type);
  2042. emitter.Emit2(InstructionSet.opIMUL,op1,temp);
  2043. UnmapTicket(rd);
  2044. END;
  2045. ELSE
  2046. Move(op1,op2,PhysicalOperandType(op1));
  2047. emitter.Emit2(InstructionSet.opIMUL,op1,op3);
  2048. END;
  2049. END;
  2050. IF ra # NIL THEN
  2051. Move(temp,op1,PhysicalOperandType(op1));
  2052. UnmapTicket(ra);
  2053. END;
  2054. END;
  2055. END EmitMul;
  2056. PROCEDURE EmitDivMod(CONST instruction: IntermediateCode.Instruction);
  2057. VAR
  2058. dividend,quotient,remainder,imm,target,memop: Assembler.Operand;
  2059. op1,op2,op3: Assembler.Operand; ra,rd: Ticket;
  2060. size: LONGINT;
  2061. value: HUGEINT; exp: LONGINT; iop3: IntermediateCode.Operand;
  2062. inst: IntermediateCode.Instruction;
  2063. BEGIN
  2064. IF IntermediateCode.IsConstantInteger(instruction.op3,value) & IntermediateBackend.PowerOf2(value,exp) THEN
  2065. IF instruction.opcode = IntermediateCode.div THEN
  2066. IntermediateCode.InitImmediate(iop3, IntermediateCode.uint32, exp);
  2067. IntermediateCode.InitInstruction(inst, Basic.invalidPosition, IntermediateCode.shr, instruction.op1, instruction.op2, iop3);
  2068. EmitShift(inst);
  2069. RETURN;
  2070. ELSE
  2071. IntermediateCode.InitImmediate(iop3, instruction.op3.type, value-1);
  2072. IntermediateCode.InitInstruction(inst, Basic.invalidPosition, IntermediateCode.and, instruction.op1, instruction.op2, iop3);
  2073. EmitArithmetic3(inst,InstructionSet.opAND);
  2074. RETURN;
  2075. END;
  2076. END;
  2077. (*
  2078. In general it must obviously hold that
  2079. a = (a div b) * b + a mod b and
  2080. for all integers a,b#0, and c.
  2081. For positive numbers a and b this holds if
  2082. a div b = max{integer i: i*b <= b} = Entier(a/b)
  2083. and
  2084. a mod b = a-(a div b)*b = min{c >=0: c = a-i*b, integer i}
  2085. Example
  2086. 11 div 3 = 3 (3*3 = 9)
  2087. 11 mod 3 = 2 (=11-9)
  2088. for negative a there are two definitions for mod possible:
  2089. (i) mathematical definition with
  2090. a mod b >= 0:
  2091. a mod b = min{ c >=0: c = a-i*b, integer i} >= 0
  2092. this corresponds with rounding down
  2093. a div b = Entier(a/b) <= a/b
  2094. (ii) symmetric definition with
  2095. (-a) mod' b = -(a mod' b) and
  2096. (-a) div' b = -(a div' b)
  2097. corresponding with rounding to zero
  2098. a div' b = RoundToZero(a/b)
  2099. Examples
  2100. (i) -11 div 3 = -4 (3*(-4) = -12)
  2101. -11 mod 3 = 1 (=-11-(-12))
  2102. (ii) -11 div' 3 = -(11 div 3) = -3 (3*(-3)= -9)
  2103. -11 mod' 3 = -2 (=-11-(-9))
  2104. The behaviour for negative b can, in the symmetrical case, be deduced as
  2105. (ii) symmetric definition
  2106. a div' (-b) = (-a) div' b = -(a div' b)
  2107. a mod' (-b) = a- a div' (-b) * (-b) = a mod' b
  2108. In the mathematical case it is not so easy. It turns out that the definitions
  2109. a DIV b = Entier(a/b) = max{integer i: i*b <= b}
  2110. and
  2111. a MOD b = min { c >=0 : c = a-i*b, integer i} >= 0
  2112. are not compliant with
  2113. a = (a DIV b) * b + a MOD b
  2114. if b <= 0.
  2115. Proof: assume that b<0, then
  2116. a - Entier(a/b) * b >= 0
  2117. <=_> a >= Entier(a/b) * b
  2118. <=> Entier(a/b) >= a/b (contradiction to definition of Entier).
  2119. OBERON ADOPTS THE MATHEMATICAL DEFINITION !
  2120. For integers a and b (b>0) it holds that
  2121. a DIV b = Entier(a/b) <= a/b
  2122. a MOD b = min{ c >=0: c = b-i*a, integer i} = a - a DIV b * b
  2123. The behaviour for b < 0 is explicitely undefined.
  2124. *)
  2125. (*
  2126. AX / regMem8 = AL (remainder AH)
  2127. DX:AX / regmem16 = AX (remainder DX)
  2128. EDX:EAX / regmem32 = EAX (remainder EDX)
  2129. RDX:EAX / regmem64 = RAX (remainder RDX)
  2130. 1.) EAX <- source1
  2131. 2.) CDQ
  2132. 3.) IDIV source2
  2133. 3.) SHL EDX
  2134. 4.) SBB EAX,1
  2135. result is in EAX
  2136. *)
  2137. MakeOperand(instruction.op2,Low,op2,NIL);
  2138. CASE instruction.op1.type.sizeInBits OF
  2139. IntermediateCode.Bits8:
  2140. Spill(physicalRegisters.Mapped(AL)); ra := ReservePhysicalRegister(IntermediateCode.GeneralPurposeRegister,IntermediateCode.int8,AL,inPC);
  2141. emitter.Emit2(InstructionSet.opMOV,opAL,op2);
  2142. dividend := opAX;
  2143. quotient := opAL;
  2144. remainder := opAH;
  2145. emitter.Emit0(InstructionSet.opCBW);
  2146. | IntermediateCode.Bits16:
  2147. Spill(physicalRegisters.Mapped(AX)); ra := ReservePhysicalRegister(IntermediateCode.GeneralPurposeRegister,IntermediateCode.int16,AX,inPC);
  2148. emitter.Emit2(InstructionSet.opMOV,opAX,op2);
  2149. Spill(physicalRegisters.Mapped(DX)); rd := ReservePhysicalRegister(IntermediateCode.GeneralPurposeRegister,IntermediateCode.int16,DX,inPC);
  2150. dividend := opAX;
  2151. quotient := dividend;
  2152. remainder := opDX;
  2153. emitter.Emit0(InstructionSet.opCWD);
  2154. | IntermediateCode.Bits32:
  2155. Spill(physicalRegisters.Mapped(EAX)); ra := ReservePhysicalRegister(IntermediateCode.GeneralPurposeRegister,IntermediateCode.int32,EAX,inPC);
  2156. emitter.Emit2(InstructionSet.opMOV,opEAX,op2);
  2157. Spill(physicalRegisters.Mapped(EDX)); rd := ReservePhysicalRegister(IntermediateCode.GeneralPurposeRegister,IntermediateCode.int32,EDX,inPC);
  2158. dividend := opEAX;
  2159. quotient := dividend;
  2160. remainder := opEDX;
  2161. emitter.Emit0(InstructionSet.opCDQ);
  2162. | IntermediateCode.Bits64:
  2163. Spill(physicalRegisters.Mapped(RAX)); ra := ReservePhysicalRegister(IntermediateCode.GeneralPurposeRegister,IntermediateCode.int64,RAX,inPC);
  2164. emitter.Emit2(InstructionSet.opMOV,opRA,op2);
  2165. Spill(physicalRegisters.Mapped(RDX)); rd := ReservePhysicalRegister(IntermediateCode.GeneralPurposeRegister,IntermediateCode.int64,RDX,inPC);
  2166. dividend := opRA;
  2167. quotient := dividend;
  2168. remainder := registerOperands[RDX];
  2169. emitter.Emit0(InstructionSet.opCQO);
  2170. END;
  2171. (* registers might have been changed, so we make the operands now *)
  2172. MakeOperand(instruction.op1,Low,op1,NIL);
  2173. MakeOperand(instruction.op2,Low,op2,NIL);
  2174. MakeOperand(instruction.op3,Low,op3,NIL);
  2175. IF instruction.op3.mode = IntermediateCode.ModeImmediate THEN
  2176. size := instruction.op3.type.sizeInBits DIV 8;
  2177. Basic.Align(size, 4 (* cpuBits DIV 8 *) );
  2178. AllocateStack(size);
  2179. Assembler.InitMem(memop,SHORT(instruction.op3.type.sizeInBits DIV 8),SP,0);
  2180. emitter.Emit2(InstructionSet.opMOV,memop,op3);
  2181. op3 := memop;
  2182. END;
  2183. emitter.Emit1(InstructionSet.opIDIV,op3);
  2184. IF instruction.opcode = IntermediateCode.mod THEN
  2185. imm := Assembler.NewImm8 (0);
  2186. emitter.Emit2(InstructionSet.opCMP, remainder, imm);
  2187. Assembler.InitImm8(target,0);
  2188. emitter.Emit1(InstructionSet.opJGE, target);
  2189. emitter.Emit2( InstructionSet.opADD, remainder, op3);
  2190. emitter.code.PutByteAt(target.pc,(emitter.code.pc -target.pc )-1);
  2191. emitter.Emit2(InstructionSet.opMOV, op1, remainder);
  2192. ELSE
  2193. imm := Assembler.NewImm8 (1);
  2194. emitter.Emit2(InstructionSet.opSHL, remainder, imm);
  2195. imm := Assembler.NewImm8 (0);
  2196. emitter.Emit2(InstructionSet.opSBB, quotient, imm);
  2197. emitter.Emit2(InstructionSet.opMOV, op1, quotient);
  2198. END;
  2199. IF instruction.op3.mode = IntermediateCode.ModeImmediate THEN
  2200. size := instruction.op3.type.sizeInBits DIV 8;
  2201. Basic.Align(size, 4 (* cpuBits DIV 8*) );
  2202. AllocateStack(-size);
  2203. END;
  2204. END EmitDivMod;
  2205. PROCEDURE EmitShift(CONST instruction: IntermediateCode.Instruction);
  2206. VAR
  2207. shift: Assembler.Operand;
  2208. op: LONGINT;
  2209. op1,op2,op3,dest,temporary,op1High,op2High: Assembler.Operand;
  2210. index: SHORTINT; temp: Assembler.Operand;
  2211. left: BOOLEAN;
  2212. ecx,ticket: Ticket;
  2213. BEGIN
  2214. Assert(instruction.op1.type.form IN IntermediateCode.Integer,"must be integer operand");
  2215. IF instruction.op1.type.form = IntermediateCode.UnsignedInteger THEN
  2216. IF instruction.opcode = IntermediateCode.shr THEN op := InstructionSet.opSHR; left := FALSE;
  2217. ELSIF instruction.opcode = IntermediateCode.shl THEN op := InstructionSet.opSHL; left := TRUE;
  2218. ELSIF instruction.opcode = IntermediateCode.ror THEN op := InstructionSet.opROR; left := FALSE;
  2219. ELSIF instruction.opcode = IntermediateCode.rol THEN op := InstructionSet.opROL; left := TRUE;
  2220. END;
  2221. ELSE
  2222. IF instruction.opcode = IntermediateCode.shr THEN op := InstructionSet.opSAR; left := FALSE;
  2223. ELSIF instruction.opcode = IntermediateCode.shl THEN op := InstructionSet.opSAL; left := TRUE;
  2224. ELSIF instruction.opcode = IntermediateCode.ror THEN op := InstructionSet.opROR; left := FALSE;
  2225. ELSIF instruction.opcode = IntermediateCode.rol THEN op := InstructionSet.opROL; left := TRUE;
  2226. END;
  2227. END;
  2228. IF instruction.op3.mode # IntermediateCode.ModeImmediate THEN
  2229. IF backend.cooperative THEN ap.spillable := TRUE END;
  2230. Spill(physicalRegisters.Mapped(ECX));
  2231. ecx := ReservePhysicalRegister(IntermediateCode.GeneralPurposeRegister,IntermediateCode.int32,ECX,inPC);
  2232. END;
  2233. (*GetTemporaryRegister(instruction.op2.type,dest);*)
  2234. MakeOperand(instruction.op1,Low,op1,NIL);
  2235. IF ~Assembler.IsRegisterOperand(op1) THEN GetTemporaryRegister(instruction.op2.type,dest) ELSE dest := op1 END;
  2236. MakeOperand(instruction.op2,Low,op2,NIL);
  2237. MakeOperand(instruction.op3,Low,op3,NIL);
  2238. IF instruction.op3.mode = IntermediateCode.ModeImmediate THEN
  2239. Assembler.InitImm8(shift,instruction.op3.intValue);
  2240. ELSE
  2241. CASE instruction.op3.type.sizeInBits OF
  2242. IntermediateCode.Bits8: index := CL;
  2243. |IntermediateCode.Bits16: index := CX;
  2244. |IntermediateCode.Bits32: index := ECX;
  2245. |IntermediateCode.Bits64: index := RCX;
  2246. END;
  2247. (*
  2248. IF (physicalRegisters.toVirtual[index] # free) & ((physicalRegisters.toVirtual[index] # instruction.op1.register) OR (instruction.op1.mode # IntermediateCode.ModeRegister)) THEN
  2249. Spill();
  2250. (*
  2251. emitter.Emit1(InstructionSet.opPUSH,opECX);
  2252. ecxPushed := TRUE;
  2253. *)
  2254. END;
  2255. *)
  2256. ticket := virtualRegisters.Mapped(instruction.op3.register,Low);
  2257. IF (instruction.op3.mode # IntermediateCode.ModeRegister) OR (ticket = NIL) OR (ticket.spilled) OR (ticket.register # index) THEN
  2258. emitter.Emit2(InstructionSet.opMOV,registerOperands[index],op3);
  2259. END;
  2260. shift := opCL;
  2261. END;
  2262. IF ~IsComplex(instruction.op1) THEN
  2263. Move(dest,op2,PhysicalOperandType(dest));
  2264. emitter.Emit2 (op, dest,shift);
  2265. Move(op1,dest,PhysicalOperandType(op1));
  2266. ELSIF left THEN
  2267. MakeOperand(instruction.op1,High,op1High,NIL);
  2268. MakeOperand(instruction.op2,High,op2High,NIL);
  2269. IF ~IntermediateCode.OperandEquals(instruction.op1,instruction.op2) THEN
  2270. Move(op1,op2,PhysicalOperandType(op1));
  2271. Move(op1High,op2High,PhysicalOperandType(op1High))
  2272. END;
  2273. IF (instruction.opcode=IntermediateCode.rol) THEN
  2274. (* |high| <- |low| <- |temp=high| *)
  2275. ticket := TemporaryTicket(IntermediateCode.GeneralPurposeRegister,IntermediateCode.int32);
  2276. TicketToOperand(ticket,temp);
  2277. emitter.Emit2( InstructionSet.opMOV, temp, op1High);
  2278. emitter.Emit3( InstructionSet.opSHLD,op1High, op1, shift);
  2279. emitter.Emit3( InstructionSet.opSHLD, op1, temp, shift);
  2280. UnmapTicket(ticket);
  2281. ELSE
  2282. (* |high| <- |low| *)
  2283. emitter.Emit3( InstructionSet.opSHLD, op1,op1High,shift);
  2284. emitter.Emit2( op, op1,shift);
  2285. END;
  2286. ELSE
  2287. IF ~IntermediateCode.OperandEquals(instruction.op1,instruction.op2) THEN
  2288. Move(op1,op2,PhysicalOperandType(op1))
  2289. END;
  2290. IF instruction.opcode=IntermediateCode.ror THEN
  2291. (* |temp=low| -> |high| -> |low| *)
  2292. ticket := TemporaryTicket(IntermediateCode.GeneralPurposeRegister,IntermediateCode.int32);
  2293. TicketToOperand(ticket,temp);
  2294. emitter.Emit2( InstructionSet.opMOV, temporary, op1);
  2295. emitter.Emit3( InstructionSet.opSHRD,op1, op1High, shift);
  2296. emitter.Emit3( InstructionSet.opSHRD, op1High, temporary, shift);
  2297. UnmapTicket(ticket);
  2298. ELSE
  2299. (* |high| -> |low| *)
  2300. emitter.Emit3( InstructionSet.opSHRD, op1,op1High,shift);
  2301. emitter.Emit2( op, op1High, shift);
  2302. END;
  2303. END;
  2304. IF backend.cooperative & (instruction.op3.mode # IntermediateCode.ModeImmediate) THEN
  2305. UnmapTicket(ecx);
  2306. UnSpill(ap);
  2307. ap.spillable := FALSE;
  2308. END;
  2309. END EmitShift;
  2310. PROCEDURE EmitCas(CONST instruction: IntermediateCode.Instruction);
  2311. VAR ra: Ticket; op1,op2,op3,mem: Assembler.Operand; register: LONGINT;
  2312. BEGIN
  2313. CASE instruction.op2.type.sizeInBits OF
  2314. | IntermediateCode.Bits8: register := AL;
  2315. | IntermediateCode.Bits16: register := AX;
  2316. | IntermediateCode.Bits32: register := EAX;
  2317. | IntermediateCode.Bits64: register := RAX;
  2318. END;
  2319. Spill(physicalRegisters.Mapped(register));
  2320. ra := ReservePhysicalRegister(IntermediateCode.GeneralPurposeRegister,instruction.op2.type,register,inPC);
  2321. IF IntermediateCode.OperandEquals (instruction.op2,instruction.op3) THEN
  2322. MakeOperand(instruction.op1,Low,op1,ra);
  2323. Assembler.InitMem(mem,SHORT(instruction.op1.type.sizeInBits DIV 8),op1.register,0);
  2324. emitter.Emit2(InstructionSet.opMOV,op1,mem);
  2325. ELSE
  2326. MakeOperand(instruction.op2,Low,op2,ra);
  2327. MakeRegister(instruction.op1,Low,op1);
  2328. Assembler.InitMem(mem,SHORT(instruction.op2.type.sizeInBits DIV 8),op1.register,0);
  2329. MakeRegister(instruction.op3,Low,op3);
  2330. emitter.EmitPrefix (InstructionSet.prfLOCK);
  2331. emitter.Emit2(InstructionSet.opCMPXCHG,mem,op3);
  2332. END;
  2333. END EmitCas;
  2334. PROCEDURE EmitCopy(CONST instruction: IntermediateCode.Instruction);
  2335. VAR op1,op2,op3: Assembler.Operand; esi, edi, ecx, t: Ticket; temp,imm: Assembler.Operand; source, dest: IntermediateCode.Operand; size: HUGEINT;
  2336. BEGIN
  2337. IF IntermediateCode.IsConstantInteger(instruction.op3, size) & (size = 4) THEN
  2338. Spill(physicalRegisters.Mapped(ESI));
  2339. Spill(physicalRegisters.Mapped(EDI));
  2340. esi := ReservePhysicalRegister(IntermediateCode.GeneralPurposeRegister,IntermediateCode.int32,RS,inPC);
  2341. edi := ReservePhysicalRegister(IntermediateCode.GeneralPurposeRegister,IntermediateCode.int32,RD,inPC);
  2342. MakeOperand(instruction.op1,Low,op1,edi);
  2343. MakeOperand(instruction.op2,Low,op2,esi);
  2344. emitter.Emit0(InstructionSet.opMOVSD);
  2345. UnmapTicket(esi);
  2346. UnmapTicket(edi);
  2347. ELSE
  2348. Spill(physicalRegisters.Mapped(ESI));
  2349. Spill(physicalRegisters.Mapped(EDI));
  2350. IF backend.cooperative THEN ap.spillable := TRUE END;
  2351. Spill(physicalRegisters.Mapped(ECX));
  2352. esi := ReservePhysicalRegister(IntermediateCode.GeneralPurposeRegister,IntermediateCode.int32,RS,inPC);
  2353. edi := ReservePhysicalRegister(IntermediateCode.GeneralPurposeRegister,IntermediateCode.int32,RD,inPC);
  2354. ecx := ReservePhysicalRegister(IntermediateCode.GeneralPurposeRegister,IntermediateCode.int32,RC,inPC);
  2355. MakeOperand(instruction.op1,Low,op1,edi);
  2356. MakeOperand(instruction.op2,Low,op2,esi);
  2357. IF (instruction.op1.mode = IntermediateCode.ModeRegister) & (instruction.op1.register = IntermediateCode.SP) & IntermediateCode.IsConstantInteger(instruction.op3, size) & (size >= 4096) THEN
  2358. (* special case on stack: copy downwards for possible stack allocation *)
  2359. IF size MOD 4 # 0 THEN
  2360. imm := Assembler.NewImm32(size-1);
  2361. emitter.Emit2(InstructionSet.opADD, opEDI, imm);
  2362. emitter.Emit2(InstructionSet.opADD, opESI, imm);
  2363. imm := Assembler.NewImm32(size MOD 4);
  2364. emitter.Emit2(InstructionSet.opMOV, opECX, imm);
  2365. emitter.Emit0(InstructionSet.opSTD); (* copy down *)
  2366. emitter.EmitPrefix (InstructionSet.prfREP);
  2367. emitter.Emit0(InstructionSet.opMOVSB);
  2368. imm := Assembler.NewImm32(size DIV 4);
  2369. emitter.Emit2(InstructionSet.opMOV, opECX, imm);
  2370. emitter.EmitPrefix (InstructionSet.prfREP);
  2371. emitter.Emit0(InstructionSet.opMOVSD);
  2372. ELSE
  2373. imm := Assembler.NewImm32(size-4);
  2374. emitter.Emit2(InstructionSet.opADD, opEDI, imm);
  2375. emitter.Emit2(InstructionSet.opADD, opESI, imm);
  2376. imm := Assembler.NewImm32(size DIV 4);
  2377. emitter.Emit2(InstructionSet.opMOV, opECX, imm);
  2378. emitter.Emit0(InstructionSet.opSTD); (* copy down *)
  2379. emitter.EmitPrefix (InstructionSet.prfREP);
  2380. emitter.Emit0(InstructionSet.opMOVSD);
  2381. END
  2382. ELSIF IntermediateCode.IsConstantInteger(instruction.op3, size) THEN
  2383. imm := Assembler.NewImm32(size DIV 4);
  2384. emitter.Emit2(InstructionSet.opMOV, opECX, imm);
  2385. emitter.Emit0(InstructionSet.opCLD); (* copy upwards *)
  2386. emitter.EmitPrefix (InstructionSet.prfREP);
  2387. emitter.Emit0(InstructionSet.opMOVSD);
  2388. IF size MOD 4 # 0 THEN
  2389. imm := Assembler.NewImm32(size MOD 4);
  2390. emitter.Emit2(InstructionSet.opMOV, opECX, imm);
  2391. emitter.EmitPrefix (InstructionSet.prfREP);
  2392. emitter.Emit0(InstructionSet.opMOVSB);
  2393. END;
  2394. (* this does not work in the kernel -- for whatever reasons *)
  2395. ELSIF (instruction.op1.mode = IntermediateCode.ModeRegister) & (instruction.op1.register = IntermediateCode.SP) THEN
  2396. MakeOperand(instruction.op3,Low,op3,ecx);
  2397. t := TemporaryTicket(IntermediateCode.GeneralPurposeRegister, IntermediateCode.int32);
  2398. TicketToOperand(t, temp);
  2399. emitter.Emit2(InstructionSet.opADD, opESI, opECX);
  2400. emitter.Emit2(InstructionSet.opADD, opEDI, opECX);
  2401. imm := Assembler.NewImm8(1);
  2402. emitter.Emit2(InstructionSet.opSUB, opESI, imm);
  2403. emitter.Emit2(InstructionSet.opSUB, opEDI, imm);
  2404. emitter.Emit2(InstructionSet.opMOV, temp, opECX);
  2405. imm := Assembler.NewImm8(3);
  2406. emitter.Emit2(InstructionSet.opAND, opECX, imm);
  2407. emitter.Emit0(InstructionSet.opSTD); (* copy downwards *)
  2408. emitter.EmitPrefix (InstructionSet.prfREP);
  2409. emitter.Emit0(InstructionSet.opMOVSB);
  2410. imm := Assembler.NewImm8(2);
  2411. emitter.Emit2(InstructionSet.opMOV, opECX, temp);
  2412. emitter.Emit2(InstructionSet.opSHR, opECX, imm);
  2413. imm := Assembler.NewImm8(3);
  2414. emitter.Emit2(InstructionSet.opSUB, opESI, imm);
  2415. emitter.Emit2(InstructionSet.opSUB, opEDI, imm);
  2416. emitter.EmitPrefix (InstructionSet.prfREP);
  2417. emitter.Emit0(InstructionSet.opMOVSD);
  2418. emitter.Emit0(InstructionSet.opCLD);
  2419. ELSE
  2420. MakeOperand(instruction.op3,Low,op3,ecx);
  2421. t := TemporaryTicket(IntermediateCode.GeneralPurposeRegister, IntermediateCode.int32);
  2422. TicketToOperand(t, temp);
  2423. emitter.Emit2(InstructionSet.opMOV, temp, opECX);
  2424. imm := Assembler.NewImm8(3);
  2425. emitter.Emit2(InstructionSet.opAND, temp, imm);
  2426. imm := Assembler.NewImm8(2);
  2427. emitter.Emit2(InstructionSet.opSHR, opECX, imm);
  2428. emitter.Emit0(InstructionSet.opCLD); (* copy upwards *)
  2429. emitter.EmitPrefix (InstructionSet.prfREP);
  2430. emitter.Emit0(InstructionSet.opMOVSD);
  2431. emitter.Emit2(InstructionSet.opMOV, opECX, temp);
  2432. emitter.EmitPrefix (InstructionSet.prfREP);
  2433. emitter.Emit0(InstructionSet.opMOVSB);
  2434. END;
  2435. UnmapTicket(esi);
  2436. UnmapTicket(edi);
  2437. UnmapTicket(ecx);
  2438. IF backend.cooperative THEN
  2439. UnSpill(ap);
  2440. ap.spillable := FALSE;
  2441. END;
  2442. END;
  2443. END EmitCopy;
  2444. PROCEDURE EmitFill(CONST instruction: IntermediateCode.Instruction; down: BOOLEAN);
  2445. VAR reg,sizeInBits,i: LONGINT;val, value, size, dest: Assembler.Operand;
  2446. op: LONGINT;
  2447. edi, ecx: Ticket;
  2448. BEGIN
  2449. IF FALSE & (instruction.op2.mode = IntermediateCode.ModeImmediate) & (instruction.op2.symbol.name = "") & (instruction.op2.intValue < 5) THEN
  2450. sizeInBits := instruction.op3.type.sizeInBits;
  2451. IF sizeInBits = IntermediateCode.Bits8 THEN value := opAL;
  2452. ELSIF sizeInBits = IntermediateCode.Bits16 THEN value := opAX;
  2453. ELSIF sizeInBits = IntermediateCode.Bits32 THEN value := opEAX;
  2454. ELSE HALT(200)
  2455. END;
  2456. MakeOperand(instruction.op1,Low,dest,NIL);
  2457. IF instruction.op1.mode = IntermediateCode.ModeRegister THEN reg := dest.register
  2458. ELSE emitter.Emit2(InstructionSet.opMOV,opEDX,dest); reg := EDX;
  2459. END;
  2460. IF (instruction.op3.mode = IntermediateCode.ModeImmediate) & (instruction.op3.type.form IN IntermediateCode.Integer) & (instruction.op3.intValue = 0) THEN
  2461. emitter.Emit2(InstructionSet.opXOR,opEAX,opEAX);
  2462. ELSE
  2463. MakeOperand(instruction.op3,Low,value,NIL);
  2464. END;
  2465. FOR i := 0 TO SHORT(instruction.op2.intValue)-1 DO
  2466. IF down THEN
  2467. Assembler.InitMem(dest,SHORT(SHORT(sizeInBits DIV 8)),reg,-i*sizeInBits DIV 8);
  2468. ELSE
  2469. Assembler.InitMem(dest,SHORT(SHORT(sizeInBits DIV 8 )),reg,i*sizeInBits DIV 8);
  2470. END;
  2471. emitter.Emit2(InstructionSet.opMOV,dest,value);
  2472. END;
  2473. ELSE
  2474. Spill(physicalRegisters.Mapped(EDI));
  2475. IF backend.cooperative THEN ap.spillable := TRUE END;
  2476. Spill(physicalRegisters.Mapped(ECX));
  2477. edi := ReservePhysicalRegister(IntermediateCode.GeneralPurposeRegister,IntermediateCode.int32,EDI,inPC);
  2478. ecx := ReservePhysicalRegister(IntermediateCode.GeneralPurposeRegister,IntermediateCode.int32,ECX,inPC);
  2479. MakeOperand(instruction.op1,Low,dest,edi);
  2480. MakeOperand(instruction.op2,Low,size,ecx);
  2481. MakeOperand(instruction.op3,Low,value,NIL);
  2482. (*
  2483. emitter.Emit2(InstructionSet.opMOV,opEDI, op1[Low]);
  2484. emitter.Emit2(InstructionSet.opMOV,opECX, op3[Low]);
  2485. *)
  2486. CASE instruction.op3.type.sizeInBits OF
  2487. IntermediateCode.Bits8: val := opAL; op := InstructionSet.opSTOSB;
  2488. |IntermediateCode.Bits16: val := opAX; op := InstructionSet.opSTOSW;
  2489. |IntermediateCode.Bits32: val := opEAX; op := InstructionSet.opSTOSD;
  2490. ELSE Halt("only supported for upto 32 bit integers ");
  2491. END;
  2492. IF (instruction.op3.mode = IntermediateCode.ModeImmediate) & (instruction.op3.type.form IN IntermediateCode.Integer) & (instruction.op3.intValue = 0) THEN
  2493. emitter.Emit2(InstructionSet.opXOR,opEAX,opEAX);
  2494. ELSE
  2495. emitter.Emit2(InstructionSet.opMOV,val,value);
  2496. END;
  2497. IF down THEN
  2498. emitter.Emit0(InstructionSet.opSTD); (* fill downwards *)
  2499. ELSE
  2500. emitter.Emit0(InstructionSet.opCLD); (* fill upwards *)
  2501. END;
  2502. emitter.EmitPrefix (InstructionSet.prfREP);
  2503. emitter.Emit0(op);
  2504. IF down THEN (* needed as calls to windows crash otherwise *)
  2505. emitter.Emit0(InstructionSet.opCLD);
  2506. END;
  2507. UnmapTicket(ecx);
  2508. IF backend.cooperative THEN
  2509. UnSpill(ap);
  2510. ap.spillable := FALSE;
  2511. END;
  2512. END;
  2513. END EmitFill;
  2514. PROCEDURE EmitBr (CONST instruction: IntermediateCode.Instruction);
  2515. VAR dest,destPC,offset: LONGINT; target: Assembler.Operand;hit,fail: LONGINT; reverse: BOOLEAN;
  2516. (* jump operands *) left,right,temp: Assembler.Operand;
  2517. failOp: Assembler.Operand; failPC: LONGINT;
  2518. PROCEDURE JmpDest(brop: LONGINT);
  2519. BEGIN
  2520. IF instruction.op1.mode = IntermediateCode.ModeImmediate THEN
  2521. IF instruction.op1.symbol.name # in.name THEN
  2522. Assembler.InitOffset32(target,instruction.op1.intValue);
  2523. Assembler.SetSymbol(target,instruction.op1.symbol.name,instruction.op1.symbol.fingerprint,instruction.op1.symbolOffset,instruction.op1.offset);
  2524. emitter.Emit1(brop,target);
  2525. ELSE
  2526. dest := (instruction.op1.symbolOffset); (* this is the offset in the in-data section (intermediate code), it is not byte- *)
  2527. destPC := (in.instructions[dest].pc );
  2528. offset := destPC - (out.pc );
  2529. IF dest > inPC THEN (* forward jump *)
  2530. Assembler.InitOffset32(target,0);
  2531. Assembler.SetSymbol(target,instruction.op1.symbol.name,instruction.op1.symbol.fingerprint,instruction.op1.symbolOffset,instruction.op1.offset);
  2532. emitter.Emit1(brop,target);
  2533. ELSIF ABS(offset) <= 126 THEN
  2534. Assembler.InitOffset8(target,destPC);
  2535. emitter.Emit1(brop,target);
  2536. ELSE
  2537. Assembler.InitOffset32(target,destPC);
  2538. emitter.Emit1(brop,target);
  2539. END;
  2540. END;
  2541. ELSE
  2542. MakeOperand(instruction.op1,Low,target,NIL);
  2543. emitter.Emit1(brop,target);
  2544. END;
  2545. END JmpDest;
  2546. PROCEDURE CmpFloat;
  2547. BEGIN
  2548. IF backend.forceFPU THEN
  2549. MakeOperand(instruction.op2,Low,left,NIL);
  2550. emitter.Emit1(InstructionSet.opFLD,left); INC(fpStackPointer);
  2551. MakeOperand(instruction.op3,Low,right,NIL);
  2552. emitter.Emit1(InstructionSet.opFCOMP,right); DEC(fpStackPointer);
  2553. emitter.Emit1(InstructionSet.opFNSTSW,opAX);
  2554. emitter.Emit0(InstructionSet.opSAHF);
  2555. ELSE
  2556. MakeRegister(instruction.op2,Low,left);
  2557. MakeOperand(instruction.op3,Low,right,NIL);
  2558. IF instruction.op2.type.sizeInBits = 32 THEN
  2559. emitter.Emit2(InstructionSet.opCOMISS, left, right);
  2560. ELSE
  2561. emitter.Emit2(InstructionSet.opCOMISD, left, right);
  2562. END
  2563. END;
  2564. END CmpFloat;
  2565. PROCEDURE Cmp(part: LONGINT; VAR reverse: BOOLEAN);
  2566. VAR type: IntermediateCode.Type; left,right: Assembler.Operand;
  2567. BEGIN
  2568. IF (instruction.op2.mode = IntermediateCode.ModeImmediate) & (instruction.op3.mode = IntermediateCode.ModeImmediate) THEN
  2569. reverse := FALSE;
  2570. GetPartType(instruction.op2.type,part,type);
  2571. GetTemporaryRegister(type,temp);
  2572. MakeOperand(instruction.op2,part,left,NIL);
  2573. MakeOperand(instruction.op3,part,right,NIL);
  2574. Move(temp,left, type);
  2575. left := temp;
  2576. ELSIF instruction.op2.mode = IntermediateCode.ModeImmediate THEN
  2577. reverse := TRUE;
  2578. MakeOperand(instruction.op2,part,right,NIL);
  2579. MakeOperand(instruction.op3,part,left,NIL);
  2580. ELSIF IsMemoryOperand(instruction.op2,part) & IsMemoryOperand(instruction.op3,part) THEN
  2581. reverse := FALSE;
  2582. GetPartType(instruction.op2.type,part,type);
  2583. GetTemporaryRegister(type,temp);
  2584. MakeOperand(instruction.op2,part,left,NIL);
  2585. MakeOperand(instruction.op3,part,right,NIL);
  2586. Move(temp,right,type);
  2587. right := temp;
  2588. ELSE
  2589. reverse := FALSE;
  2590. MakeOperand(instruction.op2,part,left,NIL);
  2591. MakeOperand(instruction.op3,part,right,NIL);
  2592. END;
  2593. emitter.Emit2(InstructionSet.opCMP,left,right);
  2594. END Cmp;
  2595. BEGIN
  2596. IF (instruction.op1.symbol.name = in.name) & (instruction.op1.symbolOffset = inPC +1) THEN (* jump to next instruction can be ignored *)
  2597. IF dump # NIL THEN dump.String("jump to next instruction ignored"); dump.Ln END;
  2598. RETURN
  2599. END;
  2600. failPC := 0;
  2601. IF instruction.opcode = IntermediateCode.br THEN
  2602. hit := InstructionSet.opJMP
  2603. ELSIF instruction.op2.type.form = IntermediateCode.Float THEN
  2604. CmpFloat;
  2605. CASE instruction.opcode OF
  2606. IntermediateCode.breq: hit := InstructionSet.opJE;
  2607. |IntermediateCode.brne:hit := InstructionSet.opJNE;
  2608. |IntermediateCode.brge: hit := InstructionSet.opJAE
  2609. |IntermediateCode.brlt: hit := InstructionSet.opJB
  2610. END;
  2611. ELSE
  2612. IF ~IsComplex(instruction.op2) THEN
  2613. Cmp(Low,reverse);
  2614. CASE instruction.opcode OF
  2615. IntermediateCode.breq: hit := InstructionSet.opJE;
  2616. |IntermediateCode.brne: hit := InstructionSet.opJNE;
  2617. |IntermediateCode.brge:
  2618. IF instruction.op2.type.form = IntermediateCode.SignedInteger THEN
  2619. IF reverse THEN hit := InstructionSet.opJLE ELSE hit := InstructionSet.opJGE END;
  2620. ELSIF instruction.op2.type.form = IntermediateCode.UnsignedInteger THEN
  2621. IF reverse THEN hit := InstructionSet.opJBE ELSE hit := InstructionSet.opJAE END;
  2622. END;
  2623. |IntermediateCode.brlt:
  2624. IF instruction.op2.type.form = IntermediateCode.SignedInteger THEN
  2625. IF reverse THEN hit := InstructionSet.opJG ELSE hit := InstructionSet.opJL END;
  2626. ELSIF instruction.op2.type.form = IntermediateCode.UnsignedInteger THEN
  2627. IF reverse THEN hit := InstructionSet.opJA ELSE hit := InstructionSet.opJB END;
  2628. END;
  2629. END;
  2630. ELSE
  2631. Assert(instruction.op2.type.form = IntermediateCode.SignedInteger,"no unsigned integer64");
  2632. Cmp(High,reverse);
  2633. CASE instruction.opcode OF
  2634. IntermediateCode.breq: hit := 0; fail := InstructionSet.opJNE;
  2635. |IntermediateCode.brne: hit := InstructionSet.opJNE; fail := 0;
  2636. |IntermediateCode.brge:
  2637. IF reverse THEN hit := InstructionSet.opJL; fail := InstructionSet.opJG;
  2638. ELSE hit := InstructionSet.opJG; fail := InstructionSet.opJL
  2639. END;
  2640. |IntermediateCode.brlt:
  2641. IF reverse THEN hit := InstructionSet.opJG; fail := InstructionSet.opJL
  2642. ELSE hit := InstructionSet.opJL; fail := InstructionSet.opJG
  2643. END;
  2644. END;
  2645. IF hit # 0 THEN JmpDest(hit) END;
  2646. IF fail # 0 THEN
  2647. failPC := out.pc; (* to avoid potential value overflow problem, will be patched anyway *)
  2648. Assembler.InitOffset8(failOp,failPC );
  2649. emitter.Emit1(fail,failOp);
  2650. failPC := failOp.pc;
  2651. END;
  2652. Cmp(Low,reverse);
  2653. CASE instruction.opcode OF
  2654. IntermediateCode.breq: hit := InstructionSet.opJE
  2655. |IntermediateCode.brne: hit := InstructionSet.opJNE
  2656. |IntermediateCode.brge:
  2657. IF reverse THEN hit := InstructionSet.opJBE ELSE hit := InstructionSet.opJAE END;
  2658. |IntermediateCode.brlt:
  2659. IF reverse THEN hit := InstructionSet.opJA ELSE hit := InstructionSet.opJB END;
  2660. END;
  2661. END;
  2662. END;
  2663. JmpDest(hit);
  2664. IF failPC > 0 THEN out.PutByteAt(failPC,(out.pc-failPC)-1); END;
  2665. END EmitBr;
  2666. PROCEDURE EmitPush(CONST vop: IntermediateCode.Operand; part: LONGINT);
  2667. VAR index: LONGINT; type,cpuType: IntermediateCode.Type; op1: Assembler.Operand; ra: Ticket;
  2668. BEGIN
  2669. GetPartType(vop.type,part,type);
  2670. ASSERT(type.form IN IntermediateCode.Integer);
  2671. IF vop.mode = IntermediateCode.ModeImmediate THEN (* may not push 16 bit immediate: strange instruction in 32 / 64 bit mode *)
  2672. GetImmediate(vop,part,op1,TRUE);
  2673. emitter.Emit1(InstructionSet.opPUSH,op1);
  2674. ELSIF (type.sizeInBits = cpuBits) THEN
  2675. MakeOperand(vop,part,op1,NIL);
  2676. emitter.Emit1(InstructionSet.opPUSH,op1);
  2677. ELSE
  2678. ASSERT(type.sizeInBits < cpuBits);
  2679. MakeOperand(vop,part,op1,NIL);
  2680. IF Assembler.IsRegisterOperand(op1) & ~((cpuBits=32) & (type.sizeInBits=8) & (op1.register >= AH)) THEN
  2681. index := op1.register MOD 32 + opRA.register;
  2682. emitter.Emit1(InstructionSet.opPUSH, registerOperands[index]);
  2683. ELSE
  2684. WHILE physicalRegisters.Mapped(opRA.register) # free DO Spill(physicalRegisters.Mapped(opRA.register)) END;
  2685. IntermediateCode.InitType(cpuType,IntermediateCode.SignedInteger,SHORT(cpuBits));
  2686. ra := ReservePhysicalRegister(IntermediateCode.GeneralPurposeRegister,cpuType,opRA.register,inPC);
  2687. CASE type.sizeInBits OF
  2688. 8: index := AL
  2689. |16: index := AX
  2690. |32: index := EAX
  2691. |64: index := RAX
  2692. END;
  2693. emitter.Emit2(InstructionSet.opMOV,registerOperands[index],op1);
  2694. emitter.Emit1(InstructionSet.opPUSH,opRA);
  2695. UnmapTicket(ra);
  2696. END;
  2697. END;
  2698. END EmitPush;
  2699. PROCEDURE EmitPop(CONST vop: IntermediateCode.Operand; part: LONGINT);
  2700. VAR index: LONGINT; type,cpuType: IntermediateCode.Type; op1: Assembler.Operand; ra: Ticket;
  2701. BEGIN
  2702. GetPartType(vop.type,part,type);
  2703. ASSERT(type.form IN IntermediateCode.Integer);
  2704. IF (type.sizeInBits = cpuBits) THEN
  2705. MakeOperand(vop,part,op1,NIL);
  2706. emitter.Emit1(InstructionSet.opPOP,op1);
  2707. ELSE
  2708. ASSERT(type.sizeInBits < cpuBits);
  2709. MakeOperand(vop,part,op1,NIL);
  2710. IF Assembler.IsRegisterOperand(op1) & ~((cpuBits=32) & (type.sizeInBits=8) & (op1.register >= AH)) THEN
  2711. index := op1.register MOD 32 + opRA.register;
  2712. emitter.Emit1(InstructionSet.opPOP, registerOperands[index]);
  2713. ELSE
  2714. WHILE physicalRegisters.Mapped(opRA.register) # free DO Spill(physicalRegisters.Mapped(opRA.register)) END;
  2715. IntermediateCode.InitType(cpuType, IntermediateCode.SignedInteger, SHORT(cpuBits));
  2716. ra := ReservePhysicalRegister(IntermediateCode.GeneralPurposeRegister,cpuType,opRA.register,inPC);
  2717. emitter.Emit1(InstructionSet.opPOP,opRA);
  2718. CASE type.sizeInBits OF
  2719. 8: index := AL
  2720. |16: index := AX
  2721. |32: index := EAX
  2722. |64: index := RAX
  2723. END;
  2724. emitter.Emit2(InstructionSet.opMOV, op1, registerOperands[index]);
  2725. UnmapTicket(ra);
  2726. END;
  2727. END;
  2728. END EmitPop;
  2729. PROCEDURE EmitPushFloat(CONST vop: IntermediateCode.Operand);
  2730. VAR sizeInBytes,length: LONGINT; memop: Assembler.Operand; op: Assembler.Operand;
  2731. BEGIN
  2732. MakeOperand(vop,Low,op,NIL);
  2733. length := vop.type.length;
  2734. IF (vop.mode = IntermediateCode.ModeMemory) & (vop.type.sizeInBits*length =cpuBits) THEN
  2735. emitter.Emit1(InstructionSet.opPUSH,op);
  2736. ELSE
  2737. sizeInBytes := vop.type.sizeInBits DIV 8;
  2738. length := vop.type.length;
  2739. IF sizeInBytes * length * 8 < cpuBits THEN
  2740. AllocateStack(cpuBits DIV 8);
  2741. ELSE
  2742. AllocateStack(sizeInBytes*length);
  2743. END;
  2744. Assembler.InitMem(memop, SHORTINT(sizeInBytes*length),SP,0);
  2745. IF backend.forceFPU THEN
  2746. emitter.Emit1(InstructionSet.opFLD,op); INC(fpStackPointer);
  2747. emitter.Emit1(InstructionSet.opFSTP,memop); DEC(fpStackPointer);
  2748. ELSE
  2749. Move(memop, op, vop.type)
  2750. END
  2751. END;
  2752. END EmitPushFloat;
  2753. PROCEDURE EmitPopFloat(CONST vop: IntermediateCode.Operand);
  2754. VAR sizeInBytes,length: LONGINT; memop: Assembler.Operand; op: Assembler.Operand;
  2755. BEGIN
  2756. sizeInBytes := vop.type.sizeInBits DIV 8;
  2757. length := vop.type.length;
  2758. IF (vop.mode = IntermediateCode.ModeMemory) & (vop.type.sizeInBits*length =cpuBits) THEN
  2759. MakeOperand(vop,Low,op,NIL);
  2760. emitter.Emit1(InstructionSet.opPOP,op);
  2761. ELSE
  2762. Assembler.InitMem(memop, SHORTINT(sizeInBytes*length),SP,0);
  2763. IF backend.forceFPU THEN
  2764. emitter.Emit1(InstructionSet.opFLD,memop);
  2765. INC(fpStackPointer);
  2766. MakeOperand(vop,Low,op,NIL);
  2767. emitter.Emit1(InstructionSet.opFSTP,op);
  2768. DEC(fpStackPointer);
  2769. ASSERT(sizeInBytes > 0);
  2770. ELSE
  2771. MakeOperand(vop,Low,op,NIL);
  2772. Move(op, memop, vop.type)
  2773. END;
  2774. IF sizeInBytes * length * 8 < cpuBits THEN
  2775. AllocateStack(-cpuBits DIV 8);
  2776. ELSE
  2777. AllocateStack(-sizeInBytes*length);
  2778. END;
  2779. END;
  2780. END EmitPopFloat;
  2781. PROCEDURE EmitNeg(CONST instruction: IntermediateCode.Instruction);
  2782. VAR opLow,opHigh: Assembler.Operand; minusOne: Assembler.Operand; ticketLow,ticketHigh: Ticket;
  2783. BEGIN
  2784. IF IsComplex(instruction.op1) THEN
  2785. PrepareOp2(instruction,High,opHigh,ticketHigh);
  2786. PrepareOp2(instruction,Low,opLow,ticketLow);
  2787. emitter.Emit1(InstructionSet.opNOT,opHigh);
  2788. emitter.Emit1(InstructionSet.opNEG,opLow);
  2789. Assembler.InitImm8(minusOne,-1);
  2790. emitter.Emit2(InstructionSet.opSBB,opHigh,minusOne);
  2791. FinishOp(instruction.op1,High,opHigh,ticketHigh);
  2792. FinishOp(instruction.op1,Low,opLow,ticketLow);
  2793. ELSE
  2794. EmitArithmetic2(instruction,Low,InstructionSet.opNEG);
  2795. END;
  2796. END EmitNeg;
  2797. PROCEDURE EmitNegXMM(CONST instruction: IntermediateCode.Instruction);
  2798. VAR temp, op: Assembler.Operand; ticket: Ticket;
  2799. BEGIN
  2800. PrepareOp2(instruction, Low, op, ticket);
  2801. GetTemporaryRegister(instruction.op1.type,temp);
  2802. IF instruction.op1.type.sizeInBits = 32 THEN
  2803. emitter.Emit2(InstructionSet.opXORPS, temp, temp);
  2804. emitter.Emit2(InstructionSet.opSUBPS, temp, op);
  2805. emitter.Emit2(InstructionSet.opMOVAPS, op, temp);
  2806. ELSE
  2807. emitter.Emit2(InstructionSet.opXORPD, temp, temp);
  2808. emitter.Emit2(InstructionSet.opSUBPD, temp, op);
  2809. emitter.Emit2(InstructionSet.opMOVAPS, op, temp);
  2810. END;
  2811. FinishOp(instruction.op1, Low, op, ticket);
  2812. END EmitNegXMM;
  2813. PROCEDURE EmitAbs(CONST instruction: IntermediateCode.Instruction);
  2814. VAR op1,op2: Assembler.Operand; source,imm: Assembler.Operand; eax: Ticket;
  2815. BEGIN
  2816. Assert(~IsComplex(instruction.op1),"complex Abs not supported");
  2817. IF instruction.op1.type.form = IntermediateCode.SignedInteger THEN
  2818. Spill(physicalRegisters.Mapped(EAX));
  2819. eax := ReservePhysicalRegister(IntermediateCode.GeneralPurposeRegister,IntermediateCode.int32,EAX,inPC);
  2820. MakeOperand(instruction.op1,Low,op1,NIL);
  2821. MakeOperand(instruction.op2,Low,op2,NIL);
  2822. CASE instruction.op1.type.sizeInBits OF
  2823. | IntermediateCode.Bits8: imm := Assembler.NewImm8 (7); source := opAL;
  2824. | IntermediateCode.Bits16: imm := Assembler.NewImm8 (15); source := opAX;
  2825. | IntermediateCode.Bits32: imm := Assembler.NewImm8 (31); source := opEAX;
  2826. | IntermediateCode.Bits64: imm := Assembler.NewImm8 (63); source := registerOperands[RAX];
  2827. END;
  2828. emitter.Emit2 (InstructionSet.opMOV, source,op2);
  2829. emitter.Emit2 (InstructionSet.opMOV, op1,source);
  2830. emitter.Emit2 (InstructionSet.opSAR, source, imm);
  2831. emitter.Emit2 (InstructionSet.opXOR, op1, source);
  2832. emitter.Emit2 (InstructionSet.opSUB, op1, source);
  2833. UnmapTicket(eax);
  2834. ELSE Halt("Abs does not make sense on unsigned integer")
  2835. END;
  2836. END EmitAbs;
  2837. PROCEDURE EmitAbsXMM(CONST instruction: IntermediateCode.Instruction);
  2838. VAR temp, op: Assembler.Operand; ticket: Ticket;
  2839. BEGIN
  2840. PrepareOp2(instruction, Low, op, ticket);
  2841. GetTemporaryRegister(instruction.op1.type,temp);
  2842. IF instruction.op1.type.sizeInBits = 32 THEN
  2843. emitter.Emit2(InstructionSet.opXORPS, temp, temp);
  2844. emitter.Emit2(InstructionSet.opSUBPS, temp, op);
  2845. emitter.Emit2(InstructionSet.opMAXPS, op, temp);
  2846. ELSE
  2847. emitter.Emit2(InstructionSet.opXORPD, temp, temp);
  2848. emitter.Emit2(InstructionSet.opSUBPD, temp, op);
  2849. emitter.Emit2(InstructionSet.opMAXPD, op, temp);
  2850. END;
  2851. FinishOp(instruction.op1, Low, op, ticket);
  2852. END EmitAbsXMM;
  2853. PROCEDURE EmitTrap(CONST instruction: IntermediateCode.Instruction);
  2854. VAR operand: Assembler.Operand;
  2855. BEGIN
  2856. IF instruction.op1.intValue < 80H THEN
  2857. operand := Assembler.NewImm8(instruction.op1.intValue);
  2858. ELSE
  2859. operand := Assembler.NewImm32(instruction.op1.intValue);
  2860. END;
  2861. emitter.Emit1(InstructionSet.opPUSH, operand);
  2862. emitter.Emit0(InstructionSet.opINT3);
  2863. END EmitTrap;
  2864. PROCEDURE EmitAsm(CONST instruction: IntermediateCode.Instruction);
  2865. VAR reader: Streams.StringReader; procedure: SyntaxTree.Procedure; scope: SyntaxTree.Scope;
  2866. len: LONGINT; symbol: SyntaxTree.Symbol; assembler: Assembler.Assembly;
  2867. inr, outr: IntermediateCode.Rules;
  2868. string: SyntaxTree.SourceCode;
  2869. i: LONGINT;
  2870. reg, dest: Assembler.Operand;
  2871. map: Assembler.RegisterMap;
  2872. register: LONGINT;
  2873. ticket: Ticket;
  2874. BEGIN
  2875. IF instruction.op2.mode = IntermediateCode.ModeRule THEN inr := instruction.op2.rule ELSE inr := NIL END;
  2876. IF instruction.op3.mode = IntermediateCode.ModeRule THEN outr := instruction.op3.rule ELSE outr := NIL END;
  2877. string := instruction.op1.string;
  2878. NEW(map);
  2879. IF inr # NIL THEN
  2880. FOR i := 0 TO LEN(inr)-1 DO
  2881. MakeRegister(inr[i], 0, reg);
  2882. ASSERT(map.Find(inr[i].string^) < 0);
  2883. map.Add(inr[i].string, reg.register)
  2884. END;
  2885. END;
  2886. IF outr # NIL THEN
  2887. FOR i := 0 TO LEN(outr)-1 DO
  2888. IF (map.Find(outr[i].string^) < 0) THEN
  2889. GetTemporaryRegister(outr[i].type,reg);
  2890. map.Add(outr[i].string, reg.register)
  2891. END;
  2892. END;
  2893. END;
  2894. len := Strings.Length(string^);
  2895. NEW(reader,len);
  2896. reader.Set(string^);
  2897. symbol := in.symbol;
  2898. procedure := symbol(SyntaxTree.Procedure);
  2899. scope := procedure.procedureScope;
  2900. NEW(assembler,diagnostics,emitter);
  2901. assembler.useLineNumbers := Compiler.UseLineNumbers IN backend.flags;
  2902. assembler.Assemble(reader,instruction.textPosition,scope,in,in,module,procedure.access * SyntaxTree.Public # {}, procedure.isInline, map) ;
  2903. error := error OR assembler.error;
  2904. IF outr # NIL THEN
  2905. FOR i := 0 TO LEN(outr)-1 DO
  2906. IF outr[i].mode # IntermediateCode.Undefined THEN
  2907. register := map.Find(outr[i].string^);
  2908. ticket := physicalRegisters.Mapped(register);
  2909. IF ticket.lastuse = inPC THEN UnmapTicket(ticket); physicalRegisters.AllocationHint(register) END; (* try to reuse register here *)
  2910. Assembler.InitRegister(reg, register);
  2911. MakeOperand(outr[i], Low, dest, NIL);
  2912. Move( dest, reg,outr[i].type)
  2913. END;
  2914. END;
  2915. END;
  2916. (*
  2917. IntermediateCode.SetString(instruction.op1, string);
  2918. *)
  2919. END EmitAsm;
  2920. END CodeGeneratorAMD64;
  2921. BackendAMD64= OBJECT (IntermediateBackend.IntermediateBackend)
  2922. VAR
  2923. cg: CodeGeneratorAMD64;
  2924. bits: LONGINT;
  2925. traceable: BOOLEAN;
  2926. forceFPU: BOOLEAN;
  2927. winAPIRegisters: ARRAY 4 OF LONGINT;
  2928. cRegisters: ARRAY 6 OF LONGINT;
  2929. PROCEDURE &InitBackendAMD64;
  2930. BEGIN
  2931. InitIntermediateBackend;
  2932. bits := 32;
  2933. forceFPU := FALSE;
  2934. winAPIRegisters[0] := RCX - RAX;
  2935. winAPIRegisters[1] := RDX - RAX;
  2936. winAPIRegisters[2] := R8 - RAX;
  2937. winAPIRegisters[3] := R9 - RAX;
  2938. cRegisters[0] := RDI - RAX;
  2939. cRegisters[1] := RSI - RAX;
  2940. cRegisters[2] := RDX - RAX;
  2941. cRegisters[3] := RCX - RAX;
  2942. cRegisters[4] := R8 - RAX;
  2943. cRegisters[5] := R9 - RAX;
  2944. SetName("AMD");
  2945. END InitBackendAMD64;
  2946. PROCEDURE Initialize(diagnostics: Diagnostics.Diagnostics; log: Streams.Writer; flags: SET; checker: SemanticChecker.Checker; system: Global.System);
  2947. BEGIN
  2948. Initialize^(diagnostics,log, flags,checker,system); NEW(cg, runtimeModuleName, diagnostics, SELF);
  2949. END Initialize;
  2950. PROCEDURE GetSystem(): Global.System;
  2951. VAR system: Global.System;
  2952. PROCEDURE AddRegister(CONST name: Scanner.IdentifierString; val: LONGINT);
  2953. BEGIN
  2954. Global.NewConstant(name,val,system.shortintType,system.systemScope)
  2955. END AddRegister;
  2956. PROCEDURE AddRegisters;
  2957. BEGIN
  2958. (* system constants *)
  2959. AddRegister("EAX",InstructionSet.regEAX); AddRegister("ECX", InstructionSet.regECX);
  2960. AddRegister( "EDX", InstructionSet.regEDX); AddRegister( "EBX", InstructionSet.regEBX);
  2961. AddRegister( "ESP", InstructionSet.regESP); AddRegister( "EBP", InstructionSet.regEBP);
  2962. AddRegister( "ESI", InstructionSet.regESI); AddRegister( "EDI", InstructionSet.regEDI);
  2963. AddRegister( "AX", InstructionSet.regAX); AddRegister( "CX", InstructionSet.regCX);
  2964. AddRegister( "DX", InstructionSet.regDX); AddRegister( "BX", InstructionSet.regBX);
  2965. AddRegister( "AL", InstructionSet.regAL); AddRegister( "CL", InstructionSet.regCL);
  2966. AddRegister( "DL", InstructionSet.regDL); AddRegister( "BL", InstructionSet.regBL);
  2967. AddRegister( "AH", InstructionSet.regAH); AddRegister( "CH", InstructionSet.regCH);
  2968. AddRegister( "DH", InstructionSet.regDH); AddRegister( "BH", InstructionSet.regBH);
  2969. AddRegister( "RAX", InstructionSet.regRAX); AddRegister( "RCX", InstructionSet.regRCX);
  2970. AddRegister( "RDX", InstructionSet.regRDX); AddRegister( "RBX", InstructionSet.regRBX);
  2971. AddRegister( "RSP", InstructionSet.regRSP); AddRegister( "RBP", InstructionSet.regRBP);
  2972. AddRegister( "RSI", InstructionSet.regRSI); AddRegister( "RDI", InstructionSet.regRDI);
  2973. AddRegister( "R8", InstructionSet.regR8); AddRegister( "R9", InstructionSet.regR9);
  2974. AddRegister( "R10", InstructionSet.regR10); AddRegister( "R11", InstructionSet.regR11);
  2975. AddRegister( "R12", InstructionSet.regR12); AddRegister( "R13", InstructionSet.regR13);
  2976. AddRegister( "R14", InstructionSet.regR14); AddRegister( "R15", InstructionSet.regR15);
  2977. AddRegister( "R8D", InstructionSet.regR8D); AddRegister( "R9D", InstructionSet.regR9D);
  2978. AddRegister( "R10D", InstructionSet.regR10D); AddRegister( "R11D", InstructionSet.regR11D);
  2979. AddRegister( "R12D", InstructionSet.regR12D); AddRegister( "R13D", InstructionSet.regR13D);
  2980. AddRegister( "R14D", InstructionSet.regR14D); AddRegister( "R15D", InstructionSet.regR15D);
  2981. AddRegister( "R8W", InstructionSet.regR8W); AddRegister( "R9W", InstructionSet.regR9W);
  2982. AddRegister( "R10W", InstructionSet.regR10W); AddRegister( "R11W", InstructionSet.regR11W);
  2983. AddRegister( "R12W", InstructionSet.regR12W); AddRegister( "R13W", InstructionSet.regR13W);
  2984. AddRegister( "R14W", InstructionSet.regR14W); AddRegister( "R15W", InstructionSet.regR15W);
  2985. AddRegister( "R8B", InstructionSet.regR8B); AddRegister( "R9B", InstructionSet.regR9B);
  2986. AddRegister( "R10B", InstructionSet.regR10B); AddRegister( "R11B", InstructionSet.regR11B);
  2987. AddRegister( "R12B", InstructionSet.regR12B); AddRegister( "R13B", InstructionSet.regR13B);
  2988. AddRegister( "R14B", InstructionSet.regR14B); AddRegister( "R15B", InstructionSet.regR15B);
  2989. END AddRegisters;
  2990. BEGIN
  2991. IF system = NIL THEN
  2992. IF bits=32 THEN
  2993. NEW(system,8,8,32, 8,32,32,32,64,cooperative);
  2994. Global.SetDefaultDeclarations(system,8);
  2995. Global.SetDefaultOperators(system);
  2996. ELSE
  2997. NEW(system,8,8,64,8,64,64,64,128,cooperative);
  2998. Global.SetDefaultDeclarations(system,8);
  2999. Global.SetDefaultOperators(system);
  3000. END;
  3001. system.SetRegisterPassCallback(CanPassInRegister);
  3002. AddRegisters
  3003. END;
  3004. RETURN system
  3005. END GetSystem;
  3006. (* return number of general purpose registery used as parameter register in calling convention *)
  3007. PROCEDURE NumberParameterRegisters*(callingConvention: SyntaxTree.CallingConvention): SIZE;
  3008. BEGIN
  3009. IF bits = 32 THEN
  3010. RETURN 0;
  3011. ELSE
  3012. CASE callingConvention OF
  3013. |SyntaxTree.WinAPICallingConvention: RETURN 4;
  3014. |SyntaxTree.CCallingConvention, SyntaxTree.DarwinCCallingConvention: RETURN 6;
  3015. ELSE
  3016. RETURN 0;
  3017. END;
  3018. END
  3019. END NumberParameterRegisters;
  3020. (* returns the following register (or part thereof)
  3021. 0: regRAX;
  3022. 1: regRCX;
  3023. 2: regRDX;
  3024. 3: regRBX;
  3025. 4: regRSP;
  3026. 5: regRBP;
  3027. 6: regRSI;
  3028. 7: regRDI;
  3029. 8 .. 15: regRx;
  3030. *)
  3031. PROCEDURE HardwareIntegerRegister(index: LONGINT; sizeInBits: LONGINT): LONGINT;
  3032. BEGIN
  3033. index := index MOD 32;
  3034. sizeInBits := sizeInBits DIV 8;
  3035. WHILE sizeInBits > 1 DO (* jump to register section that corresponds to the number of bits *)
  3036. INC(index,32);
  3037. sizeInBits := sizeInBits DIV 2;
  3038. END;
  3039. RETURN index
  3040. END HardwareIntegerRegister;
  3041. PROCEDURE HardwareFloatRegister(index: LONGINT; sizeInBits: LONGINT): LONGINT;
  3042. BEGIN
  3043. ASSERT((sizeInBits = 32) OR (sizeInBits = 64));
  3044. RETURN XMM0 + index;
  3045. END HardwareFloatRegister;
  3046. PROCEDURE ParameterRegister(callingConvention: SyntaxTree.CallingConvention; type: IntermediateCode.Type; index: LONGINT): LONGINT;
  3047. VAR size: LONGINT;
  3048. BEGIN
  3049. IF type.form IN IntermediateCode.Integer THEN
  3050. CASE callingConvention OF
  3051. |SyntaxTree.WinAPICallingConvention: index := winAPIRegisters[index];
  3052. |SyntaxTree.CCallingConvention, SyntaxTree.DarwinCCallingConvention: index := cRegisters[index]
  3053. END;
  3054. RETURN HardwareIntegerRegister(RAX + index, type.sizeInBits)
  3055. ELSIF type.form = IntermediateCode.Float THEN
  3056. RETURN HardwareFloatRegister(index, type.sizeInBits)
  3057. ELSE
  3058. HALT(100);
  3059. END;
  3060. END ParameterRegister;
  3061. PROCEDURE SupportedInstruction(CONST instruction: IntermediateCode.Instruction; VAR moduleName, procedureName: ARRAY OF CHAR): BOOLEAN;
  3062. BEGIN
  3063. RETURN cg.Supported(instruction,moduleName,procedureName);
  3064. END SupportedInstruction;
  3065. PROCEDURE GenerateBinary(module: Sections.Module; dump: Streams.Writer);
  3066. VAR
  3067. in: Sections.Section;
  3068. out: BinaryCode.Section;
  3069. name: Basic.SegmentedName;
  3070. procedure: SyntaxTree.Procedure;
  3071. i, j, initialSectionCount: LONGINT;
  3072. (* recompute fixup positions and assign binary sections *)
  3073. PROCEDURE PatchFixups(section: BinaryCode.Section);
  3074. VAR resolved: BinaryCode.Section; fixup: BinaryCode.Fixup; displacement,symbolOffset: LONGINT; in: IntermediateCode.Section;
  3075. symbol: Sections.Section;
  3076. BEGIN
  3077. fixup := section.fixupList.firstFixup;
  3078. WHILE fixup # NIL DO
  3079. symbol := module.allSections.FindByName(fixup.symbol.name);
  3080. IF (symbol # NIL) & (symbol(IntermediateCode.Section).resolved # NIL) THEN
  3081. resolved := symbol(IntermediateCode.Section).resolved(BinaryCode.Section);
  3082. in := symbol(IntermediateCode.Section);
  3083. symbolOffset := fixup.symbolOffset;
  3084. IF symbolOffset = in.pc THEN
  3085. displacement := resolved.pc
  3086. ELSIF (symbolOffset # 0) THEN
  3087. ASSERT(in.pc > symbolOffset);
  3088. displacement := in.instructions[symbolOffset].pc;
  3089. ELSE
  3090. displacement := 0;
  3091. END;
  3092. fixup.SetSymbol(fixup.symbol.name,fixup.symbol.fingerprint,0,fixup.displacement+displacement);
  3093. END;
  3094. fixup := fixup.nextFixup;
  3095. END;
  3096. END PatchFixups;
  3097. BEGIN
  3098. cg.SetModule(module);
  3099. FOR i := 0 TO module.allSections.Length() - 1 DO
  3100. in := module.allSections.GetSection(i);
  3101. IF in.type = Sections.InlineCodeSection THEN
  3102. name := in.name;
  3103. out := ResolvedSection(in(IntermediateCode.Section));
  3104. cg.Section(in(IntermediateCode.Section),out);
  3105. procedure := in.symbol(SyntaxTree.Procedure);
  3106. IF procedure.procedureScope.body.code # NIL THEN
  3107. procedure.procedureScope.body.code.SetBinaryCode(out.os.bits);
  3108. END;
  3109. END
  3110. END;
  3111. initialSectionCount := 0;
  3112. REPEAT
  3113. j := initialSectionCount;
  3114. initialSectionCount := module.allSections.Length() ;
  3115. FOR i := j TO initialSectionCount - 1 DO
  3116. in := module.allSections.GetSection(i);
  3117. IF (in.type # Sections.InlineCodeSection) & (in(IntermediateCode.Section).resolved = NIL) THEN
  3118. name := in.name;
  3119. out := ResolvedSection(in(IntermediateCode.Section));
  3120. cg.Section(in(IntermediateCode.Section),out);
  3121. IF out.os.type = Sections.VarSection THEN
  3122. IF out.pc = 1 THEN out.SetAlignment(FALSE,1)
  3123. ELSIF out.pc = 2 THEN out.SetAlignment(FALSE,2)
  3124. ELSIF (out.pc > 4) & (bits > 32) THEN out.SetAlignment(FALSE,8)
  3125. ELSIF (out.pc > 2) THEN out.SetAlignment(FALSE,4)
  3126. END;
  3127. ELSIF out.os.type = Sections.ConstSection THEN
  3128. out.SetAlignment(FALSE,bits DIV 8);
  3129. END;
  3130. END
  3131. END
  3132. UNTIL initialSectionCount = module.allSections.Length(); (* process remaining sections that have been added during traversal of sections *)
  3133. (*
  3134. FOR i := 0 TO module.allSections.Length() - 1 DO
  3135. in := module.allSections.GetSection(i);
  3136. IF in.kind = Sections.CaseTableKind THEN
  3137. IF in(IntermediateCode.Section).resolved = NIL THEN
  3138. out := ResolvedSection(in(IntermediateCode.Section));
  3139. cg.Section(in(IntermediateCode.Section),out);
  3140. END
  3141. END
  3142. END;
  3143. *)
  3144. FOR i := 0 TO module.allSections.Length() - 1 DO
  3145. in := module.allSections.GetSection(i);
  3146. PatchFixups(in(IntermediateCode.Section).resolved)
  3147. END;
  3148. (*
  3149. FOR i := 0 TO module.allSections.Length() - 1 DO
  3150. in := module.allSections.GetSection(i);
  3151. IF in.kind = Sections.CaseTableKind THEN
  3152. PatchFixups(in(IntermediateCode.Section).resolved)
  3153. END
  3154. END;
  3155. *)
  3156. IF cg.error THEN Error("",Basic.invalidPosition, Diagnostics.Invalid,"") END;
  3157. END GenerateBinary;
  3158. (* genasm *)
  3159. PROCEDURE ProcessIntermediateCodeModule*(intermediateCodeModule: Formats.GeneratedModule): Formats.GeneratedModule;
  3160. VAR
  3161. result: Formats.GeneratedModule;
  3162. BEGIN
  3163. ASSERT(intermediateCodeModule IS Sections.Module);
  3164. result := ProcessIntermediateCodeModule^(intermediateCodeModule);
  3165. IF ~error THEN
  3166. GenerateBinary(result(Sections.Module),dump);
  3167. IF dump # NIL THEN
  3168. dump.Ln; dump.Ln;
  3169. dump.String(";------------------ binary code -------------------"); dump.Ln;
  3170. IF (traceString="") OR (traceString="*") THEN
  3171. result.Dump(dump);
  3172. dump.Update
  3173. ELSE
  3174. Sections.DumpFiltered(dump, result(Sections.Module), traceString);
  3175. dump.Update;
  3176. END
  3177. END;
  3178. END;
  3179. RETURN result
  3180. FINALLY
  3181. IF dump # NIL THEN
  3182. dump.Ln; dump.Ln;
  3183. dump.String("; ------------------ rescued code (code generation trapped) -------------------"); dump.Ln;
  3184. IF (traceString="") OR (traceString="*") THEN
  3185. result.Dump(dump);
  3186. dump.Update
  3187. ELSE
  3188. Sections.DumpFiltered(dump, result(Sections.Module), traceString);
  3189. dump.Update;
  3190. END
  3191. END;
  3192. HALT(100); (* do not continue compiling after trap *)
  3193. RETURN result
  3194. END ProcessIntermediateCodeModule;
  3195. PROCEDURE FindPC(x: SyntaxTree.Module; CONST sectionName: ARRAY OF CHAR; sectionOffset: LONGINT);
  3196. VAR
  3197. section: Sections.Section; binarySection: BinaryCode.Section; label: BinaryCode.LabelList; module: Formats.GeneratedModule;
  3198. i: LONGINT; pooledName: Basic.SegmentedName;
  3199. BEGIN
  3200. module := ProcessSyntaxTreeModule(x);
  3201. Basic.ToSegmentedName(sectionName, pooledName);
  3202. i := 0;
  3203. REPEAT
  3204. section := module(Sections.Module).allSections.GetSection(i);
  3205. INC(i);
  3206. UNTIL (i = module(Sections.Module).allSections.Length()) OR (section.name = pooledName);
  3207. IF section.name # pooledName THEN
  3208. Basic.Error(diagnostics, module.module.sourceName,Basic.invalidPosition, " could not locate pc");
  3209. ELSE
  3210. binarySection := section(IntermediateCode.Section).resolved;
  3211. IF binarySection # NIL THEN
  3212. label := binarySection.labels;
  3213. WHILE (label # NIL) & (label.offset >= sectionOffset) DO
  3214. label := label.prev;
  3215. END;
  3216. END;
  3217. IF label # NIL THEN
  3218. Basic.Information(diagnostics, module.module.sourceName,label.position, " pc position");
  3219. ELSE
  3220. Basic.Error(diagnostics, module.module.sourceName,Basic.invalidPosition, " could not locate pc");
  3221. END;
  3222. END;
  3223. END FindPC;
  3224. PROCEDURE CanPassInRegister*(type: SyntaxTree.Type): BOOLEAN;
  3225. VAR length: LONGINT; baseType: SyntaxTree.Type; b: BOOLEAN;
  3226. BEGIN
  3227. b := SemanticChecker.IsStaticMathArray(type, length, baseType) & (baseType IS SyntaxTree.FloatType) &
  3228. (baseType.sizeInBits <= 32) & (length = 4);
  3229. b := b OR SemanticChecker.IsStaticMathArray(type, length, baseType) & (baseType IS SyntaxTree.CharacterType) &
  3230. (baseType.sizeInBits = 8) & (length = 4);
  3231. b := b OR SemanticChecker.IsStaticArray(type, baseType, length) & (baseType.resolved IS SyntaxTree.CharacterType) &
  3232. (baseType.resolved.sizeInBits = 8) & (length = 4);
  3233. RETURN b
  3234. END CanPassInRegister;
  3235. PROCEDURE GetDescription*(VAR instructionSet: ARRAY OF CHAR);
  3236. BEGIN instructionSet := "AMD";
  3237. END GetDescription;
  3238. PROCEDURE DefineOptions(options: Options.Options);
  3239. BEGIN
  3240. options.Add(0X,"bits",Options.Integer);
  3241. options.Add(0X,"traceable", Options.Flag);
  3242. options.Add(0X,"useFPU", Options.Flag);
  3243. DefineOptions^(options);
  3244. END DefineOptions;
  3245. PROCEDURE GetOptions(options: Options.Options);
  3246. BEGIN
  3247. IF ~options.GetInteger("bits",bits) THEN bits := 32 END;
  3248. traceable := options.GetFlag("traceable");
  3249. forceFPU := options.GetFlag("useFPU");
  3250. GetOptions^(options);
  3251. END GetOptions;
  3252. PROCEDURE DefaultObjectFileFormat(): Formats.ObjectFileFormat;
  3253. BEGIN RETURN ObjectFileFormat.Get();
  3254. END DefaultObjectFileFormat;
  3255. PROCEDURE DefaultSymbolFileFormat(): Formats.SymbolFileFormat;
  3256. BEGIN
  3257. RETURN NIL
  3258. END DefaultSymbolFileFormat;
  3259. END BackendAMD64;
  3260. (** the number of regular sections in a section list **)
  3261. PROCEDURE RegularSectionCount(sectionList: Sections.SectionList): LONGINT;
  3262. VAR
  3263. section: Sections.Section;
  3264. i, result: LONGINT;
  3265. BEGIN
  3266. result := 0;
  3267. FOR i := 0 TO sectionList.Length() - 1 DO
  3268. section := sectionList.GetSection(i);
  3269. INC(result)
  3270. END;
  3271. RETURN result
  3272. END RegularSectionCount;
  3273. PROCEDURE Assert(b: BOOLEAN; CONST s: ARRAY OF CHAR);
  3274. BEGIN
  3275. ASSERT(b,100);
  3276. END Assert;
  3277. PROCEDURE Halt(CONST s: ARRAY OF CHAR);
  3278. BEGIN
  3279. HALT(100);
  3280. END Halt;
  3281. PROCEDURE ResolvedSection(in: IntermediateCode.Section): BinaryCode.Section;
  3282. VAR section: BinaryCode.Section;
  3283. BEGIN
  3284. IF in.resolved = NIL THEN
  3285. NEW(section,in.type, 8, in.name,in.comments # NIL,FALSE);
  3286. section.SetAlignment(in.fixed, in.positionOrAlignment);
  3287. in.SetResolved(section);
  3288. ELSE
  3289. section := in.resolved
  3290. END;
  3291. RETURN section
  3292. END ResolvedSection;
  3293. PROCEDURE Init;
  3294. VAR i: LONGINT;
  3295. BEGIN
  3296. FOR i := 0 TO LEN(registerOperands)-1 DO
  3297. Assembler.InitRegister(registerOperands[i],i);
  3298. END;
  3299. opEAX := registerOperands[EAX];
  3300. opEBX := registerOperands[EBX];
  3301. opECX := registerOperands[ECX];
  3302. opEDX := registerOperands[EDX];
  3303. opESI := registerOperands[ESI];
  3304. opEDI := registerOperands[EDI];
  3305. opEBP := registerOperands[EBP];
  3306. opESP := registerOperands[ESP];
  3307. opRSP := registerOperands[RSP];
  3308. opRBP := registerOperands[RBP];
  3309. opAX := registerOperands[AX];
  3310. opBX := registerOperands[BX];
  3311. opCX := registerOperands[CX];
  3312. opDX := registerOperands[DX];
  3313. opSI := registerOperands[SI];
  3314. opDI := registerOperands[DI];
  3315. opAL := registerOperands[AL];
  3316. opBL := registerOperands[BL];
  3317. opCL := registerOperands[CL];
  3318. opDL := registerOperands[DL];
  3319. opAH := registerOperands[AH];
  3320. opBH := registerOperands[BH];
  3321. opCH := registerOperands[CH];
  3322. opDH := registerOperands[DH];
  3323. opST0 := registerOperands[ST0];
  3324. NEW(unusable); NEW(blocked); NEW(split); free := NIL;
  3325. END Init;
  3326. PROCEDURE Get*(): Backend.Backend;
  3327. VAR backend: BackendAMD64;
  3328. BEGIN NEW(backend); RETURN backend
  3329. END Get;
  3330. PROCEDURE Trace*;
  3331. BEGIN
  3332. TRACE(traceStackSize);
  3333. END Trace;
  3334. BEGIN
  3335. traceStackSize := 0;
  3336. Init;
  3337. usePool := Machine.NumberOfProcessors()>1;
  3338. END FoxAMDBackend.
  3339. SystemTools.FreeDownTo FoxAMDBackend ~