 felixf
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0f0961c3b5
patch value at index for port arrays in AC3
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9 роки тому |
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felixf
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311a5949d3
Patched a problem with instruction width (18 became 32 when data sections were present)
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9 роки тому |
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felixf
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f2ddb66c26
Ignore unsuccesful patching.
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9 роки тому |
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felixf
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1b4f36398e
TRM code generation works for small example -- ports are not yet assigned in software and properties are still unset
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9 роки тому |
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felixf
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e7ca9ce59f
removed dependencies on module ActiveCells, Hardware and TRMTools
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9 роки тому |
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felixf
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32a1cd1bb0
Added WriteCodeAndDataFiles
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9 роки тому |
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felixf
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09307c1367
Simplified IntermediateLinker for ActiveCells3 -- intermediate state!
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9 роки тому |
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felixf
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7e7acc530f
Merged modifications from ActiveCells3
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10 роки тому |
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felixf
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c4d4cb6df9
Moved TRM backend from OC to A2 trunk.
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10 роки тому |
