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Fixed inconsistently documented instructions

git-svn-id: https://svn.inf.ethz.ch/svn/lecturers/a2/trunk@7574 8c9fc860-2736-0410-a75d-ab315db34111
negelef 7 lat temu
rodzic
617ad335c7
commit
fb7c31fef0
1 zmienionych plików z 18 dodań i 18 usunięć
Widok podzielony Pokaż statystyki zmian
  1. 18 18
      source/FoxAMD64InstructionSet.Mod

+ 18 - 18
source/FoxAMD64InstructionSet.Mod
Wyświetl plik 

@@ -4399,7 +4399,7 @@ VAR
 
 		AddInstructionV(opVCOMISD,"xmm1,xmm2/mem64","C4 RXB.00001 X.src.X.01 2F /r");
 
 		AddInstructionV(opVCOMISS,"xmm1,xmm2/mem32","C4 RXB.00001 X.src.X.00 2F /r");
 
 		AddInstructionV(opVCVTDQ2PD,"xmm1,xmm2/mem64","C4 RXB.00001 X.1111.0.10 E6 /r");
 
-		AddInstructionV(opVCVTDQ2PD,"ymm1,ymm2/mem256","C4 RXB.00001 X.1111.1.10 E6 /r");
 
+		AddInstructionV(opVCVTDQ2PD,"ymm1,ymm2/mem128","C4 RXB.00001 X.1111.1.10 E6 /r");
 
 		AddInstructionV(opVCVTDQ2PS,"xmm1,xmm2/mem128","C4 RXB.00001 X.1111.0.00 5B /r");
 
 		AddInstructionV(opVCVTDQ2PS,"ymm1,ymm2/mem256","C4 RXB.00001 X.1111.1.00 5B /r");
 
 		AddInstructionV(opVCVTPD2DQ,"xmm1,xmm2/mem128","C4 RXB.00001 X.1111.0.11 E6 /r");
 
@@ -4423,7 +4423,7 @@ VAR
 
 		AddInstructionV(opVCVTSI2SS,"xmm1,xmm2,reg64/mem64","C4 RXB.00001 1.src.X.10 2A /r");
 
 		AddInstructionV(opVCVTSS2SD,"xmm1,xmm2,xmm3/mem64","C4 RXB.00001 X.src.X.10 5A /r");
 
 		AddInstructionV(opVCVTSS2SI,"reg32,xmm1/mem32","C4 RXB.00001 0.1111.X.10 2D /r");
 
-		AddInstructionV(opVCVTSS2SI,"reg64,xmm1/mem64","C4 RXB.00001 1.1111.X.10 2D /r");
 
+		AddInstructionV(opVCVTSS2SI,"reg64,xmm1/mem32","C4 RXB.00001 1.1111.X.10 2D /r");
 
 		AddInstructionV(opVCVTTPD2DQ,"xmm1,xmm2/mem128","C4 RXB.00001 X.1111.0.01 E6 /r");
 
 		AddInstructionV(opVCVTTPD2DQ,"xmm1,ymm2/mem256","C4 RXB.00001 X.1111.1.01 E6 /r");
 
 		AddInstructionV(opVCVTTPS2DQ,"xmm1,xmm2/mem128","C4 RXB.00001 X.1111.0.10 5B /r");
 
@@ -4431,7 +4431,7 @@ VAR
 
 		AddInstructionV(opVCVTTSD2SI,"reg32,xmm2/mem64","C4 RXB.00001 0.1111.X.11 2C /r");
 
 		AddInstructionV(opVCVTTSD2SI,"reg64,xmm2/mem64","C4 RXB.00001 1.1111.X.11 2C /r");
 
 		AddInstructionV(opVCVTTSS2SI,"reg32,xmm1/mem32","C4 RXB.00001 0.1111.X.10 2C /r");
 
-		AddInstructionV(opVCVTTSS2SI,"reg64,xmm1/mem64","C4 RXB.00001 1.1111.X.10 2C /r");
 
+		AddInstructionV(opVCVTTSS2SI,"reg64,xmm1/mem32","C4 RXB.00001 1.1111.X.10 2C /r");
 
 		AddInstructionV(opVDIVPD,"xmm1,xmm2,xmm3/mem128","C4 RXB.00001 X.src.0.01 5E /r");
 
 		AddInstructionV(opVDIVPD,"ymm1,ymm2,ymm3/mem256","C4 RXB.00001 X.src.1.01 5E /r");
 
 		AddInstructionV(opVDIVPS,"xmm1,xmm2,xmm3/mem128","C4 RXB.00001 X.src.0.00 5E /r");
 
@@ -4441,26 +4441,26 @@ VAR
 
 		AddInstructionV(opVDPPD,"xmm1,xmm2,xmm3/mem128,imm8","C4 RXB.00011 X.src.0.01 41 /r ib");
 
 		AddInstructionV(opVDPPS,"xmm1,xmm2,xmm3/mem128,imm8","C4 RXB.00011 X.src.0.01 40 /r ib");
 
 		AddInstructionV(opVDPPS,"ymm1,ymm2,ymm3/mem256,imm8","C4 RXB.00011 X.src.1.01 40 /r ib");
 
-		AddInstructionV(opVEXTRACTF128,"xmm/mem128,ymm,imm8","C4 RXB.03 0.1111.1.01 19 /r ib");
 
+		AddInstructionV(opVEXTRACTF128,"xmm1/mem128,ymm2,imm8","C4 RXB.03 0.1111.1.01 19 /r ib");
 
 		AddInstructionV(opVEXTRACTI128,"xmm1/mem128,ymm2,imm8","C4 RXB.03 0.1111.1.01 39 /r ib");
 
 		AddInstructionV(opVEXTRACTPS,"reg32/mem32,xmm1,imm8","C4 RXB.00011 X.1111.0.01 17 /r ib");
 
 		AddInstructionV(opVFMADD132PD,"xmm0,xmm1,xmm2/m128","C4 RXB.02 1.src2.0.01 98 /r");
 
 		AddInstructionV(opVFMADD132PD,"ymm0,ymm1,ymm2/m256","C4 RXB.02 1.src2.1.01 98 /r");
 
 		AddInstructionV(opVFMADD132PS,"xmm0,xmm1,xmm2/m128","C4 RXB.02 0.src2.0.01 98 /r");
 
 		AddInstructionV(opVFMADD132PS,"ymm0,ymm1,ymm2/m256","C4 RXB.02 0.src2.1.01 98 /r");
 
-		AddInstructionV(opVFMADD132SD,"xmm0,xmm1,xmm2/m128","C4 RXB.02 1.src2.X.01 99 /r");
 
+		AddInstructionV(opVFMADD132SD,"xmm0,xmm1,xmm2/m64","C4 RXB.02 1.src2.X.01 99 /r");
 
 		AddInstructionV(opVFMADD132SS,"xmm1,xmm2,xmm3/mem32","C4 RXB.02 0.src2.X.01 99 /r");
 
 		AddInstructionV(opVFMADD213PD,"xmm0,xmm1,xmm2/m128","C4 RXB.02 1.src2.0.01 A8 /r");
 
 		AddInstructionV(opVFMADD213PD,"ymm0,ymm1,ymm2/m256","C4 RXB.02 1.src2.1.01 A8 /r");
 
 		AddInstructionV(opVFMADD213PS,"xmm0,xmm1,xmm2/m128","C4 RXB.02 0.src2.0.01 A8 /r");
 
 		AddInstructionV(opVFMADD213PS,"ymm0,ymm1,ymm2/m256","C4 RXB.02 0.src2.1.01 A8 /r");
 
-		AddInstructionV(opVFMADD213SD,"xmm0,xmm1,xmm2/m128","C4 RXB.02 1.src2.X.01 A9 /r");
 
+		AddInstructionV(opVFMADD213SD,"xmm0,xmm1,xmm2/m64","C4 RXB.02 1.src2.X.01 A9 /r");
 
 		AddInstructionV(opVFMADD213SS,"xmm1,xmm2,xmm3/mem32","C4 RXB.02 0.src2.X.01 A9 /r");
 
 		AddInstructionV(opVFMADD231PD,"xmm0,xmm1,xmm2/m128","C4 RXB.02 1.src2.0.01 B8 /r");
 
 		AddInstructionV(opVFMADD231PD,"ymm0,ymm1,ymm2/m256","C4 RXB.02 1.src2.1.01 B8 /r");
 
 		AddInstructionV(opVFMADD231PS,"xmm0,xmm1,xmm2/m128","C4 RXB.02 0.src2.0.01 B8 /r");
 
 		AddInstructionV(opVFMADD231PS,"ymm0,ymm1,ymm2/m256","C4 RXB.02 0.src2.1.01 B8 /r");
 
-		AddInstructionV(opVFMADD231SD,"xmm0,xmm1,xmm2/m128","C4 RXB.02 1.src2.X.01 B9 /r");
 
+		AddInstructionV(opVFMADD231SD,"xmm0,xmm1,xmm2/m64","C4 RXB.02 1.src2.X.01 B9 /r");
 
 		AddInstructionV(opVFMADD231SS,"xmm1,xmm2,xmm3/mem32","C4 RXB.02 0.src2.X.01 B9 /r");
 
 		AddInstructionV(opVFMADDPD,"xmm1,xmm2,xmm3/mem128,xmm4","C4 RXB.03 0.src1.0.01 69 /r /is4");
 
 		AddInstructionV(opVFMADDPD,"ymm1,ymm2,ymm3/mem256,ymm4","C4 RXB.03 0.src1.1.01 69 /r /is4");
 
@@ -4470,8 +4470,8 @@ VAR
 
 		AddInstructionV(opVFMADDPS,"ymm1,ymm2,ymm3/mem256,ymm4","C4 RXB.03 0.src1.1.01 68 /r /is4");
 
 		AddInstructionV(opVFMADDPS,"xmm1,xmm2,xmm3,xmm4/mem128","C4 RXB.03 1.src1.0.01 68 /r /is4");
 
 		AddInstructionV(opVFMADDPS,"ymm1,ymm2,ymm3,ymm4/mem256","C4 RXB.03 1.src1.1.01 68 /r /is4");
 
-		AddInstructionV(opVFMADDSD,"xmm1,xmm2,xmm3/mem128,xmm4","C4 RXB.03 0.src1.X.01 6B /r /is4");
 
-		AddInstructionV(opVFMADDSD,"xmm1,xmm2,xmm3,xmm4/mem128","C4 RXB.03 1.src1.X.01 6B /r /is4");
 
+		AddInstructionV(opVFMADDSD,"xmm1,xmm2,xmm3/mem64,xmm4","C4 RXB.03 0.src1.X.01 6B /r /is4");
 
+		AddInstructionV(opVFMADDSD,"xmm1,xmm2,xmm3,xmm4/mem64","C4 RXB.03 1.src1.X.01 6B /r /is4");
 
 		AddInstructionV(opVFMADDSS,"xmm1,xmm2,xmm3/mem32,xmm4","C4 RXB.03 0.src1.X.01 6A /r /is4");
 
 		AddInstructionV(opVFMADDSS,"xmm1,xmm2,xmm3,xmm4/mem32","C4 RXB.03 1.src1.X.01 6A /r /is4");
 
 		AddInstructionV(opVFMADDSUB132PD,"xmm1,xmm2,xmm3/mem128","C4 RXB.02 1.src2.0.01 96 /r");
 
@@ -5104,24 +5104,24 @@ VAR
 
 		AddInstructionV(opVRCPPS,"ymm1,ymm2/mem256","C4 RXB.01 X.1111.1.00 53 /r");
 
 		AddInstructionV(opVRCPSS,"xmm1,xmm2,xmm3/mem128","C4 RXB.01 X.src1.X.10 53 /r");
 
 		AddInstructionV(opVROUNDPD,"xmm1,xmm2/mem128,imm8","C4 RXB.03 X.1111.0.01 09 /r ib");
 
-		AddInstructionV(opVROUNDPD,"ymm1,xmm2/mem256,imm8","C4 RXB.03 X.1111.1.01 09 /r ib");
 
+		AddInstructionV(opVROUNDPD,"ymm1,ymm2/mem256,imm8","C4 RXB.03 X.1111.1.01 09 /r ib");
 
 		AddInstructionV(opVROUNDPS,"xmm1,xmm2/mem128,imm8","C4 RXB.03 X.1111.0.01 08 /r ib");
 
-		AddInstructionV(opVROUNDPS,"ymm1,xmm2/mem256,imm8","C4 RXB.03 X.1111.1.01 08 /r ib");
 
+		AddInstructionV(opVROUNDPS,"ymm1,ymm2/mem256,imm8","C4 RXB.03 X.1111.1.01 08 /r ib");
 
 		AddInstructionV(opVROUNDSD,"xmm1,xmm2,xmm3/mem64,imm8","C4 RXB.03 X.src1.X.01 0B /r ib");
 
-		AddInstructionV(opVROUNDSS,"xmm1,xmm2,xmm3/mem64,imm8","C4 RXB.03 X.src1.X.01 0A /r ib");
 
+		AddInstructionV(opVROUNDSS,"xmm1,xmm2,xmm3/mem32,imm8","C4 RXB.03 X.src1.X.01 0A /r ib");
 
 		AddInstructionV(opVRSQRTPS,"xmm1,xmm2/mem128","C4 RXB.01 X.1111.0.00 52 /r");
 
 		AddInstructionV(opVRSQRTPS,"ymm1,ymm2/mem256","C4 RXB.01 X.1111.1.00 52 /r");
 
-		AddInstructionV(opVRSQRTSS,"xmm1,xmm2,xmm3/mem128","C4 RXB.01 X.src1.X.10 52 /r");
 
-		AddInstructionV(opVSHUFPD,"xmm1,xmm2,xmm3/mem128,imm8","C4 RXB.01 X.src1.0.01 C6 /r");
 
-		AddInstructionV(opVSHUFPD,"ymm1,ymm2,ymm3/mem256,imm8","C4 RXB.01 X.src1.1.01 C6 /r");
 
-		AddInstructionV(opVSHUFPS,"xmm1,xmm2,xmm3/mem128,imm8","C4 RXB.01 X.src1.0.00 C6 /r");
 
-		AddInstructionV(opVSHUFPS,"ymm1,ymm2,ymm3/mem256,imm8","C4 RXB.01 X.src1.1.00 C6 /r");
 
+		AddInstructionV(opVRSQRTSS,"xmm1,xmm2,xmm3/mem32","C4 RXB.01 X.src1.X.10 52 /r");
 
+		AddInstructionV(opVSHUFPD,"xmm1,xmm2,xmm3/mem128,imm8","C4 RXB.01 X.src1.0.01 C6 /r ib");
 
+		AddInstructionV(opVSHUFPD,"ymm1,ymm2,ymm3/mem256,imm8","C4 RXB.01 X.src1.1.01 C6 /r ib");
 
+		AddInstructionV(opVSHUFPS,"xmm1,xmm2,xmm3/mem128,imm8","C4 RXB.01 X.src1.0.00 C6 /r ib");
 
+		AddInstructionV(opVSHUFPS,"ymm1,ymm2,ymm3/mem256,imm8","C4 RXB.01 X.src1.1.00 C6 /r ib");
 
 		AddInstructionV(opVSQRTPD,"xmm1,xmm2/mem128","C4 RXB.01 X.1111.0.01 51 /r");
 
 		AddInstructionV(opVSQRTPD,"ymm1,ymm2/mem256","C4 RXB.01 X.1111.1.01 51 /r");
 
 		AddInstructionV(opVSQRTPS,"xmm1,xmm2/mem128","C4 RXB.01 X.1111.0.00 51 /r");
 
 		AddInstructionV(opVSQRTPS,"ymm1,ymm2/mem256","C4 RXB.01 X.1111.1.00 51 /r");
 
 		AddInstructionV(opVSQRTSD,"xmm1,xmm2,xmm3/mem64","C4 RXB.01 X.src1.X.11 51 /r");
 
-		AddInstructionV(opVSQRTSS,"xmm1,xmm2,xmm3/mem64","C4 RXB.01 X.src1.X.10 51 /r");
 
+		AddInstructionV(opVSQRTSS,"xmm1,xmm2,xmm3/mem32","C4 RXB.01 X.src1.X.10 51 /r");
 
 		AddInstructionV(opVSTMXCSR,"mem32","C4 RXB.01 X.1111.0.00 AE /3");
 
 		AddInstructionV(opVSUBPD,"xmm1,xmm2,xmm3/mem128","C4 RXB.01 X.src1.0.01 5C /r");
 
 		AddInstructionV(opVSUBPD,"ymm1,ymm2,ymm3/mem256","C4 RXB.01 X.src1.1.01 5C /r");