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@@ -22,6 +22,8 @@ CONST
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DefaultDMASize = 20; (* default size of ISA DMA area in KB *)
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+ IsCooperative*= FALSE;
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+
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CONST
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StrongChecks = FALSE; (* perform strong checks *)
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Stats* = FALSE; (* acquire statistics *)
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@@ -683,16 +685,16 @@ BEGIN
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END;
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ELSIF (vendor = "AuthenticAMD") THEN
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(* CPUID extended function 1 returns: largest extended function *)
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- CPUID((80000000H), eax, ebx, ecx, edx);
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+ CPUID(LONGINT (80000000H), eax, ebx, ecx, edx);
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largestFunction := SYSTEM.VAL(LONGINT, eax - {31}); (* remove sign *)
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IF (largestFunction >= 8) THEN
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(* CPUID extended function 8 returns: *)
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- CPUID((80000008H), eax, ebx, ecx, edx);
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+ CPUID(LONGINT (80000008H), eax, ebx, ecx, edx);
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coresPerProcessor := SYSTEM.VAL(LONGINT, ecx * {0..7}) + 1;
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threadsPerCore := logicalProcessorCount DIV coresPerProcessor;
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ELSIF (largestFunction >= 1) THEN
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(* CPUID extended function 1 returns CmpLegacy bit in ecx *)
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- CPUID((80000001H), eax, ebx, ecx, edx);
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+ CPUID(LONGINT (80000001H), eax, ebx, ecx, edx);
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IF 1 IN ecx THEN (* CmpLegacy bit set -> no hyperthreading *)
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coresPerProcessor := logicalProcessorCount;
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threadsPerCore := 1;
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@@ -959,7 +961,7 @@ END AllocateDMA;
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(* Check if the specified address is RAM. *)
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PROCEDURE IsRAM(adr: ADDRESS): BOOLEAN;
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-CONST Pattern1 = (0BEEFC0DEH); Pattern2 = (0AA55FF00H);
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+CONST Pattern1 = LONGINT (0BEEFC0DEH); Pattern2 = LONGINT (0AA55FF00H);
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VAR save, x: LONGINT; ok: BOOLEAN;
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BEGIN
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ok := FALSE;
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@@ -1613,13 +1615,13 @@ BEGIN
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IF TraceVerbose THEN
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Acquire (TraceOutput);
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Trace.String("Mapping ");
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- Trace.IntSuffix(SHORT(size), 1, "B"); Trace.String(" at ");
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+ Trace.IntSuffix(size, 1, "B"); Trace.String(" at ");
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Trace.Address (physAdr); Trace.String (" - "); Trace.Address (physAdr+size-1);
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IF virtAdr = NilAdr THEN
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Trace.String(" failed")
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ELSE
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Trace.String (" to "); Trace.Address (virtAdr);
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- IF ofs # 0 THEN Trace.String (", offset "); Trace.Int(SHORT(ofs), 0) END
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+ IF ofs # 0 THEN Trace.String (", offset "); Trace.Int(ofs, 0) END
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END;
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Trace.Ln;
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Release (TraceOutput);
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@@ -2786,7 +2788,7 @@ BEGIN
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IF (i > 31) OR ~(i IN {8, 10..14, 17}) THEN a := ADDRESSOF(glue[i][0]) (* include PUSH 0 *)
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ELSE a := ADDRESSOF(glue[i][2]) (* skip PUSH 0, processor supplies error code *)
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END;
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- idt[i].offsetBits0to15 := SHORT (SHORT(a MOD 10000H));
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+ idt[i].offsetBits0to15 := INTEGER(a MOD 10000H);
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(* IRQ0 must be at level 0 because time slicing in Objects needs to set interrupted process' ESP *)
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(* all irq's are handled at level 0, because of priority experiment in Objects.FieldIRQ *)
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IF TRUE (* (i < IRQ0) OR (i > IRQ15) OR (i = IRQ0) OR (i = IRQ0 + 1)*) THEN
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@@ -2796,8 +2798,8 @@ BEGIN
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idt[i].selector := User64CodeSel; (* gdt[3] -> conformant segment => level 0 or 3 *)
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idt[i].gateType := SYSTEM.VAL(INTEGER, 08E00H) (* present, DPL 0, system, 64-bit interrupt gate *)
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END;
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- idt[i].offsetBits16to31 := SHORT (SHORT(a DIV 10000H));
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- idt[i].offsetBits32to63 := SHORT(a DIV 100000000H);
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+ idt[i].offsetBits16to31 := INTEGER(a DIV 10000H);
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+ idt[i].offsetBits32to63 := LONGINT(a DIV 100000000H);
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idt[i].reserved := 0;
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END
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END InitInterrupts;
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negelef