瀏覽代碼

Added back in support for inline assembler using CODE .. WITH IN .. OUT .. END

Working example:

TYPE Vector8= ARRAY 8 OF REAL;

PROCEDURE - TestP2(VAR a: Vector8; VAR b: Vector8): Vector8;
BEGIN
	CODE
		VSUBPS C,A,B
	WITH
		IN
		A := a;
		B := b;
		OUT
		RETURN C;
	END
END TestP2;

PROCEDURE Test*;
VAR x,y,result: ARRAY 8 OF REAL; i: LONGINT;
BEGIN
	FOR i := 0 TO LEN(x)-1 DO
		x[i] := i;
		y[i] := i*i;
	END;
	result := TestP2(x,y);
	(*	TestP(x,y,result);*)
	FOR i := 0 TO LEN(x)-1 DO
		TRACE(ENTIER(x[i]), ENTIER(y[i]), ENTIER(result[i]));
	END;
END Test;


git-svn-id: https://svn.inf.ethz.ch/svn/lecturers/a2/trunk@7552 8c9fc860-2736-0410-a75d-ab315db34111
felixf 7 年之前
父節點
當前提交
dad7129d9a
共有 2 個文件被更改,包括 18 次插入1 次删除
  1. 1 1
      source/FoxAMD64Assembler.Mod
  2. 17 0
      source/FoxAMDBackend.Mod

+ 1 - 1
source/FoxAMD64Assembler.Mod

@@ -2721,7 +2721,7 @@ TYPE
 	BEGIN
 	BEGIN
 		IF (left.type # right.type) OR (left.sizeInBytes # right.sizeInBytes) OR (left.symbol # right.symbol) THEN RETURN FALSE END;
 		IF (left.type # right.type) OR (left.sizeInBytes # right.sizeInBytes) OR (left.symbol # right.symbol) THEN RETURN FALSE END;
 		CASE left.type OF
 		CASE left.type OF
-			reg8,reg16,reg32,reg64,segReg,CRn,DRn,sti,xmm,mmx: RETURN left.register = right.register
+			reg8,reg16,reg32,reg64,segReg,CRn,DRn,sti,xmm,mmx,ymm: RETURN left.register = right.register
 			| imm,ioffset: RETURN (left.val = right.val) & ((left.symbol.name="") OR (left.displacement = right.displacement))
 			| imm,ioffset: RETURN (left.val = right.val) & ((left.symbol.name="") OR (left.displacement = right.displacement))
 			| mem:RETURN (left.register = right.register) & (left.displacement = right.displacement) & (left.index = right.index) & (left.scale = right.scale)
 			| mem:RETURN (left.register = right.register) & (left.displacement = right.displacement) & (left.index = right.index) & (left.scale = right.scale)
 			| pntr1616,pntr1632: RETURN (left.selector=right.selector) & (left.offset=right.offset)
 			| pntr1616,pntr1632: RETURN (left.selector=right.selector) & (left.offset=right.offset)

+ 17 - 0
source/FoxAMDBackend.Mod

@@ -32,6 +32,8 @@ CONST
 	ST0=InstructionSet.regST0;
 	ST0=InstructionSet.regST0;
 	XMM0 = InstructionSet.regXMM0;
 	XMM0 = InstructionSet.regXMM0;
 	XMM7 = InstructionSet.regXMM7;
 	XMM7 = InstructionSet.regXMM7;
+	YMM0 = InstructionSet.regYMM0;
+	YMM7 = InstructionSet.regYMM7;
 
 
 	Low=0; High=1;
 	Low=0; High=1;
 
 
@@ -142,6 +144,7 @@ TYPE
 				toVirtual[index MOD 4 + EAX] := split;
 				toVirtual[index MOD 4 + EAX] := split;
 				toVirtual[index MOD 4 + AX] := split;
 				toVirtual[index MOD 4 + AX] := split;
 			ELSIF (index >= XMM0) & (index <= XMM7) THEN (* vector register *)
 			ELSIF (index >= XMM0) & (index <= XMM7) THEN (* vector register *)
+			ELSIF (index >= YMM0) & (index <= YMM7) THEN (* vector register *)
 			ELSE Assert( (index >=InstructionSet.regST0) & (index <= InstructionSet.regST7 ),"not a float register"); (* floats *)
 			ELSE Assert( (index >=InstructionSet.regST0) & (index <= InstructionSet.regST7 ),"not a float register"); (* floats *)
 			END;
 			END;
 		END Allocate;
 		END Allocate;
@@ -199,6 +202,7 @@ TYPE
 					toVirtual[index MOD 4 + AX] := free;
 					toVirtual[index MOD 4 + AX] := free;
 				END;
 				END;
 			ELSIF (index >= XMM0) & (index <= XMM7) THEN (* vector register *)
 			ELSIF (index >= XMM0) & (index <= XMM7) THEN (* vector register *)
+			ELSIF (index >= YMM0) & (index <= YMM7) THEN (* vector register *)
 			ELSE Assert( (index >=InstructionSet.regST0) & (index <= InstructionSet.regST7 ),"not a float register"); (* floats *)
 			ELSE Assert( (index >=InstructionSet.regST0) & (index <= InstructionSet.regST7 ),"not a float register"); (* floats *)
 			END;
 			END;
 		END Free;
 		END Free;
@@ -243,6 +247,8 @@ TYPE
 			IF (type.length > 1) THEN
 			IF (type.length > 1) THEN
 				IF (* (type.form = IntermediateCode.Float) &*)  (type.sizeInBits<=32) & (type.length =4) THEN
 				IF (* (type.form = IntermediateCode.Float) &*)  (type.sizeInBits<=32) & (type.length =4) THEN
 					i := Get(XMM7, XMM0);
 					i := Get(XMM7, XMM0);
+				ELSIF (* (type.form = IntermediateCode.Float) &*)  (type.sizeInBits<=32) & (type.length =8) THEN
+					i := Get(YMM7, YMM0);
 				ELSE
 				ELSE
 					HALT(100)
 					HALT(100)
 				END
 				END
@@ -368,6 +374,7 @@ TYPE
 				toVirtual[index MOD 32 + EAX] := split;
 				toVirtual[index MOD 32 + EAX] := split;
 				toVirtual[index MOD 32 + AX] := split;
 				toVirtual[index MOD 32 + AX] := split;
 			ELSIF (index >= XMM0) & (index <= XMM7) THEN (* vector register *)
 			ELSIF (index >= XMM0) & (index <= XMM7) THEN (* vector register *)
+			ELSIF (index >= YMM0) & (index <= YMM7) THEN (* vector register *)
 			ELSE Assert( (index >=InstructionSet.regST0) & (index <= InstructionSet.regST7 ),"not a float register"); (* floats *)
 			ELSE Assert( (index >=InstructionSet.regST0) & (index <= InstructionSet.regST7 ),"not a float register"); (* floats *)
 			END;
 			END;
 		END Allocate;
 		END Allocate;
@@ -406,6 +413,7 @@ TYPE
 				toVirtual[index MOD 32 + EAX] := free;
 				toVirtual[index MOD 32 + EAX] := free;
 				toVirtual[index MOD 32 + AX] := free;
 				toVirtual[index MOD 32 + AX] := free;
 			ELSIF (index >= XMM0) & (index <= XMM7) THEN (* vector register *)
 			ELSIF (index >= XMM0) & (index <= XMM7) THEN (* vector register *)
+			ELSIF (index >= YMM0) & (index <= YMM7) THEN (* vector register *)
 			ELSE Assert( (index >=InstructionSet.regST0) & (index <= InstructionSet.regST7 ),"not a float register"); (* floats *)
 			ELSE Assert( (index >=InstructionSet.regST0) & (index <= InstructionSet.regST7 ),"not a float register"); (* floats *)
 			END;
 			END;
 		END Free;
 		END Free;
@@ -660,6 +668,15 @@ TYPE
 					ELSIF  (type.sizeInBits = 8) THEN
 					ELSIF  (type.sizeInBits = 8) THEN
 						SpecialMove(InstructionSet.opMOVD, InstructionSet.opMOVD, TRUE, dest, src, type);
 						SpecialMove(InstructionSet.opMOVD, InstructionSet.opMOVD, TRUE, dest, src, type);
 					END;
 					END;
+				ELSIF type.length = 8 THEN
+					(*ASSERT(type.form = IntermediateCode.Float);*)
+					IF (*(type.form = IntermediateCode.Float) & *) (type.sizeInBits = 32) THEN
+					SpecialMove(InstructionSet.opVMOVUPS, InstructionSet.opVMOVUPS, TRUE, dest, src, type);
+					ELSIF (type.sizeInBits = 16) THEN
+						SpecialMove(InstructionSet.opVMOVQ, InstructionSet.opVMOVQ, TRUE, dest, src, type);
+					ELSIF  (type.sizeInBits = 8) THEN
+						SpecialMove(InstructionSet.opVMOVD, InstructionSet.opVMOVD, TRUE, dest, src, type);
+					END;
 				ELSE
 				ELSE
 					(*
 					(*
 					ASSERT(type.form = IntermediateCode.Float);
 					ASSERT(type.form = IntermediateCode.Float);