Disabled single-byte INC and DEC instructions which are interpreted as REX prefix in 64-bit mode

git-svn-id: https://svn.inf.ethz.ch/svn/lecturers/a2/trunk@7824 8c9fc860-2736-0410-a75d-ab315db34111

source/FoxAMD64InstructionSet.Mod

@@ -3266,8 +3266,8 @@ VAR
 		AddInstruction(opCWDE, "", "98", {optO32}, {cpu386});
 		AddInstruction(opDAA, "", "27", {optNot64}, {cpu8086});
 		AddInstruction(opDAS, "", "2F", {optNot64}, {cpu8086});
-		AddInstruction(opDEC, "reg16", "48rw", {optO16}, {cpu8086});
-		AddInstruction(opDEC, "reg32", "48rd", {optO32}, {cpu386});
+		AddInstruction(opDEC, "reg16", "48rw", {optO16,optNot64}, {cpu8086});
+		AddInstruction(opDEC, "reg32", "48rd", {optO32,optNot64}, {cpu386});
 		AddInstruction(opDEC, "reg/mem8", "FE/1", {}, {cpu8086});
 		AddInstruction(opDEC, "reg/mem16", "FF/1", {optO16}, {cpu8086});
 		AddInstruction(opDEC, "reg/mem32", "FF/1", {optO32}, {cpu386});
@@ -3471,8 +3471,8 @@ VAR
 		AddInstruction(opIN, "AL,DX", "EC", {}, {cpu8086});
 		AddInstruction(opIN, "AX,DX", "ED", {optO16}, {cpu8086});
 		AddInstruction(opIN, "EAX,DX", "ED", {optO32}, {cpu386});
-		AddInstruction(opINC, "reg16", "40rw", {optO16}, {cpu8086});
-		AddInstruction(opINC, "reg32", "40rd", {optO32}, {cpu386});
+		AddInstruction(opINC, "reg16", "40rw", {optO16,optNot64}, {cpu8086});
+		AddInstruction(opINC, "reg32", "40rd", {optO32,optNot64}, {cpu386});
 		AddInstruction(opINC, "reg/mem8", "FE/0", {}, {cpu8086});
 		AddInstruction(opINC, "reg/mem16", "FF/0", {optO16}, {cpu8086});
 		AddInstruction(opINC, "reg/mem32", "FF/0", {optO32}, {cpu386});