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Added useful MaskIn function
Corrected GPFSEL for Board LED


git-svn-id: https://svn.inf.ethz.ch/svn/lecturers/a2/trunk@6447 8c9fc860-2736-0410-a75d-ab315db34111

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Modificáronse 3 ficheiros con 16 adicións e 55 borrados
  1. 0 52
      source/ARM.ARMRuntime.Mod
  2. 15 2
      source/RPI.CPU.Mod
  3. 1 1
      source/RPI.Environment.Mod

+ 0 - 52
source/ARM.ARMRuntime.Mod

@@ -315,50 +315,6 @@ TYPE
 	*)
 	END DivModU64;
 
-	(* ---- FLOATING POINT EMULATION ----
-	The following procedures are used in case the target platform does not feature a math coprocessor (aka VFP unit).
-	Most of the code was taken from the Minos FPU emulation module "FPU.Mos".
-
-	Note that parameters and return types are declared as integers, even though they do contain floating point values
-	according to the IEEE standard.
-	*)
-
-	(** Tests for 0.0 (+0 or -0)
-	- corresponds to SYSTEM.NULL **)
-	PROCEDURE IsZeroF32(float: FLOAT32): BOOLEAN;
-	CODE
-		LDR R0, [FP, #+float] ; R0 := float
-		BIC R0, R0, #S ; clear the sign bit
-		CMP R0, #0 ; IF R0 = 0
-		MOVEQ R0, #1 ; THEN RETURN TRUE
-		MOVNE R0, #0 ; ELSE RETURN FALSE
-	END IsZeroF32;
-
-	(** Serves to obtain the sign for products and quotients.
-	- corresponds to SYSTEM.XOR **)
-	PROCEDURE SignXorF32(left, right: FLOAT32): FLOAT32;
-	CODE
-		LDR R0, [FP, #+left] ; R0 := left
-		LDR R1, [FP, #+right] ; R1: = right
-		EOR R0, R0, R1 ; R0 := R0 xor R1
-		AND R0, R0, #S ; clear all bits except the sign bit
-	END SignXorF32;
-
-	(** multiplies two 32-bit unsigned integer to produce a 64-bit result: [resultLow | resultHigh] = left * right
-	- corresponds to SYSTEM.MULD (but the low and high part of the result are passed explicitly) **)
-	PROCEDURE MulD(VAR resultLow, resultHigh: FLOAT32; left, right: FLOAT32);
-	CODE
-		LDR R2, [FP, #+resultLow] ; R2 := address of resultLow
-		LDR R3, [FP, #+resultHigh] ; R3: = address of resultHigh
-		LDR R4, [FP, #+left] ; R4 := left
-		LDR R5, [FP, #+right] ; R5: = right
-
-		UMULL R0, R1, R4, R5
-
-		STR R0, [R4, #+0]
-		STR R1, [R5, #+0]
-	END MulD;
-
 	PROCEDURE NegF32*(float: FLOAT32): FLOAT32;
 	CODE
 		LDR R0, [FP, #+float] ; R0 := float
@@ -585,14 +541,6 @@ TYPE
 		END ;
 		RETURN x
 	END ConvF32S32;
-	
-	(** whether x < y
-	- note that this operation should rather be done by direct code emission of the backend
-	**)
-	PROCEDURE LessThanF32(x, y: FLOAT32): BOOLEAN;
-	BEGIN
-		HALT(200)
-	END LessThanF32;
 
 	(* ---- STRING OPERATIONS ---- *)
 

+ 15 - 2
source/RPI.CPU.Mod

@@ -105,8 +105,9 @@ END Clean;
 (* hardware registers *)
 CONST WDOG* = 03F100024H; RSTC* = 03F10001CH; PASSWORD = 05A000000H; FULLRESET = 000000020H;
 
-CONST GPFSEL0* = 03F200004H; FSEL0* = 0; FSEL1* = 3; FSEL2* = 6; FSEL3* = 9; FSEL4* = 12; FSEL5* = 15; FSEL6* = 18; FSEL7* = 21; FSEL8* = 24; FSEL9* = 27;
-CONST GPFSEL1* = 03F200008H; FSEL10* = 0; FSEL11* = 3; FSEL12* = 6; FSEL13* = 9; FSEL14* = 12; FSEL15* = 15; FSEL16* = 18; FSEL17* = 21; FSEL18* = 24; FSEL19* = 27;
+CONST GPFSEL0* = 03F200000H; FSEL0* = 0; FSEL1* = 3; FSEL2* = 6; FSEL3* = 9; FSEL4* = 12; FSEL5* = 15; FSEL6* = 18; FSEL7* = 21; FSEL8* = 24; FSEL9* = 27;
+CONST GPFSEL1* = 03F200004H; FSEL10* = 0; FSEL11* = 3; FSEL12* = 6; FSEL13* = 9; FSEL14* = 12; FSEL15* = 15; FSEL16* = 18; FSEL17* = 21; FSEL18* = 24; FSEL19* = 27;
+			GPFSEL2* = 03F200008H; GPFSEL3* = 03F20000CH; GPFSEL4* = 03F200010H; GPFSEL5* = 03F200014H; 
 CONST GPSET0* = 03F20001CH; GPSET1* = 03F200020H;
 CONST GPCLR0* = 03F200028H; GPCLR1* = 03F20002CH;
 CONST GPPUD* = 03F200094H; PUD* = 0;
@@ -174,6 +175,18 @@ CODE
 	STR	R4, [R2, #0]
 END Unmask;
 
+(* combined mask / unmask: clear mask and set value *)
+PROCEDURE MaskIn-(register: ADDRESS; mask, value: SET);
+CODE
+	LDR	R2, [FP, #register]
+	LDR	R3, [FP, #mask]
+	LDR	R4, [FP, #value]
+	LDR	R5, [R2, #0]
+	BIC	R5, R5, R3
+	ORR R5, R5, R4 
+	STR	R5, [R2, #0]
+END MaskIn;
+	
 (* interrupt handling *)
 CONST Interrupts* = 7;
 CONST UndefinedInstruction* = 1; SoftwareInterrupt* = 2; PrefetchAbort* = 3; DataAbort* = 4; IRQ* = 5; FIQ* = 6;

+ 1 - 1
source/RPI.Environment.Mod

@@ -97,7 +97,7 @@ END HandleTimer;
 
 PROCEDURE LED- (status: BOOLEAN);
 BEGIN {UNCOOPERATIVE, UNCHECKED}
-	CPU.Mask (CPU.GPFSEL1, {18});
+	CPU.MaskIn (CPU.GPFSEL4, {21..23}, {21});
 	IF status THEN CPU.WriteMask (CPU.GPSET1, {15}) ELSE CPU.WriteMask (CPU.GPCLR1, {15}) END;
 END LED;