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@@ -0,0 +1,471 @@
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+(* Runtime support for CPU internals *)
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+(* Copyright (C) Florian Negele *)
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+
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+MODULE CPU;
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+
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+IMPORT SYSTEM;
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+
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+CONST StackSize* = 4096;
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+CONST Quantum* = 100000;
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+CONST CacheLineSize* = 32;
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+CONST StackDisplacement* = 0;
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+
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+PROCEDURE Backoff-;
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+CODE
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+ MOV R2, #0x100
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+loop:
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+ SUBS R2, R2, #1
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+ BNE loop
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+END Backoff;
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+
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+(* cpu control *)
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+PROCEDURE Delay- (cycles: SIZE);
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+CODE
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+ LDR R2, [FP, #cycles]
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+delay:
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+ SUBS R2, R2, #1
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+ BNE delay
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+END Delay;
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+
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+PROCEDURE {NORETURN} Reset-;
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+BEGIN {UNCOOPERATIVE, UNCHECKED}
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+ WriteWord (WDOG_CONTROL, LSH (0, CLKSEL) + LSH (0, CRV) + LSH (0248H, CKEY));
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+ WriteWord (WDOG_MODE, LSH (1, WDEN) + LSH (1, RSTEN) + LSH (0ABCH, ZKEY));
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+ Halt;
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+END Reset;
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+
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+PROCEDURE {NORETURN} Halt-;
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+CODE
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+ MRS R2, CPSR
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+ ORR R2, R2, #0b1100000
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+ MSR CPSR_c, r2
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+ WFI
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+END Halt;
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+
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+PROCEDURE -SaveResult-;
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+CODE
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+ STMDB SP!, {R0, R1}
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+END SaveResult;
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+
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+PROCEDURE -RestoreResultAndReturn-;
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+CODE
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+ LDMIA SP!, {R0, R1}
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+ ADD SP, FP, #4
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+ LDMIA SP!, {FP, PC}
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+END RestoreResultAndReturn;
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+
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+(* hardware registers *)
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+CONST PSS_RST_CTRL* = 0F8000200H; SOFT_RST* = 0;
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+
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+CONST UART_RST_CTRL* = 0F8000228H; UART0_CPU1X_RST* = 0; UART1_CPU1X_RST* = 1; UART0_REF_RST* = 2; UART1_REF_RST* = 3;
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+
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+CONST UART_REF_CLK* = 50000000;
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+CONST UART0* = 0E0000000H; UART1* = 0E0001000H;
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+CONST Control_reg0* = 000H; RXRST* = 0; TXRST* = 1; RXEN* = 2; RXDIS* = 3; TXEN* = 4; TXDIS* = 5;
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+CONST mode_reg0* = 004H; CHMOD* = 8; NBSTOP* = 6; PAR* = 3; CHRL* = 1; CLKS* = 0;
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+CONST Intrpt_dis_reg0* = 00CH;
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+CONST Baud_rate_gen_reg0* = 018H; CD* = 0;
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+CONST Channel_sts_reg0* = 02CH; TXEMPTY* = 3; TXFULL* = 4;
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+CONST Baud_rate_divider_reg0* = 034H; BDIV* = 0;
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+CONST TX_RX_FIFO0* = 030H; FIFO* = 0;
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+
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+CONST Global_Timer_Counter_Register0* = 0F8F00200H;
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+CONST Global_Timer_Counter_Register1* = 0F8F00204H;
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+
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+CONST WDOG_MODE* = 0F8005000H; WDEN* = 0; RSTEN* = 1; ZKEY* = 12;
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+CONST WDOG_CONTROL* = 0F8005004H; CLKSEL* = 0; CRV* = 2; CKEY* = 14;
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+
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+PROCEDURE ReadWord- (register: ADDRESS): WORD;
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+CODE
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+ LDR R2, [FP, #register]
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+ LDR R0, [R2, #0]
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+END ReadWord;
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+
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+PROCEDURE ReadMask- (register: ADDRESS): SET;
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+CODE
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+ LDR R2, [FP, #register]
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+ LDR R0, [R2, #0]
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+END ReadMask;
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+
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+PROCEDURE WriteWord- (register: ADDRESS; value: ADDRESS);
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+CODE
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+ LDR R2, [FP, #register]
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+ LDR R3, [FP, #value]
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+ STR R3, [R2, #0]
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+END WriteWord;
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+
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+PROCEDURE WriteMask- (register: ADDRESS; value: SET);
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+CODE
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+ LDR R2, [FP, #register]
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+ LDR R3, [FP, #value]
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+ STR R3, [R2, #0]
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+END WriteMask;
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+
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+PROCEDURE Mask- (register: ADDRESS; value: SET);
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+CODE
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+ LDR R2, [FP, #register]
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+ LDR R3, [FP, #value]
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+ LDR R4, [R2, #0]
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+ ORR R4, R4, R3
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+ STR R4, [R2, #0]
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+END Mask;
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+
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+PROCEDURE Unmask- (register: ADDRESS; value: SET);
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+CODE
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+ LDR R2, [FP, #register]
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+ LDR R3, [FP, #value]
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+ LDR R4, [R2, #0]
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+ BIC R4, R4, R3
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+ STR R4, [R2, #0]
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+END Unmask;
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+
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+(* combined mask / unmask: clear mask and set value *)
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+PROCEDURE MaskIn-(register: ADDRESS; mask, value: SET);
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+CODE
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+ LDR R2, [FP, #register]
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+ LDR R3, [FP, #mask]
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+ LDR R4, [FP, #value]
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+ LDR R5, [R2, #0]
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+ BIC R5, R5, R3
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+ ORR R5, R5, R4
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+ STR R5, [R2, #0]
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+END MaskIn;
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+
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+(* interrupt handling *)
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+CONST Interrupts* = 7;
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+CONST UndefinedInstruction* = 1; SoftwareInterrupt* = 2; PrefetchAbort* = 3; DataAbort* = 4; IRQ* = 5; FIQ* = 6;
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+
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+TYPE InterruptHandler* = PROCEDURE (index: SIZE);
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+
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+VAR handlers: ARRAY Interrupts OF InterruptHandler;
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+
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+PROCEDURE InstallInterrupt- (handler: InterruptHandler; index: SIZE): InterruptHandler;
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+VAR previous: InterruptHandler;
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+BEGIN {UNCOOPERATIVE, UNCHECKED}
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+ ASSERT (handler # NIL); ASSERT (index < Interrupts);
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+ REPEAT previous := CAS (handlers[index], NIL, NIL) UNTIL CAS (handlers[index], previous, handler) = previous;
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+ RETURN previous;
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+END InstallInterrupt;
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+
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+PROCEDURE HandleInterrupt (index: SIZE);
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+BEGIN {UNCOOPERATIVE, UNCHECKED}
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+ SYSTEM.SetActivity (NIL);
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+ IF handlers[index] # NIL THEN handlers[index] (index) ELSE HALT (1234) END;
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+END HandleInterrupt;
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+
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+PROCEDURE DisableInterrupt- (index: SIZE);
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+VAR previous: InterruptHandler;
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+BEGIN {UNCOOPERATIVE, UNCHECKED}
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+ ASSERT (index < Interrupts);
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+ REPEAT previous := CAS (handlers[index], NIL, NIL) UNTIL CAS (handlers[index], previous, NIL) = previous;
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+END DisableInterrupt;
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+
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+PROCEDURE Initialize-;
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+CODE
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+ ADD R2, PC, #vector-$-8
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+ MOV R3, #0
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+ ADD R4, R3, #vector_end - vector
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+copy:
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+ CMP R3, R4
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+ BEQ vector_end
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+ LDR r5, [R2], #4
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+ STR r5, [R3], #4
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+ B copy
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+vector:
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+ LDR PC, [PC, #header-$-8]
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+ LDR PC, [PC, #undefined_instruction-$-8]
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+ LDR PC, [PC, #software_interrupt-$-8]
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+ LDR PC, [PC, #prefetch_abort-$-8]
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+ LDR PC, [PC, #data_abort-$-8]
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+ MOV R0, R0
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+ LDR PC, [PC, #irq-$-8]
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+fiq:
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+ STMDB SP!, {R0, R1, R2, R3, R4, R5, R6, R7, LR}
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+ MOV R2, #UndefinedInstruction
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+ STR R2, [SP, #-4]!
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+ LDR R2, [PC, #handle-$-8]
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+ BLX R2
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+ ADD SP, SP, #4
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+ LDMIA SP!, {R0, R1, R2, R3, R4, R5, R6, R7, LR}
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+ SUBS PC, LR, #4
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+header:
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+ d32 0x8000
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+undefined_instruction:
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+ d32 UndefinedInstructionHandler
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+software_interrupt:
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+ d32 SoftwareInterruptHandler
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+prefetch_abort:
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+ d32 PrefetchAbortHandler
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+data_abort:
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+ d32 DataAbortHandler
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+irq:
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+ d32 IRQHandler
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+handle:
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+ d32 HandleInterrupt
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+vector_end:
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+ MOV R2, #0b10001
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+ MSR CPSR_c, R2
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+ MOV SP, #0x7000
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+ MOV R2, #0b10010
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+ MSR CPSR_c, R2
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+ MOV SP, #0x6000
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+ MOV R2, #0b10111
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+ MSR CPSR_c, R2
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+ MOV SP, #0x5000
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+ MOV R2, #0b11011
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+ MSR CPSR_c, R2
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+ MOV SP, #0x4000
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+ MOV R2, #0b10011
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+ MSR CPSR_c, R2
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+END Initialize;
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+
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+PROCEDURE {NOPAF} UndefinedInstructionHandler;
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+CODE
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+ STMDB SP!, {R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR}
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+ MOV R2, #UndefinedInstruction
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+ STR R2, [SP, #-4]!
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+ LDR R2, [PC, #handle-$-8]
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+ BLX R2
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+ ADD SP, SP, #4
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+ LDMIA SP!, {R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR}
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+ MOVS PC, LR
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+handle:
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+ d32 HandleInterrupt
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+END UndefinedInstructionHandler;
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+
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+PROCEDURE {NOPAF} SoftwareInterruptHandler;
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+CODE
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+ STMDB SP!, {R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR}
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+ MOV R2, #SoftwareInterrupt
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+ STR R2, [SP, #-4]!
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+ LDR R2, [PC, #handle-$-8]
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+ BLX R2
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+ ADD SP, SP, #4
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+ LDMIA SP!, {R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR}
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+ MOVS PC, LR
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+handle:
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+ d32 HandleInterrupt
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+END SoftwareInterruptHandler;
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+
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+PROCEDURE {NOPAF} PrefetchAbortHandler;
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+CODE
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+ STMDB SP!, {R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR}
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+ MOV R2, #PrefetchAbort
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+ STR R2, [SP, #-4]!
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+ LDR R2, [PC, #handle-$-8]
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+ BLX R2
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+ ADD SP, SP, #4
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+ LDMIA SP!, {R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR}
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+ SUBS PC, LR, #4
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+handle:
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+ d32 HandleInterrupt
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+END PrefetchAbortHandler;
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+
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+PROCEDURE {NOPAF} DataAbortHandler;
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+CODE
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+ STMDB SP!, {R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR}
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+ MOV R2, #DataAbort
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+ STR R2, [SP, #-4]!
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+ LDR R2, [PC, #handle-$-8]
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+ BLX R2
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+ ADD SP, SP, #4
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+ LDMIA SP!, {R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR}
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+ SUBS PC, LR, #4
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+handle:
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+ d32 HandleInterrupt
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+END DataAbortHandler;
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+
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+PROCEDURE {NOPAF} IRQHandler;
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+CODE
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+ STMDB SP!, {R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR}
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+ MOV R2, #IRQ
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+ STR R2, [SP, #-4]!
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+ LDR R2, [PC, #handle-$-8]
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+ BLX R2
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+ ADD SP, SP, #4
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+ LDMIA SP!, {R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR}
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+ SUBS PC, LR, #4
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+handle:
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+ d32 HandleInterrupt
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+END IRQHandler;
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+
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+(* compiler intrinsics *)
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+TYPE ULONGINT = LONGINT; (* alias to make distinction between signed and unsigned more clear *)
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+TYPE UHUGEINT = HUGEINT;
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+
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+PROCEDURE DivS8*(left, right: SHORTINT): SHORTINT;
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+VAR result, dummy: LONGINT;
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+BEGIN {UNCOOPERATIVE, UNCHECKED} DivModS32(left, right, result, dummy); RETURN SHORTINT(result)
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+END DivS8;
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+
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+PROCEDURE DivS16*(left, right: INTEGER): INTEGER;
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+VAR result, dummy: LONGINT;
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+BEGIN {UNCOOPERATIVE, UNCHECKED} DivModS32(left, right, result, dummy); RETURN INTEGER(result)
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+END DivS16;
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+
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+PROCEDURE DivS32*(left, right: LONGINT): LONGINT;
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+VAR result, dummy: LONGINT;
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+BEGIN {UNCOOPERATIVE, UNCHECKED} DivModS32(left, right, result, dummy); RETURN result
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+END DivS32;
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+
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+PROCEDURE DivU32*(left, right: ULONGINT): ULONGINT;
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+VAR result, dummy: LONGINT;
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+BEGIN {UNCOOPERATIVE, UNCHECKED} DivModU32(left, right, result, dummy); RETURN result
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+END DivU32;
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+
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+PROCEDURE DivS64*(left, right: HUGEINT): HUGEINT;
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+VAR result, dummy: HUGEINT;
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+BEGIN {UNCOOPERATIVE, UNCHECKED} DivModS64(left, right, result, dummy); RETURN result
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+END DivS64;
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+
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+PROCEDURE ModS8*(left, right: SHORTINT): SHORTINT;
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+VAR result, dummy: LONGINT;
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+BEGIN {UNCOOPERATIVE, UNCHECKED} DivModS32(left, right, dummy, result); RETURN SHORTINT(result)
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+END ModS8;
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+
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+PROCEDURE ModS16*(left, right: INTEGER): INTEGER;
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+VAR result, dummy: LONGINT;
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+BEGIN {UNCOOPERATIVE, UNCHECKED} DivModS32(left, right, dummy, result); RETURN INTEGER(result)
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+END ModS16;
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+
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+PROCEDURE ModS32*(left, right: LONGINT): LONGINT;
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+VAR result, dummy: LONGINT;
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+BEGIN {UNCOOPERATIVE, UNCHECKED} DivModS32(left, right, dummy, result); RETURN result
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+END ModS32;
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+
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+PROCEDURE ModU32*(left, right: ULONGINT): ULONGINT;
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+VAR result, dummy: LONGINT;
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+BEGIN {UNCOOPERATIVE, UNCHECKED} DivModU32(left, right, dummy, result); RETURN result
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+END ModU32;
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+
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+PROCEDURE ModS64*(left, right: HUGEINT): HUGEINT;
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+VAR result, dummy: HUGEINT;
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+BEGIN {UNCOOPERATIVE, UNCHECKED}
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+ DivModS64(left, right, dummy, result); RETURN result
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+END ModS64;
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+
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+(* signed division and modulus
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+- note: this implements the mathematical definition of DIV and MOD in contrast to the symmetric one
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+*)
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+PROCEDURE DivModS32(dividend, divisor: LONGINT; VAR quotient, remainder: LONGINT);
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+BEGIN {UNCOOPERATIVE, UNCHECKED}
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+ ASSERT(divisor > 0);
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+ IF dividend >= 0 THEN
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+ DivModU32(dividend, divisor, quotient, remainder)
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+ ELSE
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+ dividend := -dividend;
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+ DivModU32(dividend, divisor, quotient, remainder);
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+ quotient := -quotient;
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+ IF remainder # 0 THEN
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+ DEC(quotient);
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+ remainder := divisor - remainder
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+ END
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+ END
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+END DivModS32;
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+
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+(*
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+ Fast 32-bit unsigned integer division/modulo (author Alexey Morozov)
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+*)
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+PROCEDURE DivModU32(dividend, divisor: ULONGINT; VAR quotient, remainder: ULONGINT);
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+CODE
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+ MOV R2, #0 ; quotient will be stored in R2
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+
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+ LDR R0, [FP,#dividend] ; R0 := dividend
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+ LDR R1, [FP,#divisor] ; R1 := divisor
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+
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+ ; check for the case dividend < divisor
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+ CMP R0, R1
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+ BLT Exit ; nothing to do than setting quotient to 0 and remainder to dividend (R0)
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+
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+ CLZ R3, R0 ; R3 := clz(dividend)
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+ CLZ R4, R1 ; R4 := clz(divisor)
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+
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+ SUB R3, R4, R3 ; R2 := clz(divisor) - clz(dividend) , R2 >= 0
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+ LSL R1, R1, R3 ; scale divisor: divisor := LSH(divisor,clz(divisor)-clz(dividend))
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+
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+Loop:
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+ CMP R0, R1
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+ ADC R2, R2, R2
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+ SUBCS R0, R0, R1
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+ LSR R1, R1, #1
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+ SUBS R3, R3, #1
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+ BPL Loop
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+
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+ ; R0 holds the remainder
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+
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+Exit:
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+ LDR R1, [FP,#quotient] ; R1 := address of quotient
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+ LDR R3, [FP,#remainder] ; R3 := address of remainder
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+
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+ STR R2, [R1,#0] ; quotient := R1
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+ STR R0, [R3,#0] ; remainder := R0
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+END DivModU32;
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+
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+(* signed division and modulus
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+- note: this implements the mathematical definition of DIV and MOD in contrast to the symmetric one
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+*)
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+PROCEDURE DivModS64*(dividend, divisor: HUGEINT; VAR quotient, remainder: HUGEINT);
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+BEGIN {UNCOOPERATIVE, UNCHECKED}
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+ ASSERT(divisor > 0);
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+ IF dividend >= 0 THEN
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+ DivModU64(dividend, divisor, quotient, remainder)
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+ ELSE
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+ dividend := -dividend;
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+ DivModU64(dividend, divisor, quotient, remainder);
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+ quotient := -quotient;
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+ IF remainder # 0 THEN
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+ DEC(quotient);
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+ remainder := divisor - remainder
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+ END
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+ END
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+END DivModS64;
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+
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+(* Count leading zeros in a binary representation of a given 64-bit integer number *)
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+PROCEDURE Clz64*(x: UHUGEINT): LONGINT;
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+CODE
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+ ; high-half
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+ LDR R1, [FP,#x+4]
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+ CMP R1, #0 ; if high-half is zero count leading zeros of the low-half
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+ BEQ LowHalf
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+
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+ CLZ R0, R1
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+ B Exit
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+
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+ ; low-half
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+LowHalf:
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+ LDR R1, [FP,#x]
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+ CLZ R0, R1
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+ ADD R0, R0, #32 ; add 32 zeros from the high-half
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+
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+Exit:
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+END Clz64;
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+
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+(*
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+ Fast 64-bit unsigned integer division/modulo (Alexey Morozov)
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+*)
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+PROCEDURE DivModU64*(dividend, divisor: UHUGEINT; VAR quotient, remainder: UHUGEINT);
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+VAR m: LONGINT;
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+BEGIN {UNCOOPERATIVE, UNCHECKED}
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+ quotient := 0;
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+
|
|
|
+ IF dividend = 0 THEN remainder := 0; RETURN; END;
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|
|
+ IF dividend < divisor THEN remainder := dividend; RETURN; END;
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|
|
+
|
|
|
+ m := Clz64(divisor) - Clz64(dividend);
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|
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+ ASSERT(m >= 0);
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+
|
|
|
+ divisor := LSH(divisor,m);
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|
|
+ WHILE m >= 0 DO
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|
|
+ quotient := LSH(quotient,1);
|
|
|
+ IF dividend >= divisor THEN
|
|
|
+ INC(quotient);
|
|
|
+ DEC(dividend,divisor);
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|
|
+ END;
|
|
|
+ divisor := LSH(divisor,-1);
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|
|
+ DEC(m);
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|
|
+ END;
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|
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+
|
|
|
+ remainder := dividend;
|
|
|
+END DivModU64;
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+
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+END CPU.
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eth.negelef