Fixed explicit encoding of operand-size override prefix

git-svn-id: https://svn.inf.ethz.ch/svn/lecturers/a2/trunk@8674 8c9fc860-2736-0410-a75d-ab315db34111

source/FoxAMD64InstructionSet.Mod

@@ -3015,11 +3015,11 @@ VAR
 		AddInstruction(opADD, "reg/mem16,simm8", "83/0ib", {optO16}, {cpu8086});
 		AddInstruction(opADD, "reg/mem32,simm8", "83/0ib", {optO32}, {cpu386});
 		AddInstruction(opADD, "reg/mem64,simm8", "83/0ib", {}, {cpuAMD64});
-		AddInstruction(opADDPD, "xmm1,xmm2/mem128", "660F58/r", {}, {cpuSSE2});
+		AddInstruction(opADDPD, "xmm1,xmm2/mem128", "0F58/r", {optPOP}, {cpuSSE2});
 		AddInstruction(opADDPS, "xmm1,xmm2/mem128", "0F58/r", {}, {cpuSSE});
 		AddInstruction(opADDSD, "xmm1,xmm2/mem64", "F20F58/r", {}, {cpuSSE2});
 		AddInstruction(opADDSS, "xmm1,xmm2/mem32", "F30F58/r", {}, {cpuSSE});
-		AddInstruction(opADDSUBPD, "xmm1,xmm2/mem128", "660FD0/r", {}, {cpuSSE3});
+		AddInstruction(opADDSUBPD, "xmm1,xmm2/mem128", "0FD0/r", {optPOP}, {cpuSSE3});
 		AddInstruction(opADDSUBPS, "xmm1,xmm2/mem128", "F20FD0/r", {}, {cpuSSE3});
 		AddInstruction(opAND, "reg/mem8,reg8", "20/r", {}, {cpu8086});
 		AddInstruction(opAND, "reg/mem16,reg16", "21/r", {optO16}, {cpu8086});
@@ -3040,9 +3040,9 @@ VAR
 		AddInstruction(opAND, "reg/mem16,simm8", "83/4ib", {optO16}, {cpu8086});
 		AddInstruction(opAND, "reg/mem32,simm8", "83/4ib", {optO32}, {cpu386});
 		AddInstruction(opAND, "reg/mem64,simm8", "83/4ib", {}, {cpuAMD64});
-		AddInstruction(opANDNPD, "xmm1,xmm2/mem128", "660F55/r", {}, {cpuSSE2});
+		AddInstruction(opANDNPD, "xmm1,xmm2/mem128", "0F55/r", {optPOP}, {cpuSSE2});
 		AddInstruction(opANDNPS, "xmm1,xmm2/mem128", "0F55/r", {}, {cpuSSE});
-		AddInstruction(opANDPD, "xmm1,xmm2/mem128", "660F54/r", {}, {cpuSSE2});
+		AddInstruction(opANDPD, "xmm1,xmm2/mem128", "0F54/r", {optPOP}, {cpuSSE2});
 		AddInstruction(opANDPS, "xmm1,xmm2/mem128", "0F54/r", {}, {cpuSSE});
 		AddInstruction(opARPL, "reg/mem16,reg16", "63/r", {}, {cpu286,cpuPrivileged});
 		AddInstruction(opBOUND, "reg16,mem16&mem16", "62/r", {optO16,optNot64}, {cpu186});
@@ -3207,7 +3207,7 @@ VAR
 		AddInstruction(opCMP, "reg/mem16,simm8", "83/7ib", {optO16}, {cpu8086});
 		AddInstruction(opCMP, "reg/mem32,simm8", "83/7ib", {optO32}, {cpu386});
 		AddInstruction(opCMP, "reg/mem64,simm8", "83/7ib", {}, {cpuAMD64});
-		AddInstruction(opCMPPD, "xmm1,xmm2/mem128,uimm8", "660FC2/rib", {}, {cpuSSE2});
+		AddInstruction(opCMPPD, "xmm1,xmm2/mem128,uimm8", "0FC2/rib", {optPOP}, {cpuSSE2});
 		AddInstruction(opCMPPS, "xmm1,xmm2/mem128,uimm8", "0FC2/rib", {}, {cpuSSE});
 		AddInstruction(opCMPS, "mem8,mem8", "A6", {}, {cpu8086});
 		AddInstruction(opCMPS, "mem16,mem16", "A7", {optO16}, {cpu8086});
@@ -3225,22 +3225,22 @@ VAR
 		AddInstruction(opCMPXCHG, "reg/mem64,reg64", "0FB1/r", {}, {cpuAMD64});
 		AddInstruction(opCMPXCHG16B, "mem128", "0FC7/1m1", {}, {cpuSSE2});
 		AddInstruction(opCMPXCHG8B, "mem64", "0FC7/1m6", {}, {cpuPentium});
-		AddInstruction(opCOMISD, "xmm1,xmm2/mem64", "660F2F/r", {}, {cpuSSE2});
+		AddInstruction(opCOMISD, "xmm1,xmm2/mem64", "0F2F/r", {optPOP}, {cpuSSE2});
 		AddInstruction(opCOMISS, "xmm1,xmm2/mem32", "0F2F/r", {}, {cpuSSE});
 		AddInstruction(opCPUID, "", "0FA2", {}, {cpuPentium});
 		AddInstruction(opCQO, "", "99", {optO64}, {cpuAMD64});
 		AddInstruction(opCVTDQ2PD, "xmm1,xmm2/mem64", "F30FE6/r", {}, {cpuSSE2});
 		AddInstruction(opCVTDQ2PS, "xmm1,xmm2/mem128", "0F5B/r", {}, {cpuSSE2});
 		AddInstruction(opCVTPD2DQ, "xmm1,xmm2/mem128", "F20FE6/r", {}, {cpuSSE2});
-		AddInstruction(opCVTPD2PI, "mmx,xmm2/mem128", "660F2D/r", {}, {cpuSSE2});
-		AddInstruction(opCVTPD2PI, "mmx,xmm2/mem128", "660F2D/r", {}, {cpuSSE2});
-		AddInstruction(opCVTPD2PI, "mmx,xmm/mem128", "660F2C/r", {}, {cpuSSE2});
-		AddInstruction(opCVTPD2PS, "xmm1,xmm2/mem128", "660F5A/r", {}, {cpuSSE2});
-		AddInstruction(opCVTPI2PD, "xmm,mmx/mem64", "660F2A/r", {}, {cpuSSE2});
-		AddInstruction(opCVTPI2PD, "xmm,mmx/mem64", "660F2A/r", {}, {cpuSSE2});
+		AddInstruction(opCVTPD2PI, "mmx,xmm2/mem128", "0F2D/r", {optPOP}, {cpuSSE2});
+		AddInstruction(opCVTPD2PI, "mmx,xmm2/mem128", "0F2D/r", {optPOP}, {cpuSSE2});
+		AddInstruction(opCVTPD2PI, "mmx,xmm/mem128", "0F2C/r", {optPOP}, {cpuSSE2});
+		AddInstruction(opCVTPD2PS, "xmm1,xmm2/mem128", "0F5A/r", {optPOP}, {cpuSSE2});
+		AddInstruction(opCVTPI2PD, "xmm,mmx/mem64", "0F2A/r", {optPOP}, {cpuSSE2});
+		AddInstruction(opCVTPI2PD, "xmm,mmx/mem64", "0F2A/r", {optPOP}, {cpuSSE2});
 		AddInstruction(opCVTPI2PS, "xmm,mmx/mem64", "0F2A/r", {}, {cpuSSE});
 		AddInstruction(opCVTPI2PS, "xmm,mmx/mem64", "0F2A/r", {}, {cpuSSE});
-		AddInstruction(opCVTPS2DQ, "xmm1,xmm2/mem128", "660F5B/r", {}, {cpuSSE2});
+		AddInstruction(opCVTPS2DQ, "xmm1,xmm2/mem128", "0F5B/r", {optPOP}, {cpuSSE2});
 		AddInstruction(opCVTPS2PD, "xmm1,xmm2/mem64", "0F5A/r", {}, {cpuSSE2});
 		AddInstruction(opCVTPS2PI, "mmx,xmm/mem64", "0F2D/r", {}, {cpuSSE});
 		AddInstruction(opCVTPS2PI, "mmx,xmm/mem64", "0F2D/r", {}, {cpuSSE});
@@ -3254,8 +3254,8 @@ VAR
 		AddInstruction(opCVTSS2SD, "xmm1,xmm2/mem32", "F30F5A/r", {}, {cpuSSE2});
 		AddInstruction(opCVTSS2SI, "reg32,xmm2/mem32", "F30F2D/r", {}, {cpuSSE});
 		AddInstruction(opCVTSS2SI, "reg64,xmm2/mem32", "F30F2D/r", {}, {cpuAMD64,cpuSSE});
-		AddInstruction(opCVTTPD2DQ, "xmm1,xmm2/mem128", "660FE6/r", {}, {cpuSSE2});
-		AddInstruction(opCVTTPD2PI, "mmx,xmm/mem128", "660F2C/r", {}, {cpuSSE2});
+		AddInstruction(opCVTTPD2DQ, "xmm1,xmm2/mem128", "0FE6/r", {optPOP}, {cpuSSE2});
+		AddInstruction(opCVTTPD2PI, "mmx,xmm/mem128", "0F2C/r", {optPOP}, {cpuSSE2});
 		AddInstruction(opCVTTPS2DQ, "xmm1,xmm2/mem128", "F30F5B/r", {}, {cpuSSE2});
 		AddInstruction(opCVTTPS2PI, "mmx,xmm/mem64", "0F2C/r", {}, {cpuSSE});
 		AddInstruction(opCVTTPS2PI, "mmx,xmm/mem64", "0F2C/r", {}, {cpuSSE});
@@ -3277,7 +3277,7 @@ VAR
 		AddInstruction(opDIV, "reg/mem16", "F7/6", {optO16}, {cpu8086});
 		AddInstruction(opDIV, "reg/mem32", "F7/6", {optO32}, {cpu386});
 		AddInstruction(opDIV, "reg/mem64", "F7/6", {}, {cpuAMD64});
-		AddInstruction(opDIVPD, "xmm1,xmm2/mem128", "660F5E/r", {}, {cpuSSE2});
+		AddInstruction(opDIVPD, "xmm1,xmm2/mem128", "0F5E/r", {optPOP}, {cpuSSE2});
 		AddInstruction(opDIVPS, "xmm1,xmm2/mem128", "0F5E/r", {}, {cpuSSE});
 		AddInstruction(opDIVSD, "xmm1,xmm2/mem64", "F20F5E/r", {}, {cpuSSE2});
 		AddInstruction(opDIVSS, "xmm1,xmm2/mem32", "F30F5E/r", {}, {cpuSSE});
@@ -3444,10 +3444,10 @@ VAR
 		AddInstruction(opFXTRACT, "", "D9F4", {}, {cpu8086,cpuFPU});
 		AddInstruction(opFYL2X, "", "D9F1", {}, {cpu8086,cpuFPU});
 		AddInstruction(opFYL2XP1, "", "D9F9", {}, {cpu8086,cpuFPU});
-		AddInstruction(opHADDPD, "xmm1,xmm2/mem128", "660F7C/r", {}, {cpuSSE3});
+		AddInstruction(opHADDPD, "xmm1,xmm2/mem128", "0F7C/r", {optPOP}, {cpuSSE3});
 		AddInstruction(opHADDPS, "xmm1,xmm2/mem128", "F20F7C/r", {}, {cpuSSE3});
 		AddInstruction(opHLT, "", "F4", {}, {cpu8086,cpuPrivileged});
-		AddInstruction(opHSUBPD, "xmm1,xmm2/mem128", "660F7D/r", {}, {cpuSSE3});
+		AddInstruction(opHSUBPD, "xmm1,xmm2/mem128", "0F7D/r", {optPOP}, {cpuSSE3});
 		AddInstruction(opHSUBPS, "xmm1,xmm2/mem128", "F20F7D/r", {}, {cpuSSE3});
 		AddInstruction(opIDIV, "reg/mem8", "F6/7", {}, {cpu8086});
 		AddInstruction(opIDIV, "reg/mem16", "F7/7", {optO16}, {cpu8086});
@@ -3640,14 +3640,14 @@ VAR
 		AddInstruction(opLSS, "reg16,mem16:16", "0FB2/r", {optO16}, {cpu386});
 		AddInstruction(opLSS, "reg32,mem16:32", "0FB2/r", {optO32}, {cpu386});
 		AddInstruction(opLTR, "reg/mem16", "0F00/3", {}, {cpu286,cpuPrivileged});
-		AddInstruction(opMASKMOVDQU, "xmm1,xmm2", "660FF7/r", {}, {cpuSSE2});
+		AddInstruction(opMASKMOVDQU, "xmm1,xmm2", "0FF7/r", {optPOP}, {cpuSSE2});
 		AddInstruction(opMASKMOVQ, "mmx1,mmx2", "0FF7/r", {}, {cpuMMX});
-		AddInstruction(opMAXPD, "xmm1,xmm2/mem128", "660F5F/r", {}, {cpuSSE2});
+		AddInstruction(opMAXPD, "xmm1,xmm2/mem128", "0F5F/r", {optPOP}, {cpuSSE2});
 		AddInstruction(opMAXPS, "xmm1,xmm2/mem128", "0F5F/r", {}, {cpuSSE});
 		AddInstruction(opMAXSD, "xmm1,xmm2/mem64", "F20F5F/r", {}, {cpuSSE2});
 		AddInstruction(opMAXSS, "xmm1,xmm2/mem32", "F30F5F/r", {}, {cpuSSE});
 		AddInstruction(opMFENCE, "", "0FAEF0", {}, {cpuSSE2});
-		AddInstruction(opMINPD, "xmm1,xmm2/mem128", "660F5D/r", {}, {cpuSSE2});
+		AddInstruction(opMINPD, "xmm1,xmm2/mem128", "0F5D/r", {optPOP}, {cpuSSE2});
 		AddInstruction(opMINPS, "xmm1,xmm2/mem128", "0F5D/r", {}, {cpuSSE});
 		AddInstruction(opMINSD, "xmm1,xmm2/mem64", "F20F5D/r", {}, {cpuSSE2});
 		AddInstruction(opMINSS, "xmm1,xmm2/mem32", "F30F5D/r", {}, {cpuSSE});
@@ -3693,14 +3693,14 @@ VAR
 		AddInstruction(opMOV, "reg/mem16,imm16", "C7/0iw", {optO16}, {cpu8086});
 		AddInstruction(opMOV, "reg/mem32,imm32", "C7/0id", {optO32}, {cpu386});
 		AddInstruction(opMOV, "reg/mem64,simm32", "C7/0id", {}, {cpuAMD64});
-		AddInstruction(opMOVAPD, "xmm1,xmm2/mem128", "660F28/r", {}, {cpuSSE2});
-		AddInstruction(opMOVAPD, "xmm1/mem128,xmm2", "660F29/r", {}, {cpuSSE2});
+		AddInstruction(opMOVAPD, "xmm1,xmm2/mem128", "0F28/r", {optPOP}, {cpuSSE2});
+		AddInstruction(opMOVAPD, "xmm1/mem128,xmm2", "0F29/r", {optPOP}, {cpuSSE2});
 		AddInstruction(opMOVAPS, "xmm1,xmm2/mem128", "0F28/r", {}, {cpuSSE});
 		AddInstruction(opMOVAPS, "xmm1/mem128,xmm2", "0F29/r", {}, {cpuSSE});
-		AddInstruction(opMOVD, "xmm,reg/mem32", "660F6E/r", {}, {cpuSSE2});
-		AddInstruction(opMOVD, "xmm,reg/mem64", "660F6E/r", {}, {cpuAMD64,cpuSSE2});
-		AddInstruction(opMOVD, "reg/mem32,xmm", "660F7E/r", {}, {cpuSSE2});
-		AddInstruction(opMOVD, "reg/mem64,xmm", "660F7E/r", {}, {cpuAMD64,cpuSSE2});
+		AddInstruction(opMOVD, "xmm,reg/mem32", "0F6E/r", {optPOP}, {cpuSSE2});
+		AddInstruction(opMOVD, "xmm,reg/mem64", "0F6E/r", {optPOP}, {cpuAMD64,cpuSSE2});
+		AddInstruction(opMOVD, "reg/mem32,xmm", "0F7E/r", {optPOP}, {cpuSSE2});
+		AddInstruction(opMOVD, "reg/mem64,xmm", "0F7E/r", {optPOP}, {cpuAMD64,cpuSSE2});
 		AddInstruction(opMOVD, "mmx,reg/mem32", "0F6E/r", {}, {cpuMMX});
 		AddInstruction(opMOVD, "mmx,reg/mem64", "0F6E/r", {}, {cpuAMD64,cpuMMX});
 		AddInstruction(opMOVD, "reg/mem32,mmx", "0F7E/r", {}, {cpuMMX});
@@ -3710,31 +3710,31 @@ VAR
 		AddInstructionV(opVMOVDDUP,"ymm1,ymm2/mem256","C4 RXB.00001 X.1111.1.11 12 /r");
 		AddInstruction(opMOVDQ2Q, "mmx,xmm", "F20FD6/r", {}, {cpuSSE2});
 		AddInstruction(opMOVDQ2Q, "mmx,xmm", "F20FD6/r", {}, {cpuSSE2});
-		AddInstruction(opMOVDQA, "xmm1,xmm2/mem128", "660F6F/r", {}, {cpuSSE2});
-		AddInstruction(opMOVDQA, "xmm1/mem128,xmm2", "660F7F/r", {}, {cpuSSE2});
+		AddInstruction(opMOVDQA, "xmm1,xmm2/mem128", "0F6F/r", {optPOP}, {cpuSSE2});
+		AddInstruction(opMOVDQA, "xmm1/mem128,xmm2", "0F7F/r", {optPOP}, {cpuSSE2});
 		AddInstruction(opMOVDQU, "xmm1,xmm2/mem128", "F30F6F/r", {}, {cpuSSE2});
 		AddInstruction(opMOVDQU, "xmm1/mem128,xmm2", "F30F7F/r", {}, {cpuSSE2});
 		AddInstruction(opMOVHLPS, "xmm1,xmm2", "0F12/r", {}, {cpuSSE});
-		AddInstruction(opMOVHPD, "xmm,mem64", "660F16/r", {}, {cpuSSE2});
-		AddInstruction(opMOVHPD, "mem64,xmm", "660F17/r", {}, {cpuSSE2});
+		AddInstruction(opMOVHPD, "xmm,mem64", "0F16/r", {optPOP}, {cpuSSE2});
+		AddInstruction(opMOVHPD, "mem64,xmm", "0F17/r", {optPOP}, {cpuSSE2});
 		AddInstruction(opMOVHPS, "xmm,mem64", "0F16/r", {}, {cpuSSE});
 		AddInstruction(opMOVHPS, "mem64,xmm", "0F17/r", {}, {cpuSSE});
 		AddInstruction(opMOVLHPS, "xmm1,xmm2", "0F16/r", {}, {cpuSSE});
-		AddInstruction(opMOVLPD, "xmm,mem64", "660F12/r", {}, {cpuSSE2});
-		AddInstruction(opMOVLPD, "mem64,xmm", "660F13/r", {}, {cpuSSE2});
+		AddInstruction(opMOVLPD, "xmm,mem64", "0F12/r", {optPOP}, {cpuSSE2});
+		AddInstruction(opMOVLPD, "mem64,xmm", "0F13/r", {optPOP}, {cpuSSE2});
 		AddInstruction(opMOVLPS, "xmm,mem64", "0F12/r", {}, {cpuSSE});
 		AddInstruction(opMOVLPS, "mem64,xmm", "0F13/r", {}, {cpuSSE});
-		AddInstruction(opMOVMSKPD, "reg32,xmm", "660F50/r", {}, {cpuSSE2});
+		AddInstruction(opMOVMSKPD, "reg32,xmm", "0F50/r", {optPOP}, {cpuSSE2});
 		AddInstruction(opMOVMSKPS, "reg32,xmm", "0F50/r", {}, {cpuSSE});
 		AddInstruction(opMOVMSKPS, "reg32,xmm", "0F50/r", {}, {cpuSSE});
-		AddInstruction(opMOVNTDQ, "mem128,xmm", "660FE7/r", {}, {cpuSSE2});
+		AddInstruction(opMOVNTDQ, "mem128,xmm", "0FE7/r", {optPOP}, {cpuSSE2});
 		AddInstruction(opMOVNTI, "mem32,reg32", "0FC3/r", {}, {cpuSSE2});
 		AddInstruction(opMOVNTI, "mem64,reg64", "0FC3/r", {}, {cpuAMD64,cpuSSE2});
-		AddInstruction(opMOVNTPD, "mem128,xmm", "660F2B/r", {}, {cpuSSE2});
+		AddInstruction(opMOVNTPD, "mem128,xmm", "0F2B/r", {}, {cpuSSE2});
 		AddInstruction(opMOVNTPS, "mem128,xmm", "0F2B/r", {}, {cpuSSE});
 		AddInstruction(opMOVNTQ, "mem64,mmx", "0FE7/r", {}, {cpuMMX});
 		AddInstruction(opMOVQ, "xmm1,xmm2/mem64", "F30F7E/r", {}, {cpuSSE2});
-		AddInstruction(opMOVQ, "xmm1/mem64,xmm2", "660FD6/r", {}, {cpuSSE2});
+		AddInstruction(opMOVQ, "xmm1/mem64,xmm2", "0FD6/r", {optPOP}, {cpuSSE2});
 		AddInstruction(opMOVQ, "mmx1,mmx2/mem64", "0F6F/r", {}, {cpuMMX});
 		AddInstruction(opMOVQ, "mmx1/mem64,mmx2", "0F7F/r", {}, {cpuMMX});
 		AddInstruction(opMOVQ2DQ, "xmm,mmx", "F30FD6/r", {}, {cpuSSE2});
@@ -3759,8 +3759,8 @@ VAR
 		AddInstruction(opMOVSX, "reg32,reg/mem16", "0FBF/r", {optO32}, {cpu386});
 		AddInstruction(opMOVSX, "reg64,reg/mem16", "0FBF/r", {}, {cpuAMD64});
 		AddInstruction(opMOVSXD, "reg64,reg/mem32", "63/r", {}, {cpuAMD64});
-		AddInstruction(opMOVUPD, "xmm1,xmm2/mem128", "660F10/r", {}, {cpuSSE2});
-		AddInstruction(opMOVUPD, "xmm1/mem128,xmm2", "660F11/r", {}, {cpuSSE2});
+		AddInstruction(opMOVUPD, "xmm1,xmm2/mem128", "0F10/r", {optPOP}, {cpuSSE2});
+		AddInstruction(opMOVUPD, "xmm1/mem128,xmm2", "0F11/r", {optPOP}, {cpuSSE2});
 		AddInstruction(opMOVUPS, "xmm1,xmm2/mem128", "0F10/r", {}, {cpuSSE});
 		AddInstruction(opMOVUPS, "xmm1/mem128,xmm2", "0F11/r", {}, {cpuSSE});
 		AddInstruction(opMOVZX, "reg16,reg/mem8", "0FB6/r", {optO16}, {cpu386});
@@ -3776,7 +3776,7 @@ VAR
 		AddInstruction(opMUL, "AX,reg/mem16", "F7/4", {optO16}, {cpu8086});
 		AddInstruction(opMUL, "EAX,reg/mem32", "F7/4", {optO32}, {cpu386});
 		AddInstruction(opMUL, "RAX,reg/mem64", "F7/4", {}, {cpuAMD64});
-		AddInstruction(opMULPD, "xmm1,xmm2/mem128", "660F59/r", {}, {cpuSSE2});
+		AddInstruction(opMULPD, "xmm1,xmm2/mem128", "0F59/r", {optPOP}, {cpuSSE2});
 		AddInstruction(opMULPS, "xmm1,xmm2/mem128", "0F59/r", {}, {cpuSSE});
 		AddInstruction(opMULSD, "xmm1,xmm2/mem64", "F20F59/r", {}, {cpuSSE2});
 		AddInstruction(opMULSS, "xmm1,xmm2/mem32", "F30F59/r", {}, {cpuSSE});
@@ -3808,7 +3808,7 @@ VAR
 		AddInstruction(opOR, "reg/mem16,simm8", "83/1ib", {optO16}, {cpu8086});
 		AddInstruction(opOR, "reg/mem32,simm8", "83/1ib", {optO32}, {cpu386});
 		AddInstruction(opOR, "reg/mem64,simm8", "83/1ib", {}, {cpuAMD64});
-		AddInstruction(opORPD, "xmm1,xmm2/mem128", "660F56/r", {}, {cpuSSE2});
+		AddInstruction(opORPD, "xmm1,xmm2/mem128", "0F56/r", {optPOP}, {cpuSSE2});
 		AddInstruction(opORPS, "xmm1,xmm2/mem128", "0F56/r", {}, {cpuSSE});
 		AddInstruction(opOUT, "uimm8,AL", "E6ib", {}, {cpu8086});
 		AddInstruction(opOUT, "uimm8,AX", "E7ib", {optO16}, {cpu8086});
@@ -3822,51 +3822,51 @@ VAR
 		AddInstruction(opOUTSB, "", "6E", {}, {cpu186});
 		AddInstruction(opOUTSD, "", "6F", {optO32}, {cpu386});
 		AddInstruction(opOUTSW, "", "6F", {optO16}, {cpu186});
-		AddInstruction(opPACKSSDW, "xmm1,xmm2/mem128", "660F6B/r", {}, {cpuSSE2});
+		AddInstruction(opPACKSSDW, "xmm1,xmm2/mem128", "0F6B/r", {optPOP}, {cpuSSE2});
 		AddInstruction(opPACKSSDW, "mmx1,mmx2/mem64", "0F6B/r", {}, {cpuMMX});
-		AddInstruction(opPACKSSWB, "xmm1,xmm2/mem128", "660F63/r", {}, {cpuSSE2});
+		AddInstruction(opPACKSSWB, "xmm1,xmm2/mem128", "0F63/r", {optPOP}, {cpuSSE2});
 		AddInstruction(opPACKSSWB, "mmx1,mmx2/mem64", "0F63/r", {}, {cpuMMX});
-		AddInstruction(opPACKUSWB, "xmm1,xmm2/mem128", "660F67/r", {}, {cpuSSE2});
+		AddInstruction(opPACKUSWB, "xmm1,xmm2/mem128", "0F67/r", {optPOP}, {cpuSSE2});
 		AddInstruction(opPACKUSWB, "mmx1,mmx2/mem64", "0F67/r", {}, {cpuMMX});
-		AddInstruction(opPADDB, "xmm1,xmm2/mem128", "660FFC/r", {}, {cpuSSE2});
+		AddInstruction(opPADDB, "xmm1,xmm2/mem128", "0FFC/r", {optPOP}, {cpuSSE2});
 		AddInstruction(opPADDB, "mmx1,mmx2/mem64", "0FFC/r", {}, {cpuMMX});
-		AddInstruction(opPADDD, "xmm1,xmm2/mem128", "660FFE/r", {}, {cpuSSE2});
+		AddInstruction(opPADDD, "xmm1,xmm2/mem128", "0FFE/r", {optPOP}, {cpuSSE2});
 		AddInstruction(opPADDD, "mmx1,mmx2/mem64", "0FFE/r", {}, {cpuMMX});
-		AddInstruction(opPADDQ, "xmm1,xmm2/mem128", "660FD4/r", {}, {cpuSSE2});
+		AddInstruction(opPADDQ, "xmm1,xmm2/mem128", "0FD4/r", {optPOP}, {cpuSSE2});
 		AddInstruction(opPADDQ, "mmx1,mmx2/mem64", "0FD4/r", {}, {cpuMMX});
-		AddInstruction(opPADDSB, "xmm1,xmm2/mem128", "660FEC/r", {}, {cpuSSE2});
+		AddInstruction(opPADDSB, "xmm1,xmm2/mem128", "0FEC/r", {optPOP}, {cpuSSE2});
 		AddInstruction(opPADDSB, "mmx1,mmx2/mem64", "0FEC/r", {}, {cpuMMX});
-		AddInstruction(opPADDSW, "xmm1,xmm2/mem128", "660FED/r", {}, {cpuSSE2});
+		AddInstruction(opPADDSW, "xmm1,xmm2/mem128", "0FED/r", {optPOP}, {cpuSSE2});
 		AddInstruction(opPADDSW, "mmx1,mmx2/mem64", "0FED/r", {}, {cpuMMX});
-		AddInstruction(opPADDUSB, "xmm1,xmm2/mem128", "660FDC/r", {}, {cpuSSE2});
+		AddInstruction(opPADDUSB, "xmm1,xmm2/mem128", "0FDC/r", {optPOP}, {cpuSSE2});
 		AddInstruction(opPADDUSB, "mmx1,mmx2/mem64", "0FDC/r", {}, {cpuMMX});
-		AddInstruction(opPADDUSW, "xmm1,xmm2/mem128", "660FDD/r", {}, {cpuSSE2});
+		AddInstruction(opPADDUSW, "xmm1,xmm2/mem128", "0FDD/r", {optPOP}, {cpuSSE2});
 		AddInstruction(opPADDUSW, "mmx1,mmx2/mem64", "0FDD/r", {}, {cpuMMX});
-		AddInstruction(opPADDW, "xmm1,xmm2/mem128", "660FFD/r", {}, {cpuSSE2});
+		AddInstruction(opPADDW, "xmm1,xmm2/mem128", "0FFD/r", {optPOP}, {cpuSSE2});
 		AddInstruction(opPADDW, "mmx1,mmx2/mem64", "0FFD/r", {}, {cpuMMX});
-		AddInstruction(opPAND, "xmm1,xmm2/mem128", "660FDB/r", {}, {cpuSSE2});
+		AddInstruction(opPAND, "xmm1,xmm2/mem128", "0FDB/r", {optPOP}, {cpuSSE2});
 		AddInstruction(opPAND, "mmx1,mmx2/mem64", "0FDB/r", {}, {cpuMMX});
-		AddInstruction(opPANDN, "xmm1,xmm2/mem128", "660FDF/r", {}, {cpuSSE2});
+		AddInstruction(opPANDN, "xmm1,xmm2/mem128", "0FDF/r", {optPOP}, {cpuSSE2});
 		AddInstruction(opPANDN, "mmx1,mmx2/mem64", "0FDF/r", {}, {cpuMMX});
 		AddInstruction(opPAUSE, "", "F390", {}, {cpuSSE2});
-		AddInstruction(opPAVGB, "xmm1,xmm2/mem128", "660FE0/r", {}, {cpuSSE2});
+		AddInstruction(opPAVGB, "xmm1,xmm2/mem128", "0FE0/r", {optPOP}, {cpuSSE2});
 		AddInstruction(opPAVGB, "mmx1,mmx2/mem64", "0FE0/r", {}, {cpuMMX});
 		AddInstruction(opPAVGUSB, "mmx1,mmx2/mem64", "0F0F/rBF", {}, {cpu3DNow});
-		AddInstruction(opPAVGW, "xmm1,xmm2/mem128", "660FE3/r", {}, {cpuSSE2});
+		AddInstruction(opPAVGW, "xmm1,xmm2/mem128", "0FE3/r", {optPOP}, {cpuSSE2});
 		AddInstruction(opPAVGW, "mmx1,mmx2/mem64", "0FE3/r", {}, {cpuMMX});
-		AddInstruction(opPCMPEQB, "xmm1,xmm2/mem128", "660F74/r", {}, {cpuSSE2});
+		AddInstruction(opPCMPEQB, "xmm1,xmm2/mem128", "0F74/r", {optPOP}, {cpuSSE2});
 		AddInstruction(opPCMPEQB, "mmx1,mmx2/mem64", "0F74/r", {}, {cpuMMX});
-		AddInstruction(opPCMPEQD, "xmm1,xmm2/mem128", "660F76/r", {}, {cpuSSE2});
+		AddInstruction(opPCMPEQD, "xmm1,xmm2/mem128", "0F76/r", {optPOP}, {cpuSSE2});
 		AddInstruction(opPCMPEQD, "mmx1,mmx2/mem64", "0F76/r", {}, {cpuMMX});
-		AddInstruction(opPCMPEQW, "xmm1,xmm2/mem128", "660F75/r", {}, {cpuSSE2});
+		AddInstruction(opPCMPEQW, "xmm1,xmm2/mem128", "0F75/r", {optPOP}, {cpuSSE2});
 		AddInstruction(opPCMPEQW, "mmx1,mmx2/mem64", "0F75/r", {}, {cpuMMX});
-		AddInstruction(opPCMPGTB, "xmm1,xmm2/mem128", "660F64/r", {}, {cpuSSE2});
+		AddInstruction(opPCMPGTB, "xmm1,xmm2/mem128", "0F64/r", {optPOP}, {cpuSSE2});
 		AddInstruction(opPCMPGTB, "mmx1,mmx2/mem64", "0F64/r", {}, {cpuMMX});
-		AddInstruction(opPCMPGTD, "xmm1,xmm2/mem128", "660F66/r", {}, {cpuSSE2});
+		AddInstruction(opPCMPGTD, "xmm1,xmm2/mem128", "0F66/r", {optPOP}, {cpuSSE2});
 		AddInstruction(opPCMPGTD, "mmx1,mmx2/mem64", "0F66/r", {}, {cpuMMX});
-		AddInstruction(opPCMPGTW, "xmm1,xmm2/mem128", "660F65/r", {}, {cpuSSE2});
+		AddInstruction(opPCMPGTW, "xmm1,xmm2/mem128", "0F65/r", {optPOP}, {cpuSSE2});
 		AddInstruction(opPCMPGTW, "mmx1,mmx2/mem64", "0F65/r", {}, {cpuMMX});
-		AddInstruction(opPEXTRW, "reg32,xmm,uimm8", "660FC5/rib", {}, {cpuSSE2});
+		AddInstruction(opPEXTRW, "reg32,xmm,uimm8", "0FC5/rib", {optPOP}, {cpuSSE2});
 		AddInstruction(opPEXTRW, "reg32,mmx,uimm8", "0FC5/rib", {}, {cpuMMX});
 		AddInstruction(opPF2ID, "mmx1,mmx2/mem64", "0F0F/r1D", {}, {cpu3DNow});
 		AddInstruction(opPF2IW, "mmx1,mmx2/mem64", "0F0F/r1C", {}, {cpu3DNow});
@@ -3889,30 +3889,30 @@ VAR
 		AddInstruction(opPFSUBR, "mmx1,mmx2/mem64", "0F0F/rAA", {}, {cpu3DNow});
 		AddInstruction(opPI2FD, "mmx1,mmx2/mem64", "0F0F/r0D", {}, {cpu3DNow});
 		AddInstruction(opPI2FW, "mmx1,mmx2/mem64", "0F0F/r0C", {}, {cpu3DNow});
-		AddInstruction(opPINSRW, "xmm,reg/mem16,uimm8", "660FC4/rib", {}, {cpuSSE2});
-		AddInstruction(opPINSRW, "xmm,reg/mem32,uimm8", "660FC4/rib", {}, {cpuSSE2});
+		AddInstruction(opPINSRW, "xmm,reg/mem16,uimm8", "0FC4/rib", {optPOP}, {cpuSSE2});
+		AddInstruction(opPINSRW, "xmm,reg/mem32,uimm8", "0FC4/rib", {optPOP}, {cpuSSE2});
 		AddInstruction(opPINSRW, "mmx,reg/mem16,uimm8", "0FC4/rib", {}, {cpuMMX});
 		AddInstruction(opPINSRW, "mmx,reg/mem32,uimm8", "0FC4/rib", {}, {cpuMMX});
-		AddInstruction(opPMADDWD, "xmm1,xmm2/mem128", "660FF5/r", {}, {cpuSSE2});
+		AddInstruction(opPMADDWD, "xmm1,xmm2/mem128", "0FF5/r", {optPOP}, {cpuSSE2});
 		AddInstruction(opPMADDWD, "mmx1,mmx2/mem64", "0FF5/r", {}, {cpuMMX});
-		AddInstruction(opPMAXSW, "xmm1,xmm2/mem128", "660FEE/r", {}, {cpuSSE2});
+		AddInstruction(opPMAXSW, "xmm1,xmm2/mem128", "0FEE/r", {optPOP}, {cpuSSE2});
 		AddInstruction(opPMAXSW, "mmx1,mmx2/mem64", "0FEE/r", {}, {cpuMMX});
-		AddInstruction(opPMAXUB, "xmm1,xmm2/mem128", "660FDE/r", {}, {cpuSSE2});
+		AddInstruction(opPMAXUB, "xmm1,xmm2/mem128", "0FDE/r", {optPOP}, {cpuSSE2});
 		AddInstruction(opPMAXUB, "mmx1,mmx2/mem64", "0FDE/r", {}, {cpuMMX});
-		AddInstruction(opPMINSW, "xmm1,xmm2/mem128", "660FEA/r", {}, {cpuSSE2});
+		AddInstruction(opPMINSW, "xmm1,xmm2/mem128", "0FEA/r", {optPOP}, {cpuSSE2});
 		AddInstruction(opPMINSW, "mmx1,mmx2/mem64", "0FEA/r", {}, {cpuMMX});
-		AddInstruction(opPMINUB, "xmm1,xmm2/mem128", "660FDA/r", {}, {cpuSSE2});
+		AddInstruction(opPMINUB, "xmm1,xmm2/mem128", "0FDA/r", {optPOP}, {cpuSSE2});
 		AddInstruction(opPMINUB, "mmx1,mmx2/mem64", "0FDA/r", {}, {cpuMMX});
-		AddInstruction(opPMOVMSKB, "reg32,xmm", "660FD7/r", {}, {cpuSSE2});
+		AddInstruction(opPMOVMSKB, "reg32,xmm", "0FD7/r", {optPOP}, {cpuSSE2});
 		AddInstruction(opPMOVMSKB, "reg32,mmx", "0FD7/r", {}, {cpuMMX});
 		AddInstruction(opPMULHRW, "mmx1,mmx2/mem64", "0F0F/rB7", {}, {cpu3DNow});
-		AddInstruction(opPMULHUW, "xmm1,xmm2/mem128", "660FE4/r", {}, {cpuSSE2});
+		AddInstruction(opPMULHUW, "xmm1,xmm2/mem128", "0FE4/r", {optPOP}, {cpuSSE2});
 		AddInstruction(opPMULHUW, "mmx1,mmx2/mem64", "0FE4/r", {}, {cpuMMX});
-		AddInstruction(opPMULHW, "xmm1,xmm2/mem128", "660FE5/r", {}, {cpuSSE2});
+		AddInstruction(opPMULHW, "xmm1,xmm2/mem128", "0FE5/r", {optPOP}, {cpuSSE2});
 		AddInstruction(opPMULHW, "mmx1,mmx2/mem64", "0FE5/r", {}, {cpuMMX});
-		AddInstruction(opPMULLW, "xmm1,xmm2/mem128", "660FD5/r", {}, {cpuSSE2});
+		AddInstruction(opPMULLW, "xmm1,xmm2/mem128", "0FD5/r", {optPOP}, {cpuSSE2});
 		AddInstruction(opPMULLW, "mmx1,mmx2/mem64", "0FD5/r", {}, {cpuMMX});
-		AddInstruction(opPMULUDQ, "xmm1,xmm2/mem128", "660FF4/r", {}, {cpuSSE2});
+		AddInstruction(opPMULUDQ, "xmm1,xmm2/mem128", "0FF4/r", {optPOP}, {cpuSSE2});
 		AddInstruction(opPMULUDQ, "mmx1,mmx2/mem64", "0FF4/r", {}, {cpuSSE2});
 		AddInstruction(opPOP, "reg16", "58rw", {optO16}, {cpu8086});
 		AddInstruction(opPOP, "reg32", "58rd", {optO32}, {cpu386});
@@ -3931,7 +3931,7 @@ VAR
 		AddInstruction(opPOPF, "", "9D", {}, {cpu8086});
 		AddInstruction(opPOPFD, "", "9D", {optO32}, {cpu386});
 		AddInstruction(opPOPFQ, "", "9D", {}, {cpuAMD64});
-		AddInstruction(opPOR, "xmm1,xmm2/mem128", "660FEB/r", {}, {cpuSSE2});
+		AddInstruction(opPOR, "xmm1,xmm2/mem128", "0FEB/r", {optPOP}, {cpuSSE2});
 		AddInstruction(opPOR, "mmx1,mmx2/mem64", "0FEB/r", {}, {cpuMMX});
 		AddInstruction(opPREFETCH, "mem8", "0F0D/0", {}, {cpu3DNow});
 		AddInstruction(opPREFETCHNTA, "mem8", "0F18/0", {}, {cpuSSE,cpuMMX});
@@ -3939,76 +3939,76 @@ VAR
 		AddInstruction(opPREFETCHT1, "mem8", "0F18/2", {}, {cpuSSE,cpuMMX});
 		AddInstruction(opPREFETCHT2, "mem8", "0F18/3", {}, {cpuSSE,cpuMMX});
 		AddInstruction(opPREFETCHW, "mem8", "0F0D/1", {}, {cpu3DNow});
-		AddInstruction(opPSADBW, "xmm1,xmm2/mem128", "660FF6/r", {}, {cpuSSE2});
+		AddInstruction(opPSADBW, "xmm1,xmm2/mem128", "0FF6/r", {optPOP}, {cpuSSE2});
 		AddInstruction(opPSADBW, "mmx1,mmx2/mem64", "0FF6/r", {}, {cpuMMX});
-		AddInstruction(opPSHUFD, "xmm1,xmm2/mem128,uimm8", "660F70/rib", {}, {cpuSSE2});
+		AddInstruction(opPSHUFD, "xmm1,xmm2/mem128,uimm8", "0F70/rib", {optPOP}, {cpuSSE2});
 		AddInstruction(opPSHUFHW, "xmm1,xmm2/mem128,uimm8", "F30F70/rib", {}, {cpuSSE2});
 		AddInstruction(opPSHUFLW, "xmm1,xmm2/mem128,uimm8", "F20F70/rib", {}, {cpuSSE2});
 		AddInstruction(opPSHUFW, "mmx1,mmx2/mem64,imm8", "0F70/rib", {}, {cpuSSE2});
-		AddInstruction(opPSLLD, "xmm1,xmm2/mem128", "660FF2/r", {}, {cpuSSE2});
-		AddInstruction(opPSLLD, "xmm,uimm8", "660F72/6ib", {}, {cpuSSE2});
+		AddInstruction(opPSLLD, "xmm1,xmm2/mem128", "0FF2/r", {optPOP}, {cpuSSE2});
+		AddInstruction(opPSLLD, "xmm,uimm8", "0F72/6ib", {optPOP}, {cpuSSE2});
 		AddInstruction(opPSLLD, "mmx1,mmx2/mem64", "0FF2/r", {}, {cpuMMX});
 		AddInstruction(opPSLLD, "mmx,imm8", "0F72/6ib", {}, {cpuMMX});
-		AddInstruction(opPSLLDQ, "xmm,uimm8", "660F73/7ib", {}, {cpuSSE2});
-		AddInstruction(opPSLLQ, "xmm1,xmm2/mem128", "660FF3/r", {}, {cpuSSE2});
-		AddInstruction(opPSLLQ, "xmm,uimm8", "660F73/6ib", {}, {cpuSSE2});
+		AddInstruction(opPSLLDQ, "xmm,uimm8", "0F73/7ib", {optPOP}, {cpuSSE2});
+		AddInstruction(opPSLLQ, "xmm1,xmm2/mem128", "0FF3/r", {optPOP}, {cpuSSE2});
+		AddInstruction(opPSLLQ, "xmm,uimm8", "0F73/6ib", {optPOP}, {cpuSSE2});
 		AddInstruction(opPSLLQ, "mmx1,mmx2/mem64", "0FF3/r", {}, {cpuMMX});
 		AddInstruction(opPSLLQ, "mmx,imm8", "0F73/6ib", {}, {cpuMMX});
-		AddInstruction(opPSLLW, "xmm1,xmm2/mem128", "660FF1/r", {}, {cpuSSE2});
-		AddInstruction(opPSLLW, "xmm,uimm8", "660F71/6ib", {}, {cpuSSE2});
+		AddInstruction(opPSLLW, "xmm1,xmm2/mem128", "0FF1/r", {optPOP}, {cpuSSE2});
+		AddInstruction(opPSLLW, "xmm,uimm8", "0F71/6ib", {optPOP}, {cpuSSE2});
 		AddInstruction(opPSLLW, "mmx1,mmx2/mem64", "0FF1/r", {}, {cpuMMX});
 		AddInstruction(opPSLLW, "mmx,imm8", "0F71/6ib", {}, {cpuMMX});
-		AddInstruction(opPSRAD, "xmm1,xmm2/mem128", "660FE2/r", {}, {cpuSSE2});
-		AddInstruction(opPSRAD, "xmm,uimm8", "660F72/4ib", {}, {cpuSSE2});
+		AddInstruction(opPSRAD, "xmm1,xmm2/mem128", "0FE2/r", {optPOP}, {cpuSSE2});
+		AddInstruction(opPSRAD, "xmm,uimm8", "0F72/4ib", {optPOP}, {cpuSSE2});
 		AddInstruction(opPSRAD, "mmx1,mmx2/mem64", "0FE2/r", {}, {cpuMMX});
 		AddInstruction(opPSRAD, "mmx,imm8", "0F72/4ib", {}, {cpuMMX});
-		AddInstruction(opPSRAW, "xmm1,xmm2/mem128", "660FE1/r", {}, {cpuSSE2});
-		AddInstruction(opPSRAW, "xmm,uimm8", "660F71/4ib", {}, {cpuSSE2});
+		AddInstruction(opPSRAW, "xmm1,xmm2/mem128", "0FE1/r", {optPOP}, {cpuSSE2});
+		AddInstruction(opPSRAW, "xmm,uimm8", "0F71/4ib", {optPOP}, {cpuSSE2});
 		AddInstruction(opPSRAW, "mmx1,mmx2/mem64", "0FE1/r", {}, {cpuMMX});
 		AddInstruction(opPSRAW, "mmx,imm8", "0F71/4ib", {}, {cpuMMX});
-		AddInstruction(opPSRLD, "xmm1,xmm2/mem128", "660FD2/r", {}, {cpuSSE2});
-		AddInstruction(opPSRLD, "xmm,uimm8", "660F72/2ib", {}, {cpuSSE2});
+		AddInstruction(opPSRLD, "xmm1,xmm2/mem128", "0FD2/r", {optPOP}, {cpuSSE2});
+		AddInstruction(opPSRLD, "xmm,uimm8", "0F72/2ib", {optPOP}, {cpuSSE2});
 		AddInstruction(opPSRLD, "mmx1,mmx2/mem64", "0FD2/r", {}, {cpuMMX});
 		AddInstruction(opPSRLD, "mmx,imm8", "0F72/2ib", {}, {cpuMMX});
-		AddInstruction(opPSRLDQ, "xmm,uimm8", "660F73/3ib", {}, {cpuSSE2});
-		AddInstruction(opPSRLQ, "xmm1,xmm2/mem128", "660FD3/r", {}, {cpuSSE2});
-		AddInstruction(opPSRLQ, "xmm,uimm8", "660F73/2ib", {}, {cpuSSE2});
+		AddInstruction(opPSRLDQ, "xmm,uimm8", "0F73/3ib", {optPOP}, {cpuSSE2});
+		AddInstruction(opPSRLQ, "xmm1,xmm2/mem128", "0FD3/r", {optPOP}, {cpuSSE2});
+		AddInstruction(opPSRLQ, "xmm,uimm8", "0F73/2ib", {optPOP}, {cpuSSE2});
 		AddInstruction(opPSRLQ, "mmx1,mmx2/mem64", "0FD3/r", {}, {cpuMMX});
 		AddInstruction(opPSRLQ, "mmx,imm8", "0F73/2ib", {}, {cpuMMX});
-		AddInstruction(opPSRLW, "xmm1,xmm2/mem128", "660FD1/r", {}, {cpuSSE2});
-		AddInstruction(opPSRLW, "xmm,uimm8", "660F71/2ib", {}, {cpuSSE2});
+		AddInstruction(opPSRLW, "xmm1,xmm2/mem128", "0FD1/r", {optPOP}, {cpuSSE2});
+		AddInstruction(opPSRLW, "xmm,uimm8", "0F71/2ib", {optPOP}, {cpuSSE2});
 		AddInstruction(opPSRLW, "mmx1,mmx2/mem64", "0FD1/r", {}, {cpuMMX});
 		AddInstruction(opPSRLW, "mmx,imm8", "0F71/2ib", {}, {cpuMMX});
-		AddInstruction(opPSUBB, "xmm1,xmm2/mem128", "660FF8/r", {}, {cpuSSE2});
+		AddInstruction(opPSUBB, "xmm1,xmm2/mem128", "0FF8/r", {optPOP}, {cpuSSE2});
 		AddInstruction(opPSUBB, "mmx1,mmx2/mem64", "0FF8/r", {}, {cpuMMX});
-		AddInstruction(opPSUBD, "xmm1,xmm2/mem128", "660FFA/r", {}, {cpuSSE2});
+		AddInstruction(opPSUBD, "xmm1,xmm2/mem128", "0FFA/r", {optPOP}, {cpuSSE2});
 		AddInstruction(opPSUBD, "mmx1,mmx2/mem64", "0FFA/r", {}, {cpuMMX});
-		AddInstruction(opPSUBQ, "xmm1,xmm2/mem128", "660FFB/r", {}, {cpuSSE2});
+		AddInstruction(opPSUBQ, "xmm1,xmm2/mem128", "0FFB/r", {optPOP}, {cpuSSE2});
 		AddInstruction(opPSUBQ, "mmx1,mmx2/mem64", "0FFB/r", {}, {cpuMMX});
-		AddInstruction(opPSUBSB, "xmm1,xmm2/mem128", "660FE8/r", {}, {cpuSSE2});
+		AddInstruction(opPSUBSB, "xmm1,xmm2/mem128", "0FE8/r", {optPOP}, {cpuSSE2});
 		AddInstruction(opPSUBSB, "mmx1,mmx2/mem64", "0FE8/r", {}, {cpuMMX});
-		AddInstruction(opPSUBSW, "xmm1,xmm2/mem128", "660FE9/r", {}, {cpuSSE2});
+		AddInstruction(opPSUBSW, "xmm1,xmm2/mem128", "0FE9/r", {optPOP}, {cpuSSE2});
 		AddInstruction(opPSUBSW, "mmx1,mmx2/mem64", "0FE9/r", {}, {cpuMMX});
-		AddInstruction(opPSUBUSB, "xmm1,xmm2/mem128", "660FD8/r", {}, {cpuSSE2});
+		AddInstruction(opPSUBUSB, "xmm1,xmm2/mem128", "0FD8/r", {optPOP}, {cpuSSE2});
 		AddInstruction(opPSUBUSB, "mmx1,mmx2/mem64", "0FD8/r", {}, {cpuMMX});
-		AddInstruction(opPSUBUSW, "xmm1,xmm2/mem128", "660FD9/r", {}, {cpuSSE2});
+		AddInstruction(opPSUBUSW, "xmm1,xmm2/mem128", "0FD9/r", {optPOP}, {cpuSSE2});
 		AddInstruction(opPSUBUSW, "mmx1,mmx2/mem64", "0FD9/r", {}, {cpuMMX});
-		AddInstruction(opPSUBW, "xmm1,xmm2/mem128", "660FF9/r", {}, {cpuSSE2});
+		AddInstruction(opPSUBW, "xmm1,xmm2/mem128", "0FF9/r", {optPOP}, {cpuSSE2});
 		AddInstruction(opPSUBW, "mmx1,mmx2/mem64", "0FF9/r", {}, {cpuMMX});
 		AddInstruction(opPSWAPD, "mmx1,mmx2/mem64", "0F0F/rBB", {}, {cpu3DNow});
-		AddInstruction(opPUNPCKHBW, "xmm1,xmm2/mem128", "660F68/r", {}, {cpuSSE2});
+		AddInstruction(opPUNPCKHBW, "xmm1,xmm2/mem128", "0F68/r", {optPOP}, {cpuSSE2});
 		AddInstruction(opPUNPCKHBW, "mmx1,mmx2/mem64", "0F68/r", {}, {cpuMMX});
-		AddInstruction(opPUNPCKHDQ, "xmm1,xmm2/mem128", "660F6A/r", {}, {cpuSSE2});
+		AddInstruction(opPUNPCKHDQ, "xmm1,xmm2/mem128", "0F6A/r", {optPOP}, {cpuSSE2});
 		AddInstruction(opPUNPCKHDQ, "mmx1,mmx2/mem64", "0F6A/r", {}, {cpuMMX});
-		AddInstruction(opPUNPCKHQDQ, "xmm1,xmm2/mem128", "660F6D/r", {}, {cpuSSE2});
-		AddInstruction(opPUNPCKHWD, "xmm1,xmm2/mem128", "660F69/r", {}, {cpuSSE2});
+		AddInstruction(opPUNPCKHQDQ, "xmm1,xmm2/mem128", "0F6D/r", {optPOP}, {cpuSSE2});
+		AddInstruction(opPUNPCKHWD, "xmm1,xmm2/mem128", "0F69/r", {optPOP}, {cpuSSE2});
 		AddInstruction(opPUNPCKHWD, "mmx1,mmx2/mem64", "0F69/r", {}, {cpuMMX});
-		AddInstruction(opPUNPCKLBW, "xmm1,xmm2/mem128", "660F60/r", {}, {cpuSSE2});
+		AddInstruction(opPUNPCKLBW, "xmm1,xmm2/mem128", "0F60/r", {optPOP}, {cpuSSE2});
 		AddInstruction(opPUNPCKLBW, "mmx1,mmx2/mem32", "0F60/r", {}, {cpuMMX});
-		AddInstruction(opPUNPCKLDQ, "xmm1,xmm2/mem128", "660F62/r", {}, {cpuSSE2});
+		AddInstruction(opPUNPCKLDQ, "xmm1,xmm2/mem128", "0F62/r", {optPOP}, {cpuSSE2});
 		AddInstruction(opPUNPCKLDQ, "mmx1,mmx2/mem32", "0F62/r", {}, {cpuMMX});
-		AddInstruction(opPUNPCKLQDQ, "xmm1,xmm2/mem128", "660F6C/r", {}, {cpuSSE2});
-		AddInstruction(opPUNPCKLWD, "xmm1,xmm2/mem128", "660F61/r", {}, {cpuSSE2});
+		AddInstruction(opPUNPCKLQDQ, "xmm1,xmm2/mem128", "0F6C/r", {optPOP}, {cpuSSE2});
+		AddInstruction(opPUNPCKLWD, "xmm1,xmm2/mem128", "0F61/r", {optPOP}, {cpuSSE2});
 		AddInstruction(opPUNPCKLWD, "mmx1,mmx2/mem32", "0F61/r", {}, {cpuMMX});
 		AddInstruction(opPUSH, "reg16", "50rw", {optO16}, {cpu8086});
 		AddInstruction(opPUSH, "reg32", "50rd", {optO32}, {cpu386});
@@ -4031,7 +4031,7 @@ VAR
 		AddInstruction(opPUSHF, "", "9C", {}, {cpu8086});
 		AddInstruction(opPUSHFD, "", "9C", {optO32}, {cpu386});
 		AddInstruction(opPUSHFQ, "", "9C", {}, {cpuAMD64});
-		AddInstruction(opPXOR, "xmm1,xmm2/mem128", "660FEF/r", {}, {cpuSSE2});
+		AddInstruction(opPXOR, "xmm1,xmm2/mem128", "0FEF/r", {optPOP}, {cpuSSE2});
 		AddInstruction(opPXOR, "mmx1,mmx2/mem64", "0FEF/r", {}, {cpuMMX});
 		AddInstruction(opRCL, "reg/mem8,1", "D0/2", {}, {cpu8086});
 		AddInstruction(opRCL, "reg/mem8,CL", "D2/2", {}, {cpu8086});
@@ -4215,7 +4215,7 @@ VAR
 		AddInstruction(opSHRD, "reg/mem32,reg32,CL", "0FAD/r", {optO32}, {cpu386});
 		AddInstruction(opSHRD, "reg/mem64,reg64,uimm8", "0FAC/rib", {}, {cpuAMD64});
 		AddInstruction(opSHRD, "reg/mem64,reg64,CL", "0FAD/r", {}, {cpuAMD64});
-		AddInstruction(opSHUFPD, "xmm1,xmm2/mem128,uimm8", "660FC6/rib", {}, {cpuSSE2});
+		AddInstruction(opSHUFPD, "xmm1,xmm2/mem128,uimm8", "0FC6/rib", {optPOP}, {cpuSSE2});
 		AddInstruction(opSHUFPS, "xmm1,xmm2/mem128,uimm8", "0FC6/rib", {}, {cpuSSE});
 		AddInstruction(opSIDT, "mem16:32", "0F01/1", {}, {cpu286,cpuPrivileged});
 		AddInstruction(opSIDT, "mem16:64", "0F01/1", {}, {cpuAMD64,cpuPrivileged});
@@ -4228,7 +4228,7 @@ VAR
 		AddInstruction(opSMSW, "reg32", "0F01/4", {optO32}, {cpu386});
 		AddInstruction(opSMSW, "reg64", "0F01/4", {}, {cpuAMD64});
 		AddInstruction(opSMSW, "mem16", "0F01/4", {}, {cpu286});
-		AddInstruction(opSQRTPD, "xmm1,xmm2/mem128", "660F51/r", {}, {cpuSSE2});
+		AddInstruction(opSQRTPD, "xmm1,xmm2/mem128", "0F51/r", {optPOP}, {cpuSSE2});
 		AddInstruction(opSQRTPS, "xmm1,xmm2/mem128", "0F51/r", {}, {cpuSSE});
 		AddInstruction(opSQRTSD, "xmm1,xmm2/mem64", "F20F51/r", {}, {cpuSSE2});
 		AddInstruction(opSQRTSS, "xmm1,xmm2/mem32", "F30F51/r", {}, {cpuSSE});
@@ -4268,7 +4268,7 @@ VAR
 		AddInstruction(opSUB, "reg/mem16,simm8", "83/5ib", {optO16}, {cpu8086});
 		AddInstruction(opSUB, "reg/mem32,simm8", "83/5ib", {optO32}, {cpu386});
 		AddInstruction(opSUB, "reg/mem64,simm8", "83/5ib", {}, {cpuAMD64});
-		AddInstruction(opSUBPD, "xmm1,xmm2/mem128", "660F5C/r", {}, {cpuSSE2});
+		AddInstruction(opSUBPD, "xmm1,xmm2/mem128", "0F5C/r", {optPOP}, {cpuSSE2});
 		AddInstruction(opSUBPS, "xmm1,xmm2/mem128", "0F5C/r", {}, {cpuSSE});
 		AddInstruction(opSUBSD, "xmm1,xmm2/mem64", "F20F5C/r", {}, {cpuSSE2});
 		AddInstruction(opSUBSS, "xmm1,xmm2/mem32", "F30F5C/r", {}, {cpuSSE});
@@ -4289,12 +4289,12 @@ VAR
 		AddInstruction(opTEST, "reg/mem16,imm16", "F7/0iw", {optO16}, {cpu8086});
 		AddInstruction(opTEST, "reg/mem32,imm32", "F7/0id", {optO32}, {cpu386});
 		AddInstruction(opTEST, "reg/mem64,simm32", "F7/0id", {}, {cpuAMD64});
-		AddInstruction(opUCOMISD, "xmm1,xmm2/mem64", "660F2E/r", {}, {cpuSSE2});
+		AddInstruction(opUCOMISD, "xmm1,xmm2/mem64", "0F2E/r", {optPOP}, {cpuSSE2});
 		AddInstruction(opUCOMISS, "xmm1,xmm2/mem32", "0F2E/r", {}, {cpuSSE});
 		AddInstruction(opUD2, "", "0F0B", {}, {cpu286});
-		AddInstruction(opUNPCKHPD, "xmm1,xmm2/mem128", "660F15/r", {}, {cpuSSE2});
+		AddInstruction(opUNPCKHPD, "xmm1,xmm2/mem128", "0F15/r", {optPOP}, {cpuSSE2});
 		AddInstruction(opUNPCKHPS, "xmm1,xmm2/mem128", "0F15/r", {}, {cpuSSE});
-		AddInstruction(opUNPCKLPD, "xmm1,xmm2/mem128", "660F14/r", {}, {cpuSSE2});
+		AddInstruction(opUNPCKLPD, "xmm1,xmm2/mem128", "0F14/r", {optPOP}, {cpuSSE2});
 		AddInstruction(opUNPCKLPS, "xmm1,xmm2/mem128", "0F14/r", {}, {cpuSSE});
 		AddInstruction(opVERR, "reg/mem16", "0F00/4", {}, {cpu286,cpuPrivileged});
 		AddInstruction(opVERW, "reg/mem16", "0F00/5", {}, {cpu286,cpuPrivileged});
@@ -4343,7 +4343,7 @@ VAR
 		AddInstruction(opXOR, "reg/mem16,simm8", "83/6ib", {optO16}, {cpu8086});
 		AddInstruction(opXOR, "reg/mem32,simm8", "83/6ib", {optO32}, {cpu386});
 		AddInstruction(opXOR, "reg/mem64,simm8", "83/6ib", {}, {cpuAMD64});
-		AddInstruction(opXORPD, "xmm1,xmm2/mem128", "660F57/r", {}, {cpuSSE2});
+		AddInstruction(opXORPD, "xmm1,xmm2/mem128", "0F57/r", {optPOP}, {cpuSSE2});
 		AddInstruction(opXORPS, "xmm1,xmm2/mem128", "0F57/r", {}, {cpuSSE});